1 /* $NetBSD: s3c24x0_clk.c,v 1.10 2008/07/04 11:59:45 bsh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Genetec corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Genetec corporation may not be used to endorse 16 * or promote products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: s3c24x0_clk.c,v 1.10 2008/07/04 11:59:45 bsh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/atomic.h> 39 #include <sys/time.h> 40 #include <sys/timetc.h> 41 42 #include <machine/bus.h> 43 #include <machine/intr.h> 44 #include <arm/cpufunc.h> 45 46 #include <arm/s3c2xx0/s3c24x0reg.h> 47 #include <arm/s3c2xx0/s3c24x0var.h> 48 49 50 #ifndef STATHZ 51 #define STATHZ 64 52 #endif 53 54 #define TIMER_FREQUENCY(pclk) ((pclk)/16) /* divider=1/16 */ 55 56 static unsigned int timer4_reload_value; 57 static unsigned int timer4_prescaler; 58 static unsigned int timer4_mseccount; 59 60 #define usec_to_counter(t) \ 61 ((timer4_mseccount*(t))/1000) 62 63 #define counter_to_usec(c,pclk) \ 64 (((c)*timer4_prescaler*1000)/(TIMER_FREQUENCY(pclk)/1000)) 65 66 static u_int s3c24x0_get_timecount(struct timecounter *); 67 68 static struct timecounter s3c24x0_timecounter = { 69 s3c24x0_get_timecount, /* get_timecount */ 70 0, /* no poll_pps */ 71 0xffffffff, /* counter_mask */ 72 0, /* frequency */ 73 "s3c234x0", /* name */ 74 100, /* quality */ 75 NULL, /* prev */ 76 NULL, /* next */ 77 }; 78 79 static volatile uint32_t s3c24x0_base; 80 81 static u_int 82 s3c24x0_get_timecount(struct timecounter *tc) 83 { 84 struct s3c24x0_softc *sc = (struct s3c24x0_softc *) s3c2xx0_softc; 85 int save, int_pend0, int_pend1, count; 86 87 save = disable_interrupts(I32_bit); 88 89 again: 90 int_pend0 = S3C24X0_INT_TIMER4 & 91 bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_intctl_ioh, 92 INTCTL_SRCPND); 93 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_timer_ioh, 94 TIMER_TCNTO(4)); 95 96 for (;;) { 97 98 int_pend1 = S3C24X0_INT_TIMER4 & 99 bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_intctl_ioh, 100 INTCTL_SRCPND); 101 if( int_pend0 == int_pend1 ) 102 break; 103 104 /* 105 * Down counter reached to zero while we were reading 106 * timer values. do it again to get consistent values. 107 */ 108 int_pend0 = int_pend1; 109 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_timer_ioh, 110 TIMER_TCNTO(4)); 111 } 112 113 if (__predict_false(count > timer4_reload_value)) { 114 /* 115 * Buggy Hardware Warning --- sometimes timer counter 116 * reads bogus value like 0xffff. I guess it happens when 117 * the timer is reloaded. 118 */ 119 printf("Bogus value from timer counter: %d\n", count); 120 goto again; 121 } 122 123 restore_interrupts(save); 124 125 if (int_pend1) 126 count -= timer4_reload_value; 127 128 return s3c24x0_base - count; 129 } 130 131 static inline int 132 read_timer(struct s3c24x0_softc *sc) 133 { 134 int count; 135 136 do { 137 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_timer_ioh, 138 TIMER_TCNTO(4)); 139 } while ( __predict_false(count > timer4_reload_value) ); 140 141 return count; 142 } 143 144 /* 145 * delay: 146 * 147 * Delay for at least N microseconds. 148 */ 149 void 150 delay(u_int n) 151 { 152 struct s3c24x0_softc *sc = (struct s3c24x0_softc *) s3c2xx0_softc; 153 int v0, v1, delta; 154 u_int ucnt; 155 156 if ( timer4_reload_value == 0 ){ 157 /* not initialized yet */ 158 while ( n-- > 0 ){ 159 int m; 160 161 for (m=0; m<100; ++m ) 162 ; 163 } 164 return; 165 } 166 167 /* read down counter */ 168 v0 = read_timer(sc); 169 170 ucnt = usec_to_counter(n); 171 172 while( ucnt > 0 ) { 173 v1 = read_timer(sc); 174 delta = v0 - v1; 175 if ( delta < 0 ) 176 delta += timer4_reload_value; 177 #ifdef DEBUG 178 if (delta < 0 || delta > timer4_reload_value) 179 panic("wrong value from timer counter"); 180 #endif 181 182 if((u_int)delta < ucnt){ 183 ucnt -= (u_int)delta; 184 v0 = v1; 185 } 186 else { 187 ucnt = 0; 188 } 189 } 190 /*NOTREACHED*/ 191 } 192 193 void 194 setstatclockrate(int newhz) 195 { 196 } 197 198 static int 199 hardintr(void *arg) 200 { 201 atomic_add_32(&s3c24x0_base, timer4_reload_value); 202 203 hardclock((struct clockframe *)arg); 204 205 return 1; 206 } 207 208 void 209 cpu_initclocks(void) 210 { 211 struct s3c24x0_softc *sc = (struct s3c24x0_softc *)s3c2xx0_softc; 212 long tc; 213 int prescaler, h; 214 int pclk = s3c2xx0_softc->sc_pclk; 215 bus_space_tag_t iot = sc->sc_sx.sc_iot; 216 bus_space_handle_t ioh = sc->sc_timer_ioh; 217 uint32_t reg; 218 219 stathz = STATHZ; 220 profhz = stathz; 221 222 #define time_constant(hz) (TIMER_FREQUENCY(pclk) /(hz)/ prescaler) 223 #define calc_time_constant(hz) \ 224 do { \ 225 prescaler = 1; \ 226 do { \ 227 ++prescaler; \ 228 tc = time_constant(hz); \ 229 } while( tc > 65536 ); \ 230 } while(0) 231 232 233 /* Use the channels 4 and 3 for hardclock and statclock, respectively */ 234 235 /* stop all timers */ 236 bus_space_write_4(iot, ioh, TIMER_TCON, 0); 237 238 /* calc suitable prescaler value */ 239 h = MIN(hz,stathz); 240 calc_time_constant(h); 241 242 timer4_prescaler = prescaler; 243 timer4_reload_value = TIMER_FREQUENCY(pclk) / hz / prescaler; 244 timer4_mseccount = TIMER_FREQUENCY(pclk)/timer4_prescaler/1000 ; 245 246 bus_space_write_4(iot, ioh, TIMER_TCNTB(4), 247 ((prescaler - 1) << 16) | (timer4_reload_value - 1)); 248 249 printf("clock: hz=%d stathz = %d PCLK=%d prescaler=%d tc=%ld\n", 250 hz, stathz, pclk, prescaler, tc); 251 252 bus_space_write_4(iot, ioh, TIMER_TCNTB(3), 253 ((prescaler - 1) << 16) | (time_constant(stathz) - 1)); 254 255 s3c24x0_intr_establish(S3C24X0_INT_TIMER4, IPL_CLOCK, 256 IST_NONE, hardintr, 0); 257 #ifdef IPL_STATCLOCK 258 s3c24x0_intr_establish(S3C24X0_INT_TIMER3, IPL_STATCLOCK, 259 IST_NONE, statintr, 0); 260 #endif 261 262 /* set prescaler1 */ 263 reg = bus_space_read_4(iot, ioh, TIMER_TCFG0); 264 bus_space_write_4(iot, ioh, TIMER_TCFG0, 265 (reg & ~0xff00) | ((prescaler-1) << 8)); 266 267 /* divider 1/16 for ch #3 and #4 */ 268 reg = bus_space_read_4(iot, ioh, TIMER_TCFG1); 269 bus_space_write_4(iot, ioh, TIMER_TCFG1, 270 (reg & ~(TCFG1_MUX_MASK(3)|TCFG1_MUX_MASK(4))) | 271 (TCFG1_MUX_DIV16 << TCFG1_MUX_SHIFT(3)) | 272 (TCFG1_MUX_DIV16 << TCFG1_MUX_SHIFT(4)) ); 273 274 275 /* start timers */ 276 reg = bus_space_read_4(iot, ioh, TIMER_TCON); 277 reg &= ~(TCON_MASK(3)|TCON_MASK(4)); 278 279 /* load the time constant */ 280 bus_space_write_4(iot, ioh, TIMER_TCON, reg | 281 TCON_MANUALUPDATE(3) | TCON_MANUALUPDATE(4)); 282 /* set auto reload and start */ 283 bus_space_write_4(iot, ioh, TIMER_TCON, reg | 284 TCON_AUTORELOAD(3) | TCON_START(3) | 285 TCON_AUTORELOAD(4) | TCON_START(4) ); 286 287 s3c24x0_timecounter.tc_frequency = TIMER_FREQUENCY(pclk) / timer4_prescaler; 288 tc_init(&s3c24x0_timecounter); 289 } 290 291 292 #if 0 293 /* test routine for delay() */ 294 295 void delay_test(void); 296 void 297 delay_test(void) 298 { 299 struct s3c2xx0_softc *sc = s3c2xx0_softc; 300 volatile int *pdatc = (volatile int *) 301 ((char *)bus_space_vaddr(sc->sc_iot, sc->sc_gpio_ioh) + GPIO_PDATC); 302 static const int d[] = {0, 1, 5, 10, 50, 100, 500, 1000, -1}; 303 int i; 304 int v = *pdatc & ~0x07; 305 306 for (;;) { 307 *pdatc = v | 2; 308 309 for (i=0; d[i] >= 0; ++i) { 310 *pdatc = v | 3; 311 delay(d[i]); 312 *pdatc = v | 2; 313 } 314 *pdatc = v; 315 } 316 } 317 #endif 318 319