1 /* $NetBSD: s3c2800_intr.c,v 1.12 2010/12/20 00:25:29 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Fujitsu Component Limited 5 * Copyright (c) 2002 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * IRQ handler for Samsung S3C2800 processor. 37 * It has integrated interrupt controller. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: s3c2800_intr.c,v 1.12 2010/12/20 00:25:29 matt Exp $"); 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/malloc.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 50 #include <arm/cpufunc.h> 51 52 #include <arm/s3c2xx0/s3c2800reg.h> 53 #include <arm/s3c2xx0/s3c2800var.h> 54 55 /* 56 * interrupt dispatch table. 57 */ 58 59 struct s3c2xx0_intr_dispatch handler[ICU_LEN]; 60 61 volatile int intr_mask; /* XXX: does this need to be volatile? */ 62 volatile int global_intr_mask = 0; /* mask some interrupts at all spl level */ 63 64 /* interrupt masks for each level */ 65 int s3c2xx0_imask[NIPL]; 66 int s3c2xx0_ilevel[ICU_LEN]; 67 68 vaddr_t intctl_base; /* interrupt controller registers */ 69 #define icreg(offset) \ 70 (*(volatile uint32_t *)(intctl_base+(offset))) 71 72 /* 73 * Clearing interrupt pending bits affects some built-in 74 * peripherals. For example, IIC starts transmitting next data when 75 * its interrupt pending bit is cleared. 76 * We need to leave those bits to peripheral handlers. 77 */ 78 #define PENDING_CLEAR_MASK (~((1<<S3C2800_INT_IIC0)|(1<<S3C2800_INT_IIC1))) 79 80 /* 81 * called from irq_entry. 82 */ 83 void s3c2800_irq_handler(struct clockframe *); 84 void 85 s3c2800_irq_handler(struct clockframe *frame) 86 { 87 uint32_t irqbits; 88 int irqno; 89 int saved_spl_level; 90 91 saved_spl_level = curcpl(); 92 93 while ((irqbits = icreg(INTCTL_IRQPND) & ICU_INT_HWMASK) != 0) { 94 95 for (irqno = ICU_LEN-1; irqno >= 0; --irqno) 96 if (irqbits & (1<<irqno)) 97 break; 98 99 if (irqno < 0) 100 break; 101 102 /* raise spl to stop interrupts of lower priorities */ 103 if (saved_spl_level < handler[irqno].level) 104 s3c2xx0_setipl(handler[irqno].level); 105 106 /* clear pending bit */ 107 icreg(INTCTL_SRCPND) = PENDING_CLEAR_MASK & (1 << irqno); 108 109 enable_interrupts(I32_bit); /* allow nested interrupts */ 110 111 (*handler[irqno].func) ( 112 handler[irqno].cookie == 0 113 ? frame : handler[irqno].cookie); 114 115 disable_interrupts(I32_bit); 116 117 /* restore spl to that was when this interrupt happen */ 118 s3c2xx0_setipl(saved_spl_level); 119 } 120 121 #ifdef __HAVE_FAST_SOFTINTS 122 cpu_dosoftints(); 123 #endif 124 } 125 126 static const u_char s3c2800_ist[] = { 127 EXTINTR_LOW, /* NONE */ 128 EXTINTR_FALLING, /* PULSE */ 129 EXTINTR_FALLING, /* EDGE */ 130 EXTINTR_LOW, /* LEVEL */ 131 EXTINTR_HIGH, 132 EXTINTR_RISING, 133 EXTINTR_BOTH, 134 }; 135 136 void * 137 s3c2800_intr_establish(int irqno, int level, int type, 138 int (* func) (void *), void *cookie) 139 { 140 int save; 141 142 if (irqno < 0 || irqno >= ICU_LEN || 143 type < IST_NONE || IST_EDGE_BOTH < type) 144 panic("intr_establish: bogus irq or type"); 145 146 save = disable_interrupts(I32_bit); 147 148 handler[irqno].cookie = cookie; 149 handler[irqno].func = func; 150 handler[irqno].level = level; 151 152 s3c2xx0_update_intr_masks(irqno, level); 153 154 if (irqno <= S3C2800_INT_EXT(7)) { 155 /* 156 * Update external interrupt control 157 */ 158 uint32_t reg; 159 u_int trig; 160 161 trig = s3c2800_ist[type]; 162 163 reg = bus_space_read_4(s3c2xx0_softc->sc_iot, 164 s3c2xx0_softc->sc_gpio_ioh, 165 GPIO_EXTINTR); 166 167 reg = reg & ~(0x0f << (4*irqno)); 168 reg |= trig << (4*irqno); 169 170 bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh, 171 GPIO_EXTINTR, reg); 172 } 173 174 s3c2xx0_setipl(curcpl()); 175 176 restore_interrupts(save); 177 178 return (&handler[irqno]); 179 } 180 181 182 static void 183 init_interrupt_masks(void) 184 { 185 int i; 186 187 for (i = 0; i < NIPL; i++) 188 s3c2xx0_imask[i] = 0; 189 } 190 191 void 192 s3c2800_intr_init(struct s3c2800_softc *sc) 193 { 194 intctl_base = (vaddr_t) bus_space_vaddr(sc->sc_sx.sc_iot, 195 sc->sc_sx.sc_intctl_ioh); 196 197 s3c2xx0_intr_mask_reg = (uint32_t *)(intctl_base + INTCTL_INTMSK); 198 199 /* clear all pending interrupt */ 200 icreg(INTCTL_SRCPND) = 0xffffffff; 201 202 init_interrupt_masks(); 203 204 s3c2xx0_intr_init(handler, ICU_LEN); 205 206 } 207