xref: /netbsd/sys/arch/arm/s3c2xx0/s3c2800reg.h (revision c4a72b64)
1 /* $NetBSD: s3c2800reg.h,v 1.1 2002/11/20 17:52:50 bsh Exp $ */
2 
3 /*
4  * Copyright (c) 2002 Fujitsu Component Limited
5  * Copyright (c) 2002 Genetec Corporation
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. Neither the name of The Fujitsu Component Limited nor the name of
17  *    Genetec corporation may not be used to endorse or promote products
18  *    derived from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
21  * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
22  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24  * DISCLAIMED.  IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
25  * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
29  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32  * SUCH DAMAGE.
33  */
34 
35 /*
36  * Samsung S3C2800 processor is ARM920T based integrated CPU
37  *
38  * Reference:
39  *  S3C2800 User's Manual
40  */
41 #ifndef _ARM_S3C2XX0_S3C2800REG_H_
42 #define _ARM_S3C2XX0_S3C2800REG_H_
43 
44 /* common definitions for S3C2800, S3C2400 and S3C2410 */
45 #include <arm/s3c2xx0/s3c2xx0reg.h>
46 
47 /*
48  * Memory Map
49  */
50 
51 /* ROM/SRAM/FLASH */
52 #define S3C2800_SBANK0_START 0x00000000
53 #define S3C2800_SBANK1_START 0x02000000
54 #define S3C2800_SBANK2_START 0x04000000
55 #define S3C2800_SBANK3_START 0x06000000
56 #define S3C2800_SBANK4_START 0x08000000
57 
58 /* DRAM */
59 #define S3C2800_DBANK0_START 0x08000000
60 #define S3C2800_DBANK1_START 0x0a000000
61 #define S3C2800_DBANK2_START 0x0c000000
62 #define S3C2800_DBANK3_START 0x0e000000
63 #define S3C2800_DBANK_SIZE   0x02000000	/* 32MB */
64 
65 /*
66  * Physical address of integrated peripherals
67  */
68 #define S3C2800_PERIPHERALS	0x10000000
69 #define S3C2800_CLKMAN_BASE	0x10000000 /* clock & power management */
70 #define S3C2800_CLKMAN_SIZE	0x18
71 #define S3C2800_MEMCTL_BASE	0x10010000 /* memory controller */
72 #define S3C2800_MEMCTL_SIZE	0x20
73 #define S3C2800_DMA0_BASE	0x10030000
74 #define S3C2800_DMA1_BASE	0x10040000
75 #define S3C2800_DMA2_BASE	0x10050000
76 #define S3C2800_DMA3_BASE	0x10060000
77 #define S3C2800_PCICTL_BASE	0x10080000
78 #define S3C2800_PCICTL_SIZE	0x58
79 #define S3C2800_GPIO_BASE	0x10100000
80 #define S3C2800_GPIO_SIZE	0x50
81 #define S3C2800_TIMER0_BASE	0x10130000
82 #define S3C2800_TIMER1_BASE	0x10140000
83 #define S3C2800_TIMER2_BASE	0x10150000
84 #define S3C2800_TIMER_SIZE	0x10
85 #define S3C2800_UART0_BASE	0x10170000
86 #define S3C2800_UART1_BASE	0x10180000
87 #define S3C2800_UART_SIZE	0x2c
88 #define S3C2800_INTCTL_BASE	0x10020000
89 #define S3C2800_INTCTL_SIZE	0x14
90 
91 
92 /* width of interrupt controller */
93 #define ICU_LEN			29
94 #define ICU_INT_HWMASK		0x1fffffff
95 
96 /* Clock & power manager */
97 #define CLKMAN_PLLCON	0x00
98 /* MDIV, PDIV, SDIV */
99 #define CLKMAN_CLKCON	0x04
100 #define  CLKCON_PCLK	(1<<12)	/* APB clock division ratio */
101 #define  CLKCON_HCLK	(1<<11)	/* AHB clock division ratio */
102 #define  CLKCON_PCI	(1<<10)	/* FCLK into PCI */
103 #define  CLKCON_IIC1	(1<<9)	/* PCLK to I2C1 */
104 #define  CLKCON_IIC0	(1<<8)	/* PCLK to I2C0 */
105 #define  CLKCON_RTC	(1<<7)	/* PCLK to RTC */
106 #define  CLKCON_UART1	(1<<6)	/* PCLK to UART1 */
107 #define  CLKCON_UART0	(1<<5)	/* PCLK to UART0 */
108 #define  CLKCON_DMA23	(1<<4)	/* PCLK to DMA2,3 */
109 #define  CLKCON_DMA01	(1<<3)	/* PCLK to DMA0,1 */
110 #define  CLKCON_TIMER	(1<<2)	/* PCLK to TIMER */
111 #define  CLKCON_IDLE	(1<<1)	/* Enter IDLE Mode */
112 
113 #define CLKMAN_CLKSLOW	0x08	/* slow clock controll */
114 #define  CLKSLOW_SLOW	(1<<4)	/* 1: Enable SLOW mode */
115 #define  CLKSLOW_VAL_MASK  0x0f	/* divider value for slow clock */
116 
117 #define CLKMAN_LOCKTIME 0x0c	/* PLL lock time */
118 
119 #define CLKMAN_SWRCON	0x10	/* Software reset control */
120 #define  SWRCON_SWR	(1<<0)	/* 1: Invoke software reset */
121 
122 #define CLKMAN_RSTSR	0x14	/* Reset status register */
123 #define  RSTSR_WDR	(1<<2)	/* watchdog reset */
124 #define  RSTSR_SWR	(1<<1)	/* Software reset */
125 #define  RSTSR_HWR	(1<<0)	/* Hardware reset */
126 
127 /* memory controller */
128 #define MEMCTL_ENDIAN	0x00	/* Endian control (read-only) */
129 #define MEMCTL_SMBCON0	0x04	/* SBank0 control register for static */
130 #define MEMCTL_SMBCON1	0x08	/* SBank0 control register for static */
131 #define MEMCTL_SMBCON2	0x0c	/* SBank0 control register for static */
132 #define MEMCTL_SMBCON3	0x10	/* SBank0 control register for static */
133 #define  SMBCON_WS	(1<<20)	/* Wait status */
134 #define  SMBCON_ST	(1<<19)	/* use UB/LB */
135 #define  SMBCON_TACS_SHIFT  12	/* address setup time before nSCSn */
136 #define  SMBCON_TACS	(3<<SMBCON_TACS_SHIFT)
137 #define  SMBCON_TCOS_SHIFT  10	/* CS setup time before nOE */
138 #define  SMBCON_TCOS	(3<<SMBCON_TCOS_SHIFT)
139 #define  SMBCON_TOCH_SHIFT   8	/* CS hold time after nOE */
140 #define  SMBCON_TOCH	(3<<SMBCON_TOCH_SHIFT)
141 #define  SMBCON_TACC_SHIFT   4	/* Access cycle */
142 #define  SMBCON_TACC	     (0x0f<<SMBCON_TOCH_SHIFT)
143 #define  SMBCON_TACC_1CLK    (0x00<<SMBCON_TOCH_SHIFT)
144 #define  SMBCON_TACC_2CLK    (0x01<<SMBCON_TOCH_SHIFT)
145 #define  SMBCON_TACC_3CLK    (0x02<<SMBCON_TOCH_SHIFT)
146 #define  SMBCON_TACC_4CLK    (0x03<<SMBCON_TOCH_SHIFT)
147 #define  SMBCON_TACC_6CLK    (0x04<<SMBCON_TOCH_SHIFT)
148 #define  SMBCON_TACC_7CLK    (0x05<<SMBCON_TOCH_SHIFT)
149 #define  SMBCON_TACC_8CLK    (0x06<<SMBCON_TOCH_SHIFT)
150 #define  SMBCON_TACC_9CLK    (0x07<<SMBCON_TOCH_SHIFT)
151 #define  SMBCON_TACC_10CLK   (0x08<<SMBCON_TOCH_SHIFT)
152 #define  SMBCON_TACC_12CLK   (0x09<<SMBCON_TOCH_SHIFT)
153 #define  SMBCON_TACC_14CLK   (0x0a<<SMBCON_TOCH_SHIFT)
154 #define  SMBCON_TCAH_SHIFT   2	/* Address hold time after nSCSn */
155 #define  SMBCON_SDW	  0x03
156 #define  SMBCON_SDW_8BIT     0
157 #define  SMBCON_SDW_16BIT    1
158 #define  SMBCON_SDW_32BIT    2
159 #define MEMCTL_REFRESH	0x14	/* DRAM/SDRAM refresh control */
160 #define  REFRESH_REFEN  (1<<23)
161 #define  REFRESH_REFMD	(1<<22)
162 #define  REFRESH_TRP	(3<<20)
163 #define  REFRESH_TRC	(3<<16)
164 #define  REFRESH_TCHR	(3<<12)	/* CAS hold time */
165 #define  REFRESH_COUNTER 0x7ff
166 #define MEMCTL_DMTMCON  0x18	/* timing control for dynamic memory */
167 #define  DMTMCON_DW	(3<<16)	/* bus width */
168 #define  DMTMCON_MT	(3<<10)	/* dynamic memory type */
169 #define  DMTMCON_TRCD	(3<<8)	/* DRAM RAS to CAS delay */
170 #define  DMTMCON_TCAS	(3<<6)	/* CAS pulse width */
171 #define  DMTMCON_TCP	(3<<4)	/* CAS pre charge */
172 #define  DMTMCON_CAN	(3<<2)	/* column address number */
173 #define  DMTMCON_STRCD	(3<<0)	/* SDRAM RAS to CAS delay */
174 #define MEMCTL_MRSR	0x1c	/* SDRAM mode register */
175 #define  MRSR_CL_SHIFT  4
176 #define  MRSR_CL	(7<<MRSR_CL_SHIFT)	/* CAS latency */
177 
178 /* GPIO */
179 #define GPIO_PCONA	0x00	/* port A configuration */
180 #define  PCON_INPUT	0	/* Input port */
181 #define  PCON_OUTPUT	1	/* Output port */
182 #define  PCON_ALTFUN	2	/* Alternate function */
183 #define GPIO_PDATA	0x04	/* port A data */
184 #define GPIO_PUPA	0x08	/* port A pull-up */
185 #define GPIO_PCONB	0x0c
186 #define GPIO_PDATB	0x10
187 #define GPIO_PCONC	0x18
188 #define GPIO_PDATC	0x1c
189 #define GPIO_PUPC	0x20
190 #define GPIO_PCOND	0x24
191 #define GPIO_PDATD	0x28
192 #define GPIO_PUPD	0x2c
193 #define GPIO_PCONE	0x30
194 #define GPIO_PDATE	0x34
195 #define GPIO_PUPE	0x38
196 #define GPIO_PCONF	0x3c
197 #define GPIO_PDATF	0x40
198 #define GPIO_PUPF	0x44
199 
200 #define GPIO_EXTINTR	0x48	/* external interrupt control */
201 #define  EXTINTR_LOW	 0x00
202 #define  EXTINTR_HIGH	 0x01
203 #define  EXTINTR_FALLING 0x02
204 #define  EXTINTR_RISING  0x04
205 #define  EXTINTR_BOTH    0x06
206 
207 #define GPIO_SPUCR	0x4c  	/* special pull-up control */
208 #define  SPUCR1	(1<<1)		/* pull-up for data[31:16] */
209 #define  SPUCR0	(1<<0)		/* pull-up for data[15:0] */
210 
211 /* Timer */
212 #define TIMER_TMCON	0x00	/* control register */
213 #define  TMCON_MUX	(3<<2)	/* MUX input */
214 #define  TMCON_MUX_DIV4  (0<<2)
215 #define  TMCON_MUX_DIV8  (1<<2)
216 #define  TMCON_MUX_DIV16 (2<<2)
217 #define  TMCON_MUX_DIV32 (3<<2)
218 #define  TMCON_INTENA	(1<<1)	/* Interrupt/DMA enable */
219 #define  TMCON_ENABLE	(1<<0)	/* Count enable */
220 #define TIMER_TMDAT	0x04	/* data register */
221 #define  TMDAT_PRESCALER  (0xff<<16)
222 #define  TMDAT_DATA	0xffff
223 #define TIMER_TMCNT	0x08	/* down counter */
224 
225 
226 /* UART (Small diffs to S3C2400's UART) */
227 #define  UMCON_AFC	(1<<1)	/* auto flow control */
228 #define  UMSTAT_DCTS	(1<<4)	/* CTS change */
229 
230 /* Interrupt controller */
231 #define INTCTL_IRQPND	0x0c	/* IRQ pending */
232 #define INTCTL_FIQPND	0x10	/* FIQ pending */
233 
234 /* Interrupt source */
235 #define S3C2800_INT_RTC  	28	/* RTC alarm */
236 #define S3C2800_INT_TICK	27	/* RTC tick */
237 #define S3C2800_INT_FULL	26	/* Remocon data FIFO full */
238 #define S3C2800_INT_RMT 	25	/* Remocon data input */
239 #define S3C2800_INT_UERR1	24	/* UART1 error */
240 #define S3C2800_INT_UERR0	23	/* UART0 error */
241 #define S3C2800_INT_TXD1	22	/* UART1 Tx */
242 #define S3C2800_INT_TXD0	21	/* UART0 Tx */
243 #define S3C2800_INT_RXD1	20	/* UART1 Rx */
244 #define S3C2800_INT_RXD0	19	/* UART0 Rx*/
245 #define S3C2800_INT_IIC1	18
246 #define S3C2800_INT_IIC0	17
247 #define S3C2800_INT_TIMER2	16
248 #define S3C2800_INT_TIMER1	15
249 #define S3C2800_INT_TIMER0	14
250 #define S3C2800_INT_DMA3	13
251 #define S3C2800_INT_DMA2	12
252 #define S3C2800_INT_DMA1	11
253 #define S3C2800_INT_DMA0	10
254 #define S3C2800_INT_PCI  	8 /* PCI interrupt */
255 #define S3C2800_INT_EXT(n)	(n) /* External interrupt [7:0] */
256 
257 
258 /* PCI space */
259 #define S3C2800_PCI_BASE	  0x20000000
260 #define S3C2800_PCI_MEMSPACE_BASE 0x20000000	/* Memory space */
261 #define S3C2800_PCI_MEMSPACE_SIZE 0x08000000
262 #define S3C2800_PCI_CONF0_BASE    0x28000000	/* Config type 0 space */
263 #define S3C2800_PCI_CONF0_SIZE    0x0000b000
264 #define S3C2800_PCI_CONF1_BASE    0x2a000000	/* Config type 1 space */
265 #define S3C2800_PCI_CONF1_SIZE    0x02000000
266 #define S3C2800_PCI_IOSPACE_BASE  0x2e000000
267 #define S3C2800_PCI_IOSPACE_SIZE  0x00100000
268 
269 #define PCICTL_PCICON   	0x0100	/* control and status */
270 #define  PCICON_INT	(1<<31)		/* internal interrupt status */
271 #define  PCICON_MBS	(1<<29)		/* PCI master interface busy */
272 #define  PCICON_TBS	(1<<28)		/* PCI target interface busy */
273 #define  PCICON_CRS	(1<<27)		/* ARM CPU reset status */
274 #define  PCICON_RDY	(1<<9)		/* Enable PCI target read */
275 #define  PCICON_CFD	(1<<8)		/* Configuration done */
276 #define  PCICON_ATS	(1<<4)		/* Enable address translation */
277 #define  PCICON_ARB	(1<<1)		/* Enable internal arbiter */
278 #define  PCICON_HST	(1<<0)		/* bridge/adaptor */
279 
280 #define PCICTL_PCISET	0x104		/* PCI command, read count, DAC */
281 #define  PCISET_CMD_SHIFT  17
282 #define  PCISET_DAC_MASK   0xff
283 
284 #define PCICTL_PCIINTEN	0x108		/* interrupt enable */
285 #define	PCICTL_PCIINTST 0x10c		/* interrupt status */
286 
287 #define  PCIINTEN_BAP	(1<<31)		/* INTA# in adapter mode */
288 #define  PCIINTST_WDE	(1<<31)		/* master fatal error in read */
289 #define  PCIINTST_RDE	(1<<30)		/* master fatal error in write */
290 #define  PCIINT_INA	(1<<10)		/* INTA# enable */
291 #define  PCIINT_SER	(1<<9)		/* SERR# interrupt enable */
292 #define  PCIINT_TPE	(1<<4)		/* target parity error */
293 #define  PCIINT_MPE	(1<<3)		/* master parity error */
294 #define  PCIINT_MFE	(1<<2)		/* master fatal error */
295 #define  PCIINT_PRA	(1<<1)		/* reset assert interrupt */
296 #define  PCIINT_PRD	(1<<0)		/* reset de-assert interrupt */
297 
298 #define PCICTL_PCIBATPA0	0x140	/* address translation PCI to AHB BAR0 */
299 #define PCICTL_PCIBAM0   	0x144	/* BAR0 mask */
300 #define PCICTL_PCIBATPA1	0x148	/* address translation PCI to AHB BAR1 */
301 #define PCICTL_PCIBAM1   	0x14c	/* BAR0 mask */
302 #define PCICTL_PCIBATPA2	0x150	/* address translation PCI to AHB BAR2 */
303 #define PCICTL_PCIBAM2   	0x154	/* BAR0 mask */
304 
305 #endif /* _ARM_S3C2XX0_S3C2800REG_H_ */
306