1 /* $NetBSD: s3c2xx0var.h,v 1.5 2010/11/16 02:53:02 bsh Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Fujitsu Component Limited 5 * Copyright (c) 2002 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #ifndef _ARM_S3C2XX0VAR_H_ 36 #define _ARM_S3C2XX0VAR_H_ 37 38 #include <machine/bus.h> 39 #include <sys/device.h> 40 41 struct s3c2xx0_softc { 42 struct device sc_dev; 43 44 bus_space_tag_t sc_iot; 45 46 bus_space_handle_t sc_intctl_ioh; 47 bus_space_handle_t sc_memctl_ioh; /* Memory controller */ 48 bus_space_handle_t sc_clkman_ioh; /* Clock manager */ 49 bus_space_handle_t sc_gpio_ioh; /* GPIO */ 50 bus_space_handle_t sc_rtc_ioh; /* real time clock */ 51 52 bus_dma_tag_t sc_dmat; 53 54 /* clock frequency */ 55 int sc_fclk; /* CPU clock */ 56 int sc_hclk; /* AHB bus clock */ 57 int sc_pclk; /* peripheral clock */ 58 }; 59 60 typedef void *s3c2xx0_chipset_tag_t; 61 62 struct s3c2xx0_attach_args { 63 s3c2xx0_chipset_tag_t sa_sc; 64 bus_space_tag_t sa_iot; 65 bus_addr_t sa_addr; 66 bus_size_t sa_size; 67 int sa_intr; 68 int sa_index; 69 bus_dma_tag_t sa_dmat; 70 }; 71 72 extern struct bus_space s3c2xx0_bs_tag; 73 extern struct s3c2xx0_softc *s3c2xx0_softc; 74 extern struct arm32_bus_dma_tag s3c2xx0_bus_dma; 75 76 /* Platform needs to provide this */ 77 bus_dma_tag_t s3c2xx0_bus_dma_init(struct arm32_bus_dma_tag *); 78 79 #endif /* _ARM_S3C2XX0VAR_H_ */ 80