1*8e90f9edSthorpej /* $NetBSD: exynos_dwcmmc.c,v 1.14 2021/01/27 03:10:19 thorpej Exp $ */ 21f005c6fSjmcneill 31f005c6fSjmcneill /*- 41f005c6fSjmcneill * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 51f005c6fSjmcneill * All rights reserved. 61f005c6fSjmcneill * 71f005c6fSjmcneill * Redistribution and use in source and binary forms, with or without 81f005c6fSjmcneill * modification, are permitted provided that the following conditions 91f005c6fSjmcneill * are met: 101f005c6fSjmcneill * 1. Redistributions of source code must retain the above copyright 111f005c6fSjmcneill * notice, this list of conditions and the following disclaimer. 121f005c6fSjmcneill * 2. Redistributions in binary form must reproduce the above copyright 131f005c6fSjmcneill * notice, this list of conditions and the following disclaimer in the 141f005c6fSjmcneill * documentation and/or other materials provided with the distribution. 151f005c6fSjmcneill * 161f005c6fSjmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 171f005c6fSjmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 181f005c6fSjmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 191f005c6fSjmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 201f005c6fSjmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 211f005c6fSjmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 221f005c6fSjmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 231f005c6fSjmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 241f005c6fSjmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 251f005c6fSjmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 261f005c6fSjmcneill * SUCH DAMAGE. 271f005c6fSjmcneill */ 281f005c6fSjmcneill 291f005c6fSjmcneill #include <sys/cdefs.h> 30*8e90f9edSthorpej __KERNEL_RCSID(0, "$NetBSD: exynos_dwcmmc.c,v 1.14 2021/01/27 03:10:19 thorpej Exp $"); 311f005c6fSjmcneill 321f005c6fSjmcneill #include <sys/param.h> 331f005c6fSjmcneill #include <sys/bus.h> 341f005c6fSjmcneill #include <sys/device.h> 351f005c6fSjmcneill #include <sys/intr.h> 361f005c6fSjmcneill #include <sys/systm.h> 371f005c6fSjmcneill #include <sys/kernel.h> 381f005c6fSjmcneill #include <sys/mutex.h> 391f005c6fSjmcneill #include <sys/condvar.h> 401f005c6fSjmcneill 411f005c6fSjmcneill #include <arm/samsung/exynos_var.h> 421f005c6fSjmcneill 43bd8beb09Sskrll #include <dev/ic/dwc_mmc_reg.h> 441f005c6fSjmcneill #include <dev/ic/dwc_mmc_var.h> 451f005c6fSjmcneill #include <dev/fdt/fdtvar.h> 461f005c6fSjmcneill 4768890319Sjmcneill #define MPS_BEGIN 0x200 4868890319Sjmcneill #define MPS_END 0x204 4968890319Sjmcneill #define MPS_CTRL 0x20c 5068890319Sjmcneill #define MPS_CTRL_SECURE_WRITE __BIT(6) 5168890319Sjmcneill #define MPS_CTRL_NON_SECURE_READ __BIT(5) 5268890319Sjmcneill #define MPS_CTRL_NON_SECURE_WRITE __BIT(4) 5368890319Sjmcneill #define MPS_CTRL_VALID __BIT(0) 5468890319Sjmcneill 551f005c6fSjmcneill static int exynos_dwcmmc_match(device_t, cfdata_t, void *); 561f005c6fSjmcneill static void exynos_dwcmmc_attach(device_t, device_t, void *); 571f005c6fSjmcneill 581f005c6fSjmcneill static int exynos_dwcmmc_card_detect(struct dwc_mmc_softc *); 59447e79e5Sjmcneill static int exynos_dwcmmc_bus_clock(struct dwc_mmc_softc *, int); 601f005c6fSjmcneill 611f005c6fSjmcneill struct exynos_dwcmmc_softc { 621f005c6fSjmcneill struct dwc_mmc_softc sc; 631f005c6fSjmcneill struct clk *sc_clk_biu; 641f005c6fSjmcneill struct clk *sc_clk_ciu; 651f005c6fSjmcneill struct fdtbus_gpio_pin *sc_pin_cd; 66447e79e5Sjmcneill u_int sc_ciu_div; 671f005c6fSjmcneill }; 681f005c6fSjmcneill 69c9a31e86Sskrll CFATTACH_DECL_NEW(exynos_dwcmmc, sizeof(struct exynos_dwcmmc_softc), 701f005c6fSjmcneill exynos_dwcmmc_match, exynos_dwcmmc_attach, NULL, NULL); 711f005c6fSjmcneill 727c2ad6b8Sthorpej static const struct device_compatible_entry compat_data[] = { 737c2ad6b8Sthorpej /* disable encryption mode? */ 747c2ad6b8Sthorpej { .compat = "samsung,exynos5250-dw-mshc", .value = 0 }, 757c2ad6b8Sthorpej { .compat = "samsung,exynos5420-dw-mshc-smu", .value = 1 }, 767c2ad6b8Sthorpej { .compat = "samsung,exynos5420-dw-mshc", .value = 0 }, 77f18cbf47Sthorpej DEVICE_COMPAT_EOL 781f005c6fSjmcneill }; 791f005c6fSjmcneill 801f005c6fSjmcneill static int 811f005c6fSjmcneill exynos_dwcmmc_match(device_t parent, cfdata_t cf, void *aux) 821f005c6fSjmcneill { 831f005c6fSjmcneill struct fdt_attach_args * const faa = aux; 841f005c6fSjmcneill 85*8e90f9edSthorpej return of_compatible_match(faa->faa_phandle, compat_data); 861f005c6fSjmcneill } 871f005c6fSjmcneill 881f005c6fSjmcneill static void 891f005c6fSjmcneill exynos_dwcmmc_attach(device_t parent, device_t self, void *aux) 901f005c6fSjmcneill { 911f005c6fSjmcneill struct exynos_dwcmmc_softc *esc = device_private(self); 921f005c6fSjmcneill struct dwc_mmc_softc *sc = &esc->sc; 931f005c6fSjmcneill struct fdt_attach_args * const faa = aux; 947c2ad6b8Sthorpej const struct device_compatible_entry *dce; 951f005c6fSjmcneill const int phandle = faa->faa_phandle; 961f005c6fSjmcneill char intrstr[128]; 971f005c6fSjmcneill bus_addr_t addr; 981f005c6fSjmcneill bus_size_t size; 991f005c6fSjmcneill int error; 1001f005c6fSjmcneill 1011f005c6fSjmcneill if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 1021f005c6fSjmcneill aprint_error(": couldn't get registers\n"); 1031f005c6fSjmcneill return; 1041f005c6fSjmcneill } 1051f005c6fSjmcneill 106447e79e5Sjmcneill if (of_getprop_uint32(phandle, "samsung,dw-mshc-ciu-div", &esc->sc_ciu_div)) { 1071f005c6fSjmcneill aprint_error(": missing samsung,dw-mshc-ciu-div property\n"); 1081f005c6fSjmcneill return; 1091f005c6fSjmcneill } 1101f005c6fSjmcneill 1111f005c6fSjmcneill esc->sc_clk_biu = fdtbus_clock_get(phandle, "biu"); 1121f005c6fSjmcneill if (esc->sc_clk_biu == NULL) { 1131f005c6fSjmcneill aprint_error(": couldn't get clock biu\n"); 1141f005c6fSjmcneill return; 1151f005c6fSjmcneill } 1161f005c6fSjmcneill esc->sc_clk_ciu = fdtbus_clock_get(phandle, "ciu"); 1171f005c6fSjmcneill if (esc->sc_clk_ciu == NULL) { 1181f005c6fSjmcneill aprint_error(": couldn't get clock ciu\n"); 1191f005c6fSjmcneill return; 1201f005c6fSjmcneill } 121c0583cc2Sjmcneill 122c0583cc2Sjmcneill error = clk_enable(esc->sc_clk_biu); 1231f005c6fSjmcneill if (error) { 124c0583cc2Sjmcneill aprint_error(": couldn't enable clock biu: %d\n", error); 1251f005c6fSjmcneill return; 1261f005c6fSjmcneill } 1271f005c6fSjmcneill error = clk_enable(esc->sc_clk_ciu); 1281f005c6fSjmcneill if (error) { 1291f005c6fSjmcneill aprint_error(": couldn't enable clock ciu: %d\n", error); 1301f005c6fSjmcneill return; 1311f005c6fSjmcneill } 1321f005c6fSjmcneill 133*8e90f9edSthorpej dce = of_compatible_lookup(faa->faa_phandle, compat_data); 1347c2ad6b8Sthorpej KASSERT(dce != NULL); 1357c2ad6b8Sthorpej 1361f005c6fSjmcneill sc->sc_dev = self; 1371f005c6fSjmcneill sc->sc_bst = faa->faa_bst; 1381f005c6fSjmcneill sc->sc_dmat = faa->faa_dmat; 139bd8beb09Sskrll sc->sc_intr_cardmask = DWC_MMC_INT_SDIO_INT(8); 1401f005c6fSjmcneill error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 1411f005c6fSjmcneill if (error) { 142dee6b79eSskrll aprint_error(": couldn't map %#" PRIxBUSADDR ": %d\n", 143dee6b79eSskrll addr, error); 1441f005c6fSjmcneill return; 1451f005c6fSjmcneill } 1461f005c6fSjmcneill 147447e79e5Sjmcneill sc->sc_clock_freq = clk_get_rate(esc->sc_clk_ciu) / (esc->sc_ciu_div + 1); 148d0bcf2beSjmcneill of_getprop_uint32(phandle, "fifo-depth", &sc->sc_fifo_depth); 149d0bcf2beSjmcneill sc->sc_flags = DWC_MMC_F_DMA; 150447e79e5Sjmcneill sc->sc_bus_clock = exynos_dwcmmc_bus_clock; 1511f005c6fSjmcneill 1521f005c6fSjmcneill esc->sc_pin_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 1531f005c6fSjmcneill GPIO_PIN_INPUT); 15468890319Sjmcneill if (esc->sc_pin_cd) 1551f005c6fSjmcneill sc->sc_card_detect = exynos_dwcmmc_card_detect; 1561f005c6fSjmcneill 1571f005c6fSjmcneill aprint_naive("\n"); 1581f005c6fSjmcneill aprint_normal(": MHS (%u Hz)\n", sc->sc_clock_freq); 1591f005c6fSjmcneill 1601f005c6fSjmcneill if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 1611f005c6fSjmcneill aprint_error_dev(self, "failed to decode interrupt\n"); 1621f005c6fSjmcneill return; 1631f005c6fSjmcneill } 1641f005c6fSjmcneill 16568890319Sjmcneill if (dwc_mmc_init(sc) != 0) 16668890319Sjmcneill return; 16768890319Sjmcneill 1681f005c6fSjmcneill sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, 0, 1691f005c6fSjmcneill dwc_mmc_intr, sc); 1701f005c6fSjmcneill if (sc->sc_ih == NULL) { 1711f005c6fSjmcneill aprint_error_dev(self, "couldn't establish interrupt on %s\n", 1721f005c6fSjmcneill intrstr); 1731f005c6fSjmcneill return; 1741f005c6fSjmcneill } 1751f005c6fSjmcneill aprint_normal_dev(self, "interrupting on %s\n", intrstr); 1761f005c6fSjmcneill 17768890319Sjmcneill /* Disable encryption mode */ 1787c2ad6b8Sthorpej if (dce->value != 0) { 17968890319Sjmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh, MPS_BEGIN, 0); 18068890319Sjmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh, MPS_END, ~0U); 18168890319Sjmcneill bus_space_write_4(sc->sc_bst, sc->sc_bsh, MPS_CTRL, 18268890319Sjmcneill MPS_CTRL_NON_SECURE_READ | MPS_CTRL_NON_SECURE_WRITE | 18368890319Sjmcneill MPS_CTRL_SECURE_WRITE | MPS_CTRL_VALID); 1841f005c6fSjmcneill } 1851f005c6fSjmcneill } 1861f005c6fSjmcneill 1871f005c6fSjmcneill static int 1881f005c6fSjmcneill exynos_dwcmmc_card_detect(struct dwc_mmc_softc *sc) 1891f005c6fSjmcneill { 1901f005c6fSjmcneill struct exynos_dwcmmc_softc *esc = device_private(sc->sc_dev); 1911f005c6fSjmcneill 1921f005c6fSjmcneill KASSERT(esc->sc_pin_cd != NULL); 1931f005c6fSjmcneill 1941f005c6fSjmcneill return fdtbus_gpio_read(esc->sc_pin_cd); 1951f005c6fSjmcneill } 196447e79e5Sjmcneill 197447e79e5Sjmcneill static int 198447e79e5Sjmcneill exynos_dwcmmc_bus_clock(struct dwc_mmc_softc *sc, int rate) 199447e79e5Sjmcneill { 200447e79e5Sjmcneill struct exynos_dwcmmc_softc *esc = device_private(sc->sc_dev); 201447e79e5Sjmcneill const int ciu_div = esc->sc_ciu_div + 1; 202447e79e5Sjmcneill int error; 203447e79e5Sjmcneill 204447e79e5Sjmcneill error = clk_set_rate(esc->sc_clk_ciu, 1000 * rate * ciu_div); 205447e79e5Sjmcneill if (error != 0) { 206447e79e5Sjmcneill aprint_error_dev(sc->sc_dev, "failed to set rate to %u Hz: %d\n", 207447e79e5Sjmcneill rate * ciu_div * 1000, error); 208447e79e5Sjmcneill return error; 209447e79e5Sjmcneill } 210447e79e5Sjmcneill 211447e79e5Sjmcneill sc->sc_clock_freq = clk_get_rate(esc->sc_clk_ciu) / ciu_div; 212447e79e5Sjmcneill 213447e79e5Sjmcneill aprint_debug_dev(sc->sc_dev, "set clock rate to %u Hz (target %u Hz)\n", 214447e79e5Sjmcneill sc->sc_clock_freq, rate * 1000); 215447e79e5Sjmcneill 216447e79e5Sjmcneill return 0; 217447e79e5Sjmcneill } 218