1 /* $NetBSD: i80200reg.h,v 1.3 2002/03/26 19:29:46 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _ARM_XSCALE_I80200REG_H_ 39 #define _ARM_XSCALE_I80200REG_H_ 40 41 /* 42 * Register definitions for the Intel 80200 XScale processor. 43 */ 44 45 /* 46 * Interrupt Controller Unit (CP13) 47 * 48 * CP13.0 Interrupt Control 49 * CP13.1 Interrupt Source 50 * CP13.2 Interrupt Steer 51 */ 52 53 #define INTCTL_FM 0x00000001 /* external FIQ# enable */ 54 #define INTCTL_IM 0x00000002 /* external IRQ# enable */ 55 #define INTCTL_PM 0x00000004 /* PMU interrupt enable */ 56 #define INTCTL_BM 0x00000008 /* BCU interrupt enable */ 57 58 #define INTSRC_PI 0x10000000 /* PMU interrupt */ 59 #define INTSRC_BM 0x20000000 /* BCU interrupt */ 60 #define INTSRC_II 0x40000000 /* external IRQ# */ 61 #define INTSRC_FI 0x80000000 /* external FIQ# */ 62 63 #define INTSTR_PS 0x00000001 /* PMU 0 = IRQ, 1 = FIQ */ 64 #define INTSTR_BS 0x00000002 /* BCU 0 = IRQ, 1 = FIQ */ 65 66 /* 67 * Bus Controller Unit (CP13) 68 * 69 * CP13.0.1 BCU Control 70 * CP13.1.1 BCUMOD 71 * CP13.4.1 ELOG0 (ECC error log) 72 * CP13.5.1 ELOG1 73 * CP13.6.1 ECAR0 (ECC error address) 74 * CP13.7.1 ECAR1 75 * CP13.8.1 ECTST (ECC test) 76 */ 77 78 #define BCUCTL_SR 0x00000001 /* single bit error report enable */ 79 #define BCUCTL_SC 0x00000004 /* single bit correct enable */ 80 #define BCUCTL_EE 0x00000008 /* ECC enable */ 81 #define BCUCTL_E0 0x10000000 /* ELOG0 valid */ 82 #define BCUCTL_E1 0x20000000 /* ELOG1 valid */ 83 #define BCUCTL_EV 0x40000000 /* error overflow */ 84 #define BCUCTL_TP 0x80000000 /* transactions pending */ 85 86 #define BCUMOD_AF 0x00000001 /* aligned fetch */ 87 88 #define ELOGx_SYN_MASK 0x000000ff /* ECC syndrome */ 89 #define ELOGx_ET_MASK 0x60000000 /* error type */ 90 #define ELOGx_ET_SB 0x00000000 /* single-bit */ 91 #define ELOGx_ET_MB 0x20000000 /* multi-bit */ 92 #define ELOGx_ET_BA 0x40000000 /* bus abort */ 93 #define ELOGx_RW 0x80000000 /* direction 0 = read 1 = write */ 94 95 #endif /* _ARM_XSCALE_I80200REG_H_ */ 96