1 /* $NetBSD: i80312_pci.c,v 1.9 2005/12/11 12:16:51 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for i80312 Companion I/O chip. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: i80312_pci.c,v 1.9 2005/12/11 12:16:51 christos Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/extent.h> 49 #include <sys/malloc.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <machine/bus.h> 54 55 #include <arm/xscale/i80312reg.h> 56 #include <arm/xscale/i80312var.h> 57 58 #include <dev/pci/ppbreg.h> 59 #include <dev/pci/pciconf.h> 60 61 #include "opt_pci.h" 62 #include "pci.h" 63 64 void i80312_pci_attach_hook(struct device *, struct device *, 65 struct pcibus_attach_args *); 66 int i80312_pci_bus_maxdevs(void *, int); 67 pcitag_t i80312_pci_make_tag(void *, int, int, int); 68 void i80312_pci_decompose_tag(void *, pcitag_t, int *, int *, 69 int *); 70 pcireg_t i80312_pci_conf_read(void *, pcitag_t, int); 71 void i80312_pci_conf_write(void *, pcitag_t, int, pcireg_t); 72 73 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 74 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 75 76 void 77 i80312_pci_init(pci_chipset_tag_t pc, void *cookie) 78 { 79 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 80 struct i80312_softc *sc = cookie; 81 struct extent *ioext, *memext; 82 pcireg_t binfo; 83 int pbus, sbus; 84 #endif 85 86 pc->pc_conf_v = cookie; 87 pc->pc_attach_hook = i80312_pci_attach_hook; 88 pc->pc_bus_maxdevs = i80312_pci_bus_maxdevs; 89 pc->pc_make_tag = i80312_pci_make_tag; 90 pc->pc_decompose_tag = i80312_pci_decompose_tag; 91 pc->pc_conf_read = i80312_pci_conf_read; 92 pc->pc_conf_write = i80312_pci_conf_write; 93 94 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 95 /* 96 * Configure the PCI bus. 97 * 98 * XXX We need to revisit this. We only configure the Secondary 99 * bus (and its children). The bus configure code needs changes 100 * to support how the busses are arranged on this chip. We also 101 * need to only configure devices in the private device space on 102 * the Secondary bus. 103 */ 104 105 binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO); 106 pbus = PPB_BUSINFO_PRIMARY(binfo); 107 sbus = PPB_BUSINFO_SECONDARY(binfo); 108 109 ioext = extent_create("pciio", sc->sc_sioout_base, 110 sc->sc_sioout_base + sc->sc_sioout_size - 1, 111 M_DEVBUF, NULL, 0, EX_NOWAIT); 112 memext = extent_create("pcimem", sc->sc_smemout_base, 113 sc->sc_smemout_base + sc->sc_smemout_size - 1, 114 M_DEVBUF, NULL, 0, EX_NOWAIT); 115 116 aprint_normal("%s: configuring Secondary PCI bus\n", sc->sc_dev.dv_xname); 117 pci_configure_bus(pc, ioext, memext, NULL, sbus, arm_dcache_align); 118 119 extent_destroy(ioext); 120 extent_destroy(memext); 121 #endif 122 } 123 124 void 125 pci_conf_interrupt(pci_chipset_tag_t pc, int a, int b, int c, int d, int *p) 126 { 127 } 128 129 void 130 i80312_pci_attach_hook(struct device *parent, struct device *self, 131 struct pcibus_attach_args *pba) 132 { 133 134 /* Nothing to do. */ 135 } 136 137 int 138 i80312_pci_bus_maxdevs(void *v, int busno) 139 { 140 141 return (32); 142 } 143 144 pcitag_t 145 i80312_pci_make_tag(void *v, int b, int d, int f) 146 { 147 148 return ((b << 16) | (d << 11) | (f << 8)); 149 } 150 151 void 152 i80312_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 153 { 154 155 if (bp != NULL) 156 *bp = (tag >> 16) & 0xff; 157 if (dp != NULL) 158 *dp = (tag >> 11) & 0x1f; 159 if (fp != NULL) 160 *fp = (tag >> 8) & 0x7; 161 } 162 163 struct pciconf_state { 164 bus_addr_t ps_addr_reg; 165 bus_addr_t ps_data_reg; 166 bus_addr_t ps_csr_reg; 167 uint32_t ps_addr_val; 168 169 int ps_b, ps_d, ps_f; 170 }; 171 172 static int 173 i80312_pci_conf_setup(struct i80312_softc *sc, pcitag_t tag, int offset, 174 struct pciconf_state *ps) 175 { 176 pcireg_t binfo; 177 int pbus, sbus; 178 179 i80312_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f); 180 181 binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO); 182 pbus = PPB_BUSINFO_PRIMARY(binfo); 183 sbus = PPB_BUSINFO_SECONDARY(binfo); 184 185 /* 186 * If the bus # is the Primary bus #, use the Primary 187 * Address/Data registers, otherwise use the Secondary 188 * Address/Data registers. 189 */ 190 if (ps->ps_b == pbus) { 191 ps->ps_addr_reg = I80312_ATU_POCCA; 192 ps->ps_data_reg = I80312_ATU_POCCD; 193 ps->ps_csr_reg = PCI_COMMAND_STATUS_REG; 194 } else { 195 ps->ps_addr_reg = I80312_ATU_SOCCA; 196 ps->ps_data_reg = I80312_ATU_SOCCD; 197 ps->ps_csr_reg = I80312_ATU_SACS; 198 } 199 200 /* 201 * If the bus # is the Primary or Secondary bus #, then use 202 * Type 0 cycles, else use Type 1. 203 * 204 * XXX We should filter out all non-private devices here! 205 * XXX How does private space interact with PCI-PCI bridges? 206 */ 207 if (ps->ps_b == pbus || ps->ps_b == sbus) { 208 if (ps->ps_d > (31 - 11)) 209 return (1); 210 ps->ps_addr_val = (1U << (ps->ps_d + 11)) | (ps->ps_f << 8) | 211 offset; 212 } else { 213 /* The tag is already in the correct format. */ 214 ps->ps_addr_val = tag | offset | 1; 215 } 216 217 return (0); 218 } 219 220 pcireg_t 221 i80312_pci_conf_read(void *v, pcitag_t tag, int offset) 222 { 223 struct i80312_softc *sc = v; 224 struct pciconf_state ps; 225 vaddr_t va; 226 pcireg_t rv; 227 u_int s; 228 229 if (i80312_pci_conf_setup(sc, tag, offset, &ps)) 230 return ((pcireg_t) -1); 231 232 PCI_CONF_LOCK(s); 233 234 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg, 235 ps.ps_addr_val); 236 237 va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh); 238 if (badaddr_read((void *) (va + ps.ps_data_reg), sizeof(rv), &rv)) { 239 /* 240 * Clear the Master Abort by reading the PCI 241 * Status Register. 242 */ 243 (void) bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 244 ps.ps_csr_reg); 245 #if 0 246 printf("conf_read: %d/%d/%d bad address\n", 247 ps.ps_b, ps.ps_d, ps.ps_f); 248 #endif 249 rv = (pcireg_t) -1; 250 } 251 252 PCI_CONF_UNLOCK(s); 253 254 return (rv); 255 } 256 257 void 258 i80312_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 259 { 260 struct i80312_softc *sc = v; 261 struct pciconf_state ps; 262 u_int s; 263 264 if (i80312_pci_conf_setup(sc, tag, offset, &ps)) 265 return; 266 267 PCI_CONF_LOCK(s); 268 269 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg, 270 ps.ps_addr_val); 271 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_data_reg, val); 272 273 PCI_CONF_UNLOCK(s); 274 } 275