xref: /netbsd/sys/arch/arm/xscale/i80321_aau.c (revision 6550d01e)
1 /*	$NetBSD: i80321_aau.c,v 1.14 2009/01/05 04:39:32 briggs Exp $	*/
2 
3 /*
4  * Copyright (c) 2002 Wasabi Systems, Inc.
5  * All rights reserved.
6  *
7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *	This product includes software developed for the NetBSD Project by
20  *	Wasabi Systems, Inc.
21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22  *    or promote products derived from this software without specific prior
23  *    written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35  * POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 /*
39  * Intel i80321 I/O Processor application accelerator unit support.
40  */
41 
42 #include <sys/cdefs.h>
43 __KERNEL_RCSID(0, "$NetBSD: i80321_aau.c,v 1.14 2009/01/05 04:39:32 briggs Exp $");
44 
45 #include <sys/param.h>
46 #include <sys/pool.h>
47 #include <sys/systm.h>
48 #include <sys/device.h>
49 #include <sys/uio.h>
50 #include <sys/bus.h>
51 #include <sys/intr.h>
52 
53 #include <uvm/uvm.h>
54 
55 #include <arm/xscale/i80321reg.h>
56 #include <arm/xscale/i80321var.h>
57 
58 #include <arm/xscale/iopaaureg.h>
59 #include <arm/xscale/iopaauvar.h>
60 
61 struct aau321_softc {
62 	/* Shared AAU definitions. */
63 	struct iopaau_softc sc_iopaau;
64 
65 	/* i80321-specific stuff. */
66 	void *sc_error_ih;
67 	void *sc_eoc_ih;
68 	void *sc_eot_ih;
69 };
70 
71 static struct iopaau_function aau321_func_zero = {
72 	.af_setup = iopaau_func_zero_setup,
73 };
74 
75 static struct iopaau_function aau321_func_fill8 = {
76 	.af_setup = iopaau_func_fill8_setup,
77 };
78 
79 static struct iopaau_function aau321_func_xor_1_4 = {
80 	.af_setup = iopaau_func_xor_setup,
81 };
82 
83 static struct iopaau_function aau321_func_xor_5_8 = {
84 	.af_setup = iopaau_func_xor_setup,
85 };
86 
87 static const struct dmover_algdesc aau321_algdescs[] = {
88 	{
89 	  .dad_name = DMOVER_FUNC_ZERO,
90 	  .dad_data = &aau321_func_zero,
91 	  .dad_ninputs = 0
92 	},
93 	{
94 	  .dad_name = DMOVER_FUNC_FILL8,
95 	  .dad_data = &aau321_func_fill8,
96 	  .dad_ninputs = 0
97 	},
98 	{
99 	  .dad_name = DMOVER_FUNC_COPY,
100 	  .dad_data = &aau321_func_xor_1_4,
101 	  .dad_ninputs = 1
102 	},
103 	{
104 	  .dad_name = DMOVER_FUNC_XOR2,
105 	  .dad_data = &aau321_func_xor_1_4,
106 	  .dad_ninputs = 2
107 	},
108 	{
109 	  .dad_name = DMOVER_FUNC_XOR3,
110 	  .dad_data = &aau321_func_xor_1_4,
111 	  .dad_ninputs = 3
112 	},
113 	{
114 	  .dad_name = DMOVER_FUNC_XOR4,
115 	  .dad_data = &aau321_func_xor_1_4,
116 	  .dad_ninputs = 4
117 	},
118 	{
119 	  .dad_name = DMOVER_FUNC_XOR5,
120 	  .dad_data = &aau321_func_xor_5_8,
121 	  5
122 	},
123 	{
124 	  .dad_name = DMOVER_FUNC_XOR6,
125 	  .dad_data = &aau321_func_xor_5_8,
126 	  .dad_ninputs = 6
127 	},
128 	{
129 	  .dad_name = DMOVER_FUNC_XOR7,
130 	  .dad_data = &aau321_func_xor_5_8,
131 	  .dad_ninputs = 7
132 	},
133 	{
134 	  .dad_name = DMOVER_FUNC_XOR8,
135 	  .dad_data = &aau321_func_xor_5_8,
136 	  .dad_ninputs = 8
137 	},
138 };
139 #define	AAU321_ALGDESC_COUNT	__arraycount(aau321_algdescs)
140 
141 static int
142 aau321_match(struct device *parent, struct cfdata *match, void *aux)
143 {
144 	struct iopxs_attach_args *ia = aux;
145 
146 	if (strcmp(match->cf_name, ia->ia_name) == 0)
147 		return (1);
148 
149 	return (0);
150 }
151 
152 static void
153 aau321_attach(struct device *parent, struct device *self, void *aux)
154 {
155 	struct aau321_softc *sc321 = (void *) self;
156 	struct iopaau_softc *sc = &sc321->sc_iopaau;
157 	struct iopxs_attach_args *ia = aux;
158 	int error;
159 
160 	aprint_naive("\n");
161 	aprint_normal("\n");
162 
163 	sc->sc_st = ia->ia_st;
164 	error = bus_space_subregion(sc->sc_st, ia->ia_sh,
165 	    ia->ia_offset, ia->ia_size, &sc->sc_sh);
166 	if (error) {
167 		aprint_error("%s: unable to subregion registers, error = %d\n",
168 		    sc->sc_dev.dv_xname, error);
169 		return;
170 	}
171 
172 	sc->sc_dmat = ia->ia_dmat;
173 
174 	sc321->sc_error_ih = i80321_intr_establish(ICU_INT_AAUE, IPL_BIO,
175 	    iopaau_intr, sc);
176 	if (sc321->sc_error_ih == NULL) {
177 		aprint_error("%s: unable to register error interrupt handler\n",
178 		    sc->sc_dev.dv_xname);
179 		return;
180 	}
181 
182 	sc321->sc_eoc_ih = i80321_intr_establish(ICU_INT_AAU_EOC, IPL_BIO,
183 	    iopaau_intr, sc);
184 	if (sc321->sc_eoc_ih == NULL) {
185 		aprint_error("%s: unable to register EOC interrupt handler\n",
186 		    sc->sc_dev.dv_xname);
187 		return;
188 	}
189 
190 	sc321->sc_eot_ih = i80321_intr_establish(ICU_INT_AAU_EOT, IPL_BIO,
191 	    iopaau_intr, sc);
192 	if (sc321->sc_eoc_ih == NULL) {
193 		aprint_error("%s: unable to register EOT interrupt handler\n",
194 		    sc->sc_dev.dv_xname);
195 		return;
196 	}
197 
198 	sc->sc_dmb.dmb_name = sc->sc_dev.dv_xname;
199 	sc->sc_dmb.dmb_speed = 1638400;			/* XXX */
200 	sc->sc_dmb.dmb_cookie = sc;
201 	sc->sc_dmb.dmb_algdescs = aau321_algdescs;
202 	sc->sc_dmb.dmb_nalgdescs = AAU321_ALGDESC_COUNT;
203 	sc->sc_dmb.dmb_process = iopaau_process;
204 
205 	iopaau_attach(sc);
206 
207 	/*
208 	 * These must be initialized after iopaau_attach()
209 	 * because iopaau_desc_[48]_cache is set up there.
210 	 */
211 	KASSERT(iopaau_desc_4_cache != NULL);
212 	aau321_func_zero.af_desc_cache = iopaau_desc_4_cache;
213 	aau321_func_fill8.af_desc_cache = iopaau_desc_4_cache;
214 	aau321_func_xor_1_4.af_desc_cache = iopaau_desc_4_cache;
215 
216 	KASSERT(iopaau_desc_8_cache != NULL);
217 	aau321_func_xor_5_8.af_desc_cache = iopaau_desc_8_cache;
218 }
219 
220 CFATTACH_DECL(iopaau, sizeof(struct aau321_softc),
221     aau321_match, aau321_attach, NULL, NULL);
222