1 /* $NetBSD: i80321_timer.c,v 1.3 2002/10/08 23:59:41 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Timer/clock support for the Intel i80321 I/O processor. 40 */ 41 42 #include "opt_perfctrs.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/time.h> 48 49 #include <machine/bus.h> 50 #include <arm/cpufunc.h> 51 52 #include <arm/xscale/i80321reg.h> 53 #include <arm/xscale/i80321var.h> 54 55 #include <arm/xscale/xscalevar.h> 56 57 void (*i80321_hardclock_hook)(void); 58 59 #define COUNTS_PER_SEC 200000000 /* 200MHz */ 60 #define COUNTS_PER_USEC (COUNTS_PER_SEC / 1000000) 61 62 static void *clock_ih; 63 64 static uint32_t counts_per_hz; 65 66 int clockhandler(void *); 67 68 static __inline uint32_t 69 tmr0_read(void) 70 { 71 uint32_t rv; 72 73 __asm __volatile("mrc p6, 0, %0, c0, c1, 0" 74 : "=r" (rv)); 75 return (rv); 76 } 77 78 static __inline void 79 tmr0_write(uint32_t val) 80 { 81 82 __asm __volatile("mcr p6, 0, %0, c0, c1, 0" 83 : 84 : "r" (val)); 85 } 86 87 static __inline uint32_t 88 tcr0_read(void) 89 { 90 uint32_t rv; 91 92 __asm __volatile("mrc p6, 0, %0, c2, c1, 0" 93 : "=r" (rv)); 94 return (rv); 95 } 96 97 static __inline void 98 tcr0_write(uint32_t val) 99 { 100 101 __asm __volatile("mcr p6, 0, %0, c2, c1, 0" 102 : 103 : "r" (val)); 104 } 105 106 static __inline void 107 trr0_write(uint32_t val) 108 { 109 110 __asm __volatile("mcr p6, 0, %0, c4, c1, 0" 111 : 112 : "r" (val)); 113 } 114 115 static __inline void 116 tisr_write(uint32_t val) 117 { 118 119 __asm __volatile("mcr p6, 0, %0, c6, c1, 0" 120 : 121 : "r" (val)); 122 } 123 124 /* 125 * i80321_calibrate_delay: 126 * 127 * Calibrate the delay loop. 128 */ 129 void 130 i80321_calibrate_delay(void) 131 { 132 133 /* 134 * Just use hz=100 for now -- we'll adjust it, if necessary, 135 * in cpu_initclocks(). 136 */ 137 counts_per_hz = COUNTS_PER_SEC / 100; 138 139 tmr0_write(0); /* stop timer */ 140 tisr_write(TISR_TMR0); /* clear interrupt */ 141 trr0_write(counts_per_hz); /* reload value */ 142 tcr0_write(counts_per_hz); /* current value */ 143 144 tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE); 145 } 146 147 /* 148 * cpu_initclocks: 149 * 150 * Initialize the clock and get them going. 151 */ 152 void 153 cpu_initclocks(void) 154 { 155 u_int oldirqstate; 156 #if defined(PERFCTRS) 157 void *pmu_ih; 158 #endif 159 160 if (hz < 50 || COUNTS_PER_SEC % hz) { 161 printf("Cannot get %d Hz clock; using 100 Hz\n", hz); 162 hz = 100; 163 } 164 tick = 1000000 / hz; /* number of microseconds between interrupts */ 165 tickfix = 1000000 - (hz * tick); 166 if (tickfix) { 167 int ftp; 168 169 ftp = min(ffs(tickfix), ffs(hz)); 170 tickfix >>= (ftp - 1); 171 tickfixinterval = hz >> (ftp - 1); 172 } 173 174 /* 175 * We only have one timer available; stathz and profhz are 176 * always left as 0 (the upper-layer clock code deals with 177 * this situation). 178 */ 179 if (stathz != 0) 180 printf("Cannot get %d Hz statclock\n", stathz); 181 stathz = 0; 182 183 if (profhz != 0) 184 printf("Cannot get %d Hz profclock\n", profhz); 185 profhz = 0; 186 187 /* Report the clock frequency. */ 188 printf("clock: hz=%d stathz=%d profhz=%d\n", hz, stathz, profhz); 189 190 oldirqstate = disable_interrupts(I32_bit); 191 192 /* Hook up the clock interrupt handler. */ 193 clock_ih = i80321_intr_establish(ICU_INT_TMR0, IPL_CLOCK, 194 clockhandler, NULL); 195 if (clock_ih == NULL) 196 panic("cpu_initclocks: unable to register timer interrupt"); 197 198 #if defined(PERFCTRS) 199 pmu_ih = i80321_intr_establish(ICU_INT_PMU, IPL_STATCLOCK, 200 xscale_pmc_dispatch, NULL); 201 if (pmu_ih == NULL) 202 panic("cpu_initclocks: unable to register timer interrupt"); 203 #endif 204 205 /* Set up the new clock parameters. */ 206 207 tmr0_write(0); /* stop timer */ 208 tisr_write(TISR_TMR0); /* clear interrupt */ 209 210 counts_per_hz = COUNTS_PER_SEC / hz; 211 212 trr0_write(counts_per_hz); /* reload value */ 213 tcr0_write(counts_per_hz); /* current value */ 214 215 tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE); 216 217 restore_interrupts(oldirqstate); 218 } 219 220 /* 221 * setstatclockrate: 222 * 223 * Set the rate of the statistics clock. 224 * 225 * We assume that hz is either stathz or profhz, and that neither 226 * will change after being set by cpu_initclocks(). We could 227 * recalculate the intervals here, but that would be a pain. 228 */ 229 void 230 setstatclockrate(int hz) 231 { 232 233 /* 234 * XXX Use TMR1? 235 */ 236 } 237 238 /* 239 * microtime: 240 * 241 * Fill in the specified timeval struct with the current time 242 * accurate to the microsecond. 243 */ 244 void 245 microtime(struct timeval *tvp) 246 { 247 static struct timeval lasttv; 248 u_int oldirqstate; 249 uint32_t counts; 250 251 oldirqstate = disable_interrupts(I32_bit); 252 253 counts = counts_per_hz - tcr0_read(); 254 255 /* Fill in the timeval struct. */ 256 *tvp = time; 257 tvp->tv_usec += (counts / COUNTS_PER_USEC); 258 259 /* Make sure microseconds doesn't overflow. */ 260 while (tvp->tv_usec >= 1000000) { 261 tvp->tv_usec -= 1000000; 262 tvp->tv_sec++; 263 } 264 265 /* Make sure the time has advanced. */ 266 if (tvp->tv_sec == lasttv.tv_sec && 267 tvp->tv_usec <= lasttv.tv_usec) { 268 tvp->tv_usec = lasttv.tv_usec + 1; 269 if (tvp->tv_usec >= 1000000) { 270 tvp->tv_usec -= 1000000; 271 tvp->tv_sec++; 272 } 273 } 274 275 lasttv = *tvp; 276 277 restore_interrupts(oldirqstate); 278 } 279 280 /* 281 * delay: 282 * 283 * Delay for at least N microseconds. 284 */ 285 void 286 delay(u_int n) 287 { 288 uint32_t cur, last, delta, usecs; 289 290 /* 291 * This works by polling the timer and counting the 292 * number of microseconds that go by. 293 */ 294 last = tcr0_read(); 295 delta = usecs = 0; 296 297 while (n > usecs) { 298 cur = tcr0_read(); 299 300 /* Check to see if the timer has wrapped around. */ 301 if (last < cur) 302 delta += (last + (counts_per_hz - cur)); 303 else 304 delta += (last - cur); 305 306 last = cur; 307 308 if (delta >= COUNTS_PER_USEC) { 309 usecs += delta / COUNTS_PER_USEC; 310 delta %= COUNTS_PER_USEC; 311 } 312 } 313 } 314 315 /* 316 * inittodr: 317 * 318 * Initialize time from the time-of-day register. 319 */ 320 void 321 inittodr(time_t base) 322 { 323 324 time.tv_sec = base; 325 time.tv_usec = 0; 326 } 327 328 /* 329 * resettodr: 330 * 331 * Reset the time-of-day register with the current time. 332 */ 333 void 334 resettodr(void) 335 { 336 } 337 338 /* 339 * clockhandler: 340 * 341 * Handle the hardclock interrupt. 342 */ 343 int 344 clockhandler(void *arg) 345 { 346 struct clockframe *frame = arg; 347 348 tisr_write(TISR_TMR0); 349 350 hardclock(frame); 351 352 if (i80321_hardclock_hook != NULL) 353 (*i80321_hardclock_hook)(); 354 355 return (1); 356 } 357