1 /* $NetBSD: i80321reg.h,v 1.3 2002/04/16 17:36:06 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _ARM_XSCALE_I80321REG_H_ 39 #define _ARM_XSCALE_I80321REG_H_ 40 41 /* 42 * Register definitions for the Intel 80321 (``Verde'') I/O processor, 43 * based on the XScale core. 44 */ 45 46 /* 47 * Base i80321 memory map: 48 * 49 * 0x0000.0000 - 0x7fff.ffff ATU Outbound Direct Addressing Window 50 * 0x8000.0000 - 0x9001.ffff ATU Outbound Translation Windows 51 * 0x9002.0000 - 0xffff.dfff External Memory 52 * 0xffff.e000 - 0xffff.e8ff Peripheral Memory Mapped Registers 53 * 0xffff.e900 - 0xffff.ffff Reserved 54 */ 55 56 #define VERDE_OUT_DIRECT_WIN_BASE 0x00000000UL 57 #define VERDE_OUT_DIRECT_WIN_SIZE 0x80000000UL 58 59 #define VERDE_OUT_XLATE_MEM_WIN_SIZE 0x04000000UL 60 #define VERDE_OUT_XLATE_IO_WIN_SIZE 0x00010000UL 61 62 #define VERDE_OUT_XLATE_MEM_WIN0_BASE 0x80000000UL 63 #define VERDE_OUT_XLATE_MEM_WIN1_BASE 0x84000000UL 64 65 #define VERDE_OUT_XLATE_IO_WIN0_BASE 0x90000000UL 66 67 #define VERDE_EXTMEM_BASE 0x90020000UL 68 69 #define VERDE_PMMR_BASE 0xffffe000UL 70 #define VERDE_PMMR_SIZE 0x00000900UL 71 72 /* 73 * Peripheral Memory Mapped Registers. Defined as offsets 74 * from the VERDE_PMMR_BASE. 75 */ 76 #define VERDE_ATU_BASE 0x0100 77 #define VERDE_ATU_SIZE 0x0100 78 79 #define VERDE_DMA_BASE 0x0400 80 #define VERDE_DMA_SIZE 0x0100 81 82 #define VERDE_MCU_BASE 0x0500 83 #define VERDE_MCU_SIZE 0x0100 84 85 #define VERDE_AAU_BASE 0x0800 86 #define VERDE_AAU_SIZE 0x0100 87 88 /* 89 * Address Translation Unit 90 */ 91 /* 0x00 - 0x38 -- PCI configuration space header */ 92 #define ATU_IALR0 0x40 /* Inbound ATU Limit 0 */ 93 #define ATU_IATVR0 0x44 /* Inbound ATU Xlate Value 0 */ 94 #define ATU_ERLR 0x48 /* Expansion ROM Limit */ 95 #define ATU_ERTVR 0x4c /* Expansion ROM Xlate Value */ 96 #define ATU_IALR1 0x50 /* Inbound ATU Limit 1 */ 97 #define ATU_IALR2 0x54 /* Inbound ATU Limit 2 */ 98 #define ATU_IATVR2 0x58 /* Inbound ATU Xlate Value 2 */ 99 #define ATU_OIOWTVR 0x5c /* Outbound I/O Window Xlate Value */ 100 #define ATU_OMWTVR0 0x60 /* Outbound Mem Window Xlate Value 0 */ 101 #define ATU_OUMWTVR0 0x64 /* Outbound Mem Window Xlate Value 0 Upper */ 102 #define ATU_OMWTVR1 0x68 /* Outbound Mem Window Xlate Value 1 */ 103 #define ATU_OUMWTVR1 0x6c /* Outbound Mem Window Xlate Value 1 Upper */ 104 #define ATU_OUDWTVR 0x78 /* Outbound Mem Direct Xlate Value Upper */ 105 #define ATU_ATUCR 0x80 /* ATU Configuration */ 106 #define ATU_PCSR 0x84 /* PCI Configuration and Status */ 107 #define ATU_ATUISR 0x88 /* ATU Interrupt Status */ 108 #define ATU_ATUIMR 0x8c /* ATU Interrupt Mask */ 109 #define ATU_IABAR3 0x90 /* Inbound ATU Base Address 3 */ 110 #define ATU_IAUBAR3 0x94 /* Inbound ATU Base Address 3 Upper */ 111 #define ATU_IALR3 0x98 /* Inbound ATU Limit 3 */ 112 #define ATU_IATVR3 0x9c /* Inbound ATU Xlate Value 3 */ 113 #define ATU_OCCAR 0xa4 /* Outbound Configuration Cycle Address */ 114 #define ATU_OCCDR 0xac /* Outbound Configuration Cycle Data */ 115 #define ATU_MSI_PORT 0xb4 /* MSI port */ 116 #define ATU_PDSCR 0xbc /* PCI Bus Drive Strength Control */ 117 #define ATU_PCI_X_CAP_ID 0xe0 /* (1) */ 118 #define ATU_PCI_X_NEXT 0xe1 /* (1) */ 119 #define ATU_PCIXCMD 0xe2 /* PCI-X Command Register (2) */ 120 #define ATU_PCIXSR 0xe4 /* PCI-X Status Register */ 121 122 #define ATUCR_DRC_ALIAS (1U << 19) 123 #define ATUCR_DAU2GXEN (1U << 18) 124 #define ATUCR_P_SERR_MA (1U << 16) 125 #define ATUCR_DTS (1U << 15) 126 #define ATUCR_P_SERR_DIE (1U << 9) 127 #define ATUCR_DAE (1U << 8) 128 #define ATUCR_BIST_IE (1U << 3) 129 #define ATUCR_OUT_EN (1U << 1) 130 131 #define PCSR_DAAAPE (1U << 18) 132 #define PCSR_PCI_X_CAP (3U << 16) 133 #define PCSR_PCI_X_CAP_BORING (0 << 16) 134 #define PCSR_PCI_X_CAP_66 (1U << 16) 135 #define PCSR_PCI_X_CAP_100 (2U << 16) 136 #define PCSR_PCI_X_CAP_133 (3U << 16) 137 #define PCSR_OTQB (1U << 15) 138 #define PCSR_IRTQB (1U << 14) 139 #define PCSR_DTV (1U << 12) 140 #define PCSR_BUS66 (1U << 10) 141 #define PCSR_BUS64 (1U << 8) 142 #define PCSR_RIB (1U << 5) 143 #define PCSR_RPB (1U << 4) 144 #define PCSR_CCR (1U << 2) 145 #define PCSR_CPR (1U << 1) 146 147 #define ATUISR_IMW1BU (1U << 14) 148 #define ATUISR_ISCEM (1U << 13) 149 #define ATUISR_RSCEM (1U << 12) 150 #define ATUISR_PST (1U << 11) 151 #define ATUISR_P_SERR_ASRT (1U << 10) 152 #define ATUISR_DPE (1U << 9) 153 #define ATUISR_BIST (1U << 8) 154 #define ATUISR_IBMA (1U << 7) 155 #define ATUISR_P_SERR_DET (1U << 4) 156 #define ATUISR_PMA (1U << 3) 157 #define ATUISR_PTAM (1U << 2) 158 #define ATUISR_PTAT (1U << 1) 159 #define ATUISR_PMPE (1U << 0) 160 161 #define ATUIMR_IMW1BU (1U << 11) 162 #define ATUIMR_ISCEM (1U << 10) 163 #define ATUIMR_RSCEM (1U << 9) 164 #define ATUIMR_PST (1U << 8) 165 #define ATUIMR_DPE (1U << 7) 166 #define ATUIMR_P_SERR_ASRT (1U << 6) 167 #define ATUIMR_PMA (1U << 5) 168 #define ATUIMR_PTAM (1U << 4) 169 #define ATUIMR_PTAT (1U << 3) 170 #define ATUIMR_PMPE (1U << 2) 171 #define ATUIMR_IE_SERR_EN (1U << 1) 172 #define ATUIMR_ECC_TAE (1U << 0) 173 174 #define PCIXCMD_MOST_1 (0 << 4) 175 #define PCIXCMD_MOST_2 (1 << 4) 176 #define PCIXCMD_MOST_3 (2 << 4) 177 #define PCIXCMD_MOST_4 (3 << 4) 178 #define PCIXCMD_MOST_8 (4 << 4) 179 #define PCIXCMD_MOST_12 (5 << 4) 180 #define PCIXCMD_MOST_16 (6 << 4) 181 #define PCIXCMD_MOST_32 (7 << 4) 182 #define PCIXCMD_MOST_MASK (7 << 4) 183 #define PCIXCMD_MMRBC_512 (0 << 2) 184 #define PCIXCMD_MMRBC_1024 (1 << 2) 185 #define PCIXCMD_MMRBC_2048 (2 << 2) 186 #define PCIXCMD_MMRBC_4096 (3 << 2) 187 #define PCIXCMD_MMRBC_MASK (3 << 2) 188 #define PCIXCMD_ERO (1U << 1) 189 #define PCIXCMD_DPERE (1U << 0) 190 191 #define PCIXSR_RSCEM (1U << 29) 192 #define PCIXSR_DMCRS_MASK (7 << 26) 193 #define PCIXSR_DMOST_MASK (7 << 23) 194 #define PCIXSR_COMPLEX (1U << 20) 195 #define PCIXSR_USC (1U << 19) 196 #define PCIXSR_SCD (1U << 18) 197 #define PCIXSR_133_CAP (1U << 17) 198 #define PCIXSR_32PCI (1U << 16) /* 0 = 32, 1 = 64 */ 199 #define PCIXSR_BUSNO(x) (((x) & 0xff) >> 8) 200 #define PCIXSR_DEVNO(x) (((x) & 0x1f) >> 3) 201 #define PCIXSR_FUNCNO(x) ((x) & 0x7) 202 203 /* 204 * Memory Controller Unit 205 */ 206 #define MCU_SDIR 0x00 /* DDR SDRAM Init. Register */ 207 #define MCU_SDCR 0x04 /* DDR SDRAM Control Register */ 208 #define MCU_SDBR 0x08 /* SDRAM Base Register */ 209 #define MCU_SBR0 0x0c /* SDRAM Boundary 0 */ 210 #define MCU_SBR1 0x10 /* SDRAM Boundary 1 */ 211 #define MCU_ECCR 0x34 /* ECC Control Register */ 212 #define MCU_ELOG0 0x38 /* ECC Log 0 */ 213 #define MCU_ELOG1 0x3c /* ECC Log 1 */ 214 #define MCU_ECAR0 0x40 /* ECC address 0 */ 215 #define MCU_ECAR1 0x44 /* ECC address 1 */ 216 #define MCU_ECTST 0x48 /* ECC test register */ 217 #define MCU_MCISR 0x4c /* MCU Interrupt Status Register */ 218 #define MCU_RFR 0x50 /* Refresh Frequency Register */ 219 #define MCU_DBUDSR 0x54 /* Data Bus Pull-up Drive Strength */ 220 #define MCU_DBDDSR 0x58 /* Data Bus Pull-down Drive Strength */ 221 #define MCU_CUDSR 0x5c /* Clock Pull-up Drive Strength */ 222 #define MCU_CDDSR 0x60 /* Clock Pull-down Drive Strength */ 223 #define MCU_CEUDSR 0x64 /* Clock En Pull-up Drive Strength */ 224 #define MCU_CEDDSR 0x68 /* Clock En Pull-down Drive Strength */ 225 #define MCU_CSUDSR 0x6c /* Chip Sel Pull-up Drive Strength */ 226 #define MCU_CSDDSR 0x70 /* Chip Sel Pull-down Drive Strength */ 227 #define MCU_REUDSR 0x74 /* Rx En Pull-up Drive Strength */ 228 #define MCU_REDDSR 0x78 /* Rx En Pull-down Drive Strength */ 229 #define MCU_ABUDSR 0x7c /* Addr Bus Pull-up Drive Strength */ 230 #define MCU_ABDDSR 0x80 /* Addr Bus Pull-down Drive Strength */ 231 #define MCU_DSDR 0x84 /* Data Strobe Delay Register */ 232 #define MCU_REDR 0x88 /* Rx Enable Delay Register */ 233 234 #define SDCR_DIMMTYPE (1U << 1) /* 0 = unbuf, 1 = reg */ 235 #define SDCR_BUSWIDTH (1U << 2) /* 0 = 64, 1 = 32 */ 236 237 #define SBRx_TECH (1U << 31) 238 #define SBRx_BOUND 0x0000003f 239 240 #define ECCR_SBERE (1U << 0) 241 #define ECCR_MBERE (1U << 1) 242 #define ECCR_SBECE (1U << 2) 243 #define ECCR_ECCEN (1U << 3) 244 245 #define ELOGx_SYNDROME 0x000000ff 246 #define ELOGx_ERRTYPE (1U << 8) /* 1 = multi-bit */ 247 #define ELOGx_RW (1U << 12) /* 1 = write error */ 248 /* 249 * Dev ID Func Requester 250 * 2 0 XScale core 251 * 2 1 ATU 252 * 13 0 DMA channel 0 253 * 13 1 DMA channel 1 254 * 26 0 ATU 255 */ 256 #define ELOGx_REQ_DEV(x) (((x) >> 19) & 0x1f) 257 #define ELOGx_REQ_FUNC(x) (((x) >> 16) & 0x3) 258 259 #define MCISR_ECC_ERR0 (1U << 0) 260 #define MCISR_ECC_ERR1 (1U << 1) 261 #define MCISR_ECC_ERRN (1U << 2) 262 263 /* 264 * Timers 265 * 266 * The i80321 timer registers are available in both memory-mapped 267 * and coprocessor spaces. Most of the registers are read-only 268 * if memory-mapped, so we access them via coprocessor space. 269 * 270 * TMR0 cp6 c0,1 0xffffe7e0 271 * TMR1 cp6 c1,1 0xffffe7e4 272 * TCR0 cp6 c2,1 0xffffe7e8 273 * TCR1 cp6 c3,1 0xffffe7ec 274 * TRR0 cp6 c4,1 0xffffe7f0 275 * TRR1 cp6 c5,1 0xffffe7f4 276 * TISR cp6 c6,1 0xffffe7f8 277 * WDTCR cp6 c7,1 0xffffe7fc 278 */ 279 280 #define TMRx_TC (1U << 0) 281 #define TMRx_ENABLE (1U << 1) 282 #define TMRx_RELOAD (1U << 2) 283 #define TMRx_CSEL_CORE (0 << 4) 284 #define TMRx_CSEL_CORE_div4 (1 << 4) 285 #define TMRx_CSEL_CORE_div8 (2 << 4) 286 #define TMRx_CSEL_CORE_div16 (3 << 4) 287 288 #define TISR_TMR0 (1U << 0) 289 #define TISR_TMR1 (1U << 1) 290 291 #define WTDCR_ENABLE1 0x1e1e1e1e 292 #define WTDCR_ENABLE2 0xe1e1e1e1 293 294 /* 295 * Interrupt Controller Unit. 296 * 297 * INTCTL cp6 c0,0 0xffffe7d0 298 * INTSTR cp6 c4,0 0xffffe7d4 299 * IINTSRC cp6 c8,0 0xffffe7d8 300 * FINTSRC cp6 c9,0 0xffffe7dc 301 * PIRSR 0xffffe2ec 302 */ 303 304 #define ICU_PIRSR 0x02ec 305 #define ICU_GPOE 0x07c4 306 #define ICU_GPID 0x07c8 307 #define ICU_GPOD 0x07cc 308 309 /* 310 * NOTE: WE USE THE `bitXX' BITS TO INDICATE PENDING SOFTWARE 311 * INTERRUPTS. See i80321_icu.c 312 */ 313 #define ICU_INT_HPI 31 /* high priority interrupt */ 314 #define ICU_INT_XINT(x) ((x) + 27) /* external interrupts */ 315 #define ICU_INT_bit26 26 316 #define ICU_INT_SSP 25 /* SSP serial port */ 317 #define ICU_INT_MUE 24 /* msg unit error */ 318 #define ICU_INT_AAUE 23 /* AAU error */ 319 #define ICU_INT_bit22 22 320 #define ICU_INT_DMA1E 21 /* DMA Ch 1 error */ 321 #define ICU_INT_DMA0E 20 /* DMA Ch 0 error */ 322 #define ICU_INT_MCUE 19 /* memory controller error */ 323 #define ICU_INT_ATUE 18 /* ATU error */ 324 #define ICU_INT_BIUE 17 /* bus interface unit error */ 325 #define ICU_INT_PMU 16 /* XScale PMU */ 326 #define ICU_INT_PPM 15 /* peripheral PMU */ 327 #define ICU_INT_BIST 14 /* ATU Start BIST */ 328 #define ICU_INT_MU 13 /* messaging unit */ 329 #define ICU_INT_I2C1 12 /* i2c unit 1 */ 330 #define ICU_INT_I2C0 11 /* i2c unit 0 */ 331 #define ICU_INT_TMR1 10 /* timer 1 */ 332 #define ICU_INT_TMR0 9 /* timer 0 */ 333 #define ICU_INT_CPPM 8 /* core processor PMU */ 334 #define ICU_INT_AAU_EOC 7 /* AAU end-of-chain */ 335 #define ICU_INT_AAU_EOT 6 /* AAU end-of-transfer */ 336 #define ICU_INT_bit5 5 337 #define ICU_INT_bit4 4 338 #define ICU_INT_DMA1_EOC 3 /* DMA1 end-of-chain */ 339 #define ICU_INT_DMA1_EOT 2 /* DMA1 end-of-transfer */ 340 #define ICU_INT_DMA0_EOC 1 /* DMA0 end-of-chain */ 341 #define ICU_INT_DMA0_EOT 0 /* DMA0 end-of-transfer */ 342 343 #define ICU_INT_HWMASK (0xffffffff & ~(ICU_INT_bit26|ICU_INT_bit22| \ 344 ICU_INT_bit5|ICU_INT_bit4)) 345 346 /* 347 * DMA Controller 348 */ 349 350 struct dma_chain_desc { 351 uint32_t dcd_nda; /* next descriptor address */ 352 uint32_t dcd_pad; /* PCI address (lower) */ 353 uint32_t dcd_puad; /* PCI address (upper) */ 354 uint32_t dcd_lad; /* local address */ 355 uint32_t dcd_bc; /* byte count */ 356 uint32_t dcd_dc; /* descriptor control */ 357 } __attribute__((__packed__)); 358 359 #define DMA_CHAN1_OFF 0x40 /* offset to channel 1 regs */ 360 361 #define DMA_CCR 0x00 /* channel control register */ 362 #define DMA_CSR 0x04 /* channel status register */ 363 #define DMA_DAR 0x0c /* descriptor address */ 364 #define DMA_DNAR 0x10 /* next descriptor address */ 365 #define DMA_PADR 0x14 /* PCI address (low) */ 366 #define DMA_PUADR 0x18 /* PCI address (high) */ 367 #define DMA_LADR 0x1c /* local address */ 368 #define DMA_BCR 0x20 /* byte count */ 369 #define DMA_DCR 0x24 /* descriptor control */ 370 371 #define DMA_CCR_CE (1U << 0) /* channel enable */ 372 #define DMA_CCR_CR (1U << 1) /* chain resume */ 373 374 #define DMA_SSR_STE (1U << 1) /* PCI-X split transaction error */ 375 #define DMA_SSR_TAF (1U << 2) /* PCI target abort flag */ 376 #define DMA_SSR_MAF (1U << 3) /* PCI master abort flag */ 377 #define DMA_SSR_IBMAF (1U << 5) /* Internal bus master abort flag */ 378 #define DMA_SSR_ECIF (1U << 8) /* end-of-chain interrupt */ 379 #define DMA_SSR_ETIF (1U << 9) /* end-of-transfer interrupt */ 380 #define DMA_SSR_CAF (1U << 10) /* channel active flag */ 381 382 #define DMA_BCR_MASK 0x00ffffff /* 24-bit count */ 383 384 #define DMA_DCR_TTYPE 0x0000000f /* PCI transaction type */ 385 #define DMA_DCR_IE (1U << 4) /* interrupt enable */ 386 #define DMA_DCR_DACE (1U << 5) /* dual address cycle enable */ 387 #define DMA_DCR_MMTE (1U << 6) /* memory->memory transfer enable */ 388 389 #define DMA_DCR_TTYPE_MR 0x06 /* Memory Read */ 390 #define DMA_DCR_TTYPE_MW 0x07 /* Memory Write */ 391 #define DMA_DCR_TTYPE_MRM 0x0c /* Memory Read Multiple */ 392 #define DMA_DCR_TTYPE_MRL 0x0e /* Memory Read Line */ 393 #define DMA_DCR_TTYPE_MW2 0x0f /* Memory Write */ 394 395 /* 396 * Application Accelerator Unit 397 */ 398 399 struct aau_chain_princ { 400 uint32_t acd_nda; /* next descriptor address */ 401 uint32_t acd_sar[4]; /* source address 0..3 */ 402 uint32_t acd_dar; /* destination address */ 403 uint32_t acd_bc; /* byte count */ 404 uint32_t acd_dc; /* descriptor control */ 405 } __attribute__((__packed__)); 406 407 struct aau_chain_mini { 408 uint32_t acd_sar[4]; /* source address 4..7 */ 409 } __attribute__((__packed__)); 410 411 struct aau_chain_ext { 412 uint32_t acd_edc; /* extended descriptor control */ 413 uint32_t acd_sar[8]; /* source address n..n+7 */ 414 } __attribute__((__packed__)); 415 416 struct aau_chain_desc8 { 417 struct aau_chain_princ acd8_princ; /* 0..3 */ 418 struct aau_chain_mini acd8_mini; /* 4..7 */ 419 } __attribute__((__packed__)); 420 421 struct aau_chain_desc16 { 422 struct aau_chain_princ acd16_princ; /* 0..3 */ 423 struct aau_chain_mini acd16_mini; /* 4..7 */ 424 struct aau_chain_ext acd16_ext0; /* 8..15 */ 425 } __attribute__((__packed__)); 426 427 struct aau_chain_desc32 { 428 struct aau_chain_princ acd32_princ; /* 0..3 */ 429 struct aau_chain_mini acd32_mini; /* 4..7 */ 430 struct aau_chain_ext acd32_ext0; /* 8..15 */ 431 struct aau_chain_ext acd32_ext1; /* 16..23 */ 432 struct aau_chain_ext acd32_ext2; /* 24..31 */ 433 } __attribute__((__packed__)); 434 435 #define AAU_ACR 0x00 /* accelerator control */ 436 #define AAU_ASR 0x04 /* accelerator status */ 437 #define AAU_ADAR 0x08 /* descriptor address */ 438 #define AAU_ANDAR 0x0c /* next descriptor address */ 439 #define AAU_DAR 0x20 /* destination address */ 440 #define AAU_ABCR 0x24 /* byte count */ 441 #define AAU_ADCR 0x28 /* descriptor control */ 442 #define AAU_EDCR0 0x3c /* extended descriptor control 0 */ 443 #define AAU_EDCR1 0x60 /* extended descriptor control 1 */ 444 #define AAU_EDCR2 0x84 /* extended descriptor control 2 */ 445 446 #define AAU_ACR_AAE (1U << 0) /* accelerator enable */ 447 #define AAU_ACR_CR (1U << 1) /* chain resume */ 448 #define AAU_ACR_512 (1U << 2) /* 512-byte buffer enable */ 449 450 #define AAU_ASR_MA (1U << 5) /* master abort */ 451 #define AAU_ASR_ECIF (1U << 8) /* end of chain interrupt */ 452 #define AAU_ASR_ETIF (1U << 9) /* end of transfer interrupt */ 453 #define AAU_ASR_AAF (1U << 10) /* acellerator active */ 454 455 #define AAU_ABCR_MASK 0x00ffffff /* 24-bit count */ 456 457 #define AAU_CMD_NULL 0 /* disregard this block */ 458 #define AAU_CMD_XOR 1 /* XOR */ 459 #define AAU_CMD_FILL 7 /* block fill */ 460 461 #define AAU_ADCR_IE (1U << 0) /* interrupt enable */ 462 #define AAU_ADCR_BxCMD(b, x) ((x) << (((b) * 3) + 1)) /* block 0..7 command */ 463 #define AAU_ADCR_SBCI_0 0 /* no supplemental blocks */ 464 #define AAU_ADCR_SBCI_4 (1U << 25) /* 4 supplemental blocks */ 465 #define AAU_ADCR_SBCI_12 (2U << 25) /* 12 supplemental blocks */ 466 #define AAU_ADCR_SBCI_28 (3U << 25) /* 28 supplemental blocks */ 467 #define AAU_ADCR_TC (1U << 28) /* transfer complete */ 468 #define AAU_ADCR_PBAD (1U << 29) /* computed parity bad */ 469 #define AAU_ADCR_PE (1U << 30) /* parity computation enable */ 470 #define AAU_ADCR_DWE (1U << 31) /* destination write enable */ 471 472 #define AAU_EDCR_BxCMD(b, x) ((x) << (((b) * 3) + 1)) 473 474 #endif /* _ARM_XSCALE_I80321REG_H_ */ 475