1*34c477d0Sskrll /* $NetBSD: ixp425_if_npe.c,v 1.53 2022/09/27 06:13:42 skrll Exp $ */
2bdea1361Sscw
3bdea1361Sscw /*-
4bdea1361Sscw * Copyright (c) 2006 Sam Leffler. All rights reserved.
5bdea1361Sscw *
6bdea1361Sscw * Redistribution and use in source and binary forms, with or without
7bdea1361Sscw * modification, are permitted provided that the following conditions
8bdea1361Sscw * are met:
9bdea1361Sscw * 1. Redistributions of source code must retain the above copyright
10bdea1361Sscw * notice, this list of conditions and the following disclaimer.
11bdea1361Sscw * 2. Redistributions in binary form must reproduce the above copyright
12bdea1361Sscw * notice, this list of conditions and the following disclaimer in the
13bdea1361Sscw * documentation and/or other materials provided with the distribution.
14bdea1361Sscw *
15bdea1361Sscw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16bdea1361Sscw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17bdea1361Sscw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18bdea1361Sscw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19bdea1361Sscw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20bdea1361Sscw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21bdea1361Sscw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22bdea1361Sscw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23bdea1361Sscw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24bdea1361Sscw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25bdea1361Sscw */
26bdea1361Sscw
27bdea1361Sscw #include <sys/cdefs.h>
28bdea1361Sscw #if 0
29bdea1361Sscw __FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/if_npe.c,v 1.1 2006/11/19 23:55:23 sam Exp $");
30bdea1361Sscw #endif
31*34c477d0Sskrll __KERNEL_RCSID(0, "$NetBSD: ixp425_if_npe.c,v 1.53 2022/09/27 06:13:42 skrll Exp $");
32bdea1361Sscw
33bdea1361Sscw /*
34bdea1361Sscw * Intel XScale NPE Ethernet driver.
35bdea1361Sscw *
36bdea1361Sscw * This driver handles the two ports present on the IXP425.
37bdea1361Sscw * Packet processing is done by the Network Processing Engines
38bdea1361Sscw * (NPE's) that work together with a MAC and PHY. The MAC
39bdea1361Sscw * is also mapped to the XScale cpu; the PHY is accessed via
40bdea1361Sscw * the MAC. NPE-XScale communication happens through h/w
41bdea1361Sscw * queues managed by the Q Manager block.
42bdea1361Sscw *
43bdea1361Sscw * The code here replaces the ethAcc, ethMii, and ethDB classes
44bdea1361Sscw * in the Intel Access Library (IAL) and the OS-specific driver.
45bdea1361Sscw *
46bdea1361Sscw * XXX add vlan support
47bdea1361Sscw * XXX NPE-C port doesn't work yet
48bdea1361Sscw */
49bdea1361Sscw
50bdea1361Sscw #include <sys/param.h>
51bdea1361Sscw #include <sys/systm.h>
52bdea1361Sscw #include <sys/kernel.h>
53bdea1361Sscw #include <sys/device.h>
54bdea1361Sscw #include <sys/callout.h>
55*34c477d0Sskrll #include <sys/kmem.h>
56bdea1361Sscw #include <sys/mbuf.h>
57bdea1361Sscw #include <sys/socket.h>
58bdea1361Sscw #include <sys/endian.h>
59bdea1361Sscw #include <sys/ioctl.h>
603589a8fdSmsaitoh #include <sys/syslog.h>
61af51edd2Sdyoung #include <sys/bus.h>
6212f4368bSmsaitoh #include <sys/rndsource.h>
63bdea1361Sscw
64bdea1361Sscw #include <net/if.h>
65bdea1361Sscw #include <net/if_dl.h>
66bdea1361Sscw #include <net/if_media.h>
67bdea1361Sscw #include <net/if_ether.h>
68bdea1361Sscw #include <net/bpf.h>
69bdea1361Sscw
70bdea1361Sscw #include <arm/xscale/ixp425reg.h>
71bdea1361Sscw #include <arm/xscale/ixp425var.h>
72bdea1361Sscw #include <arm/xscale/ixp425_qmgr.h>
73bdea1361Sscw #include <arm/xscale/ixp425_npevar.h>
74bdea1361Sscw #include <arm/xscale/ixp425_if_npereg.h>
75bdea1361Sscw
76bdea1361Sscw #include <dev/mii/miivar.h>
77bdea1361Sscw
78bdea1361Sscw #include "locators.h"
79bdea1361Sscw
80bdea1361Sscw struct npebuf {
81bdea1361Sscw struct npebuf *ix_next; /* chain to next buffer */
82bdea1361Sscw void *ix_m; /* backpointer to mbuf */
83bdea1361Sscw bus_dmamap_t ix_map; /* bus dma map for associated data */
84bdea1361Sscw struct npehwbuf *ix_hw; /* associated h/w block */
85bdea1361Sscw uint32_t ix_neaddr; /* phys address of ix_hw */
86bdea1361Sscw };
87bdea1361Sscw
88bdea1361Sscw struct npedma {
89bdea1361Sscw const char* name;
90bdea1361Sscw int nbuf; /* # npebuf's allocated */
91bdea1361Sscw bus_dmamap_t m_map;
92bdea1361Sscw struct npehwbuf *hwbuf; /* NPE h/w buffers */
93bdea1361Sscw bus_dmamap_t buf_map;
94bdea1361Sscw bus_addr_t buf_phys; /* phys addr of buffers */
95bdea1361Sscw struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */
96bdea1361Sscw };
97bdea1361Sscw
98bdea1361Sscw struct npe_softc {
99e20bd029Smatt device_t sc_dev;
100bdea1361Sscw struct ethercom sc_ethercom;
1013589a8fdSmsaitoh uint8_t sc_enaddr[ETHER_ADDR_LEN];
102bdea1361Sscw struct mii_data sc_mii;
103bdea1361Sscw bus_space_tag_t sc_iot;
104bdea1361Sscw bus_dma_tag_t sc_dt;
105bdea1361Sscw bus_space_handle_t sc_ioh; /* MAC register window */
106bdea1361Sscw bus_space_handle_t sc_miih; /* MII register window */
107bdea1361Sscw struct ixpnpe_softc *sc_npe; /* NPE support */
108bdea1361Sscw int sc_unit;
109bdea1361Sscw int sc_phy;
110bdea1361Sscw struct callout sc_tick_ch; /* Tick callout */
111bdea1361Sscw struct npedma txdma;
112bdea1361Sscw struct npebuf *tx_free; /* list of free tx buffers */
113bdea1361Sscw struct npedma rxdma;
114bdea1361Sscw int rx_qid; /* rx qid */
115bdea1361Sscw int rx_freeqid; /* rx free buffers qid */
116bdea1361Sscw int tx_qid; /* tx qid */
117bdea1361Sscw int tx_doneqid; /* tx completed qid */
118bdea1361Sscw struct npestats *sc_stats;
119bdea1361Sscw bus_dmamap_t sc_stats_map;
120bdea1361Sscw bus_addr_t sc_stats_phys; /* phys addr of sc_stats */
121397a83b3Smsaitoh u_short sc_if_flags; /* keep last if_flags */
1228e933452Stls krndsource_t rnd_source; /* random source */
123bdea1361Sscw };
124bdea1361Sscw
125bdea1361Sscw /*
126bdea1361Sscw * Per-unit static configuration for IXP425. The tx and
127bdea1361Sscw * rx free Q id's are fixed by the NPE microcode. The
128bdea1361Sscw * rx Q id's are programmed to be separate to simplify
129bdea1361Sscw * multi-port processing. It may be better to handle
130bdea1361Sscw * all traffic through one Q (as done by the Intel drivers).
131bdea1361Sscw *
132bdea1361Sscw * Note that the PHY's are accessible only from MAC A
133bdea1361Sscw * on the IXP425. This and other platform-specific
134bdea1361Sscw * assumptions probably need to be handled through hints.
135bdea1361Sscw */
136bdea1361Sscw static const struct {
137bdea1361Sscw const char *desc; /* device description */
138bdea1361Sscw int npeid; /* NPE assignment */
139227ae4c9Smsaitoh int macport; /* Port number of the MAC */
140bdea1361Sscw uint32_t imageid; /* NPE firmware image id */
141bdea1361Sscw uint32_t regbase;
142bdea1361Sscw int regsize;
143bdea1361Sscw uint32_t miibase;
144bdea1361Sscw int miisize;
145bdea1361Sscw uint8_t rx_qid;
146bdea1361Sscw uint8_t rx_freeqid;
147bdea1361Sscw uint8_t tx_qid;
148bdea1361Sscw uint8_t tx_doneqid;
149bdea1361Sscw } npeconfig[NPE_PORTS_MAX] = {
150bdea1361Sscw { .desc = "IXP NPE-B",
151bdea1361Sscw .npeid = NPE_B,
152227ae4c9Smsaitoh .macport = 0x10,
153bdea1361Sscw .imageid = IXP425_NPE_B_IMAGEID,
154bdea1361Sscw .regbase = IXP425_MAC_A_HWBASE,
155bdea1361Sscw .regsize = IXP425_MAC_A_SIZE,
156bdea1361Sscw .miibase = IXP425_MAC_A_HWBASE,
157bdea1361Sscw .miisize = IXP425_MAC_A_SIZE,
158bdea1361Sscw .rx_qid = 4,
159bdea1361Sscw .rx_freeqid = 27,
160bdea1361Sscw .tx_qid = 24,
161bdea1361Sscw .tx_doneqid = 31
162bdea1361Sscw },
163bdea1361Sscw { .desc = "IXP NPE-C",
164bdea1361Sscw .npeid = NPE_C,
165227ae4c9Smsaitoh .macport = 0x20,
166bdea1361Sscw .imageid = IXP425_NPE_C_IMAGEID,
167bdea1361Sscw .regbase = IXP425_MAC_B_HWBASE,
168bdea1361Sscw .regsize = IXP425_MAC_B_SIZE,
169bdea1361Sscw .miibase = IXP425_MAC_A_HWBASE,
170bdea1361Sscw .miisize = IXP425_MAC_A_SIZE,
171bdea1361Sscw .rx_qid = 12,
172bdea1361Sscw .rx_freeqid = 28,
173bdea1361Sscw .tx_qid = 25,
174bdea1361Sscw .tx_doneqid = 31
175bdea1361Sscw },
176bdea1361Sscw };
177bdea1361Sscw static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */
178bdea1361Sscw
179bdea1361Sscw static __inline uint32_t
RD4(struct npe_softc * sc,bus_size_t off)180bdea1361Sscw RD4(struct npe_softc *sc, bus_size_t off)
181bdea1361Sscw {
182bdea1361Sscw return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off);
183bdea1361Sscw }
184bdea1361Sscw
185bdea1361Sscw static __inline void
WR4(struct npe_softc * sc,bus_size_t off,uint32_t val)186bdea1361Sscw WR4(struct npe_softc *sc, bus_size_t off, uint32_t val)
187bdea1361Sscw {
188bdea1361Sscw bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val);
189bdea1361Sscw }
190bdea1361Sscw
191bdea1361Sscw static int npe_activate(struct npe_softc *);
192bdea1361Sscw #if 0
193bdea1361Sscw static void npe_deactivate(struct npe_softc *);
194bdea1361Sscw #endif
195cdc70479Smsaitoh static void npe_setmac(struct npe_softc *, const u_char *);
196cdc70479Smsaitoh static void npe_getmac(struct npe_softc *);
197cdc70479Smsaitoh static void npe_txdone(int, void *);
198bdea1361Sscw static int npe_rxbuf_init(struct npe_softc *, struct npebuf *,
199bdea1361Sscw struct mbuf *);
200cdc70479Smsaitoh static void npe_rxdone(int, void *);
201816cf5b8Smsaitoh static void npeinit_macreg(struct npe_softc *);
202bdea1361Sscw static int npeinit(struct ifnet *);
203227ae4c9Smsaitoh static void npeinit_resetcb(void *);
204816cf5b8Smsaitoh static void npeinit_locked(void *);
205bdea1361Sscw static void npestart(struct ifnet *);
206bdea1361Sscw static void npestop(struct ifnet *, int);
207bdea1361Sscw static void npewatchdog(struct ifnet *);
208cdc70479Smsaitoh static int npeioctl(struct ifnet *, u_long, void *);
209bdea1361Sscw
210cdc70479Smsaitoh static int npe_setrxqosentry(struct npe_softc *, int, int, int);
211bdea1361Sscw static int npe_updatestats(struct npe_softc *);
212bdea1361Sscw #if 0
213bdea1361Sscw static int npe_getstats(struct npe_softc *);
214bdea1361Sscw static uint32_t npe_getimageid(struct npe_softc *);
215cdc70479Smsaitoh static int npe_setloopback(struct npe_softc *, int);
216bdea1361Sscw #endif
217bdea1361Sscw
218e746222fSmsaitoh static int npe_miibus_readreg(device_t, int, int, uint16_t *);
219e746222fSmsaitoh static int npe_miibus_writereg(device_t, int, int, uint16_t);
220e20bd029Smatt static void npe_miibus_statchg(struct ifnet *);
221bdea1361Sscw
222bdea1361Sscw static int npe_debug;
223bdea1361Sscw #define DPRINTF(sc, fmt, ...) do { \
224bdea1361Sscw if (npe_debug) printf(fmt, __VA_ARGS__); \
225bdea1361Sscw } while (0)
226bdea1361Sscw #define DPRINTFn(n, sc, fmt, ...) do { \
227bdea1361Sscw if (npe_debug >= n) printf(fmt, __VA_ARGS__); \
228bdea1361Sscw } while (0)
229bdea1361Sscw
230bdea1361Sscw #define NPE_TXBUF 128
231bdea1361Sscw #define NPE_RXBUF 64
232bdea1361Sscw
2333589a8fdSmsaitoh #define MAC2UINT64(addr) (((uint64_t)addr[0] << 40) \
2343589a8fdSmsaitoh + ((uint64_t)addr[1] << 32) \
2353589a8fdSmsaitoh + ((uint64_t)addr[2] << 24) \
2363589a8fdSmsaitoh + ((uint64_t)addr[3] << 16) \
2373589a8fdSmsaitoh + ((uint64_t)addr[4] << 8) \
2383589a8fdSmsaitoh + (uint64_t)addr[5])
2393589a8fdSmsaitoh
240bdea1361Sscw /* NB: all tx done processing goes through one queue */
241bdea1361Sscw static int tx_doneqid = -1;
242bdea1361Sscw
2433589a8fdSmsaitoh void (*npe_getmac_md)(int, uint8_t *);
2443589a8fdSmsaitoh
245e20bd029Smatt static int npe_match(device_t, cfdata_t, void *);
246e20bd029Smatt static void npe_attach(device_t, device_t, void *);
247bdea1361Sscw
248e20bd029Smatt CFATTACH_DECL_NEW(npe, sizeof(struct npe_softc),
249bdea1361Sscw npe_match, npe_attach, NULL, NULL);
250bdea1361Sscw
251bdea1361Sscw static int
npe_match(device_t parent,cfdata_t cf,void * arg)252e20bd029Smatt npe_match(device_t parent, cfdata_t cf, void *arg)
253bdea1361Sscw {
254bdea1361Sscw struct ixpnpe_attach_args *na = arg;
255bdea1361Sscw
256bdea1361Sscw return (na->na_unit == NPE_B || na->na_unit == NPE_C);
257bdea1361Sscw }
258bdea1361Sscw
259bdea1361Sscw static void
npe_attach(device_t parent,device_t self,void * arg)260e20bd029Smatt npe_attach(device_t parent, device_t self, void *arg)
261bdea1361Sscw {
262e20bd029Smatt struct npe_softc *sc = device_private(self);
263e20bd029Smatt struct ixpnpe_softc *isc = device_private(parent);
264bdea1361Sscw struct ixpnpe_attach_args *na = arg;
265bdea1361Sscw struct ifnet *ifp;
266cdc70479Smsaitoh struct mii_data * const mii = &sc->sc_mii;
267bdea1361Sscw
268bdea1361Sscw aprint_naive("\n");
269bdea1361Sscw aprint_normal(": Ethernet co-processor\n");
270bdea1361Sscw
271e20bd029Smatt sc->sc_dev = self;
272bdea1361Sscw sc->sc_iot = na->na_iot;
273bdea1361Sscw sc->sc_dt = na->na_dt;
274bdea1361Sscw sc->sc_npe = na->na_npe;
275bdea1361Sscw sc->sc_unit = (na->na_unit == NPE_B) ? 0 : 1;
276bdea1361Sscw sc->sc_phy = na->na_phy;
277bdea1361Sscw
278bdea1361Sscw memset(&sc->sc_ethercom, 0, sizeof(sc->sc_ethercom));
279cdc70479Smsaitoh memset(mii, 0, sizeof(*mii));
280bdea1361Sscw
28188ab7da9Sad callout_init(&sc->sc_tick_ch, 0);
282bdea1361Sscw
283bdea1361Sscw if (npe_activate(sc)) {
284e20bd029Smatt aprint_error_dev(sc->sc_dev,
285e20bd029Smatt "Failed to activate NPE (missing microcode?)\n");
286bdea1361Sscw return;
287bdea1361Sscw }
288bdea1361Sscw
2893589a8fdSmsaitoh npe_getmac(sc);
290b9c2a505Smsaitoh npeinit_macreg(sc);
291bdea1361Sscw
292e20bd029Smatt aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
2933589a8fdSmsaitoh ether_sprintf(sc->sc_enaddr));
294bdea1361Sscw
295bdea1361Sscw ifp = &sc->sc_ethercom.ec_if;
296cdc70479Smsaitoh mii->mii_ifp = ifp;
297cdc70479Smsaitoh mii->mii_readreg = npe_miibus_readreg;
298cdc70479Smsaitoh mii->mii_writereg = npe_miibus_writereg;
299cdc70479Smsaitoh mii->mii_statchg = npe_miibus_statchg;
300cdc70479Smsaitoh sc->sc_ethercom.ec_mii = mii;
301bdea1361Sscw
302cdc70479Smsaitoh ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange,
3032f5b2d52Sthorpej ether_mediastatus);
304273cfb27Smsaitoh
305cdc70479Smsaitoh mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY,
306273cfb27Smsaitoh MII_OFFSET_ANY, MIIF_DOPAUSE);
307cdc70479Smsaitoh if (LIST_FIRST(&mii->mii_phys) == NULL) {
308cdc70479Smsaitoh ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
309cdc70479Smsaitoh ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
310273cfb27Smsaitoh } else
311cdc70479Smsaitoh ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
312bdea1361Sscw
313bdea1361Sscw ifp->if_softc = sc;
314e20bd029Smatt strcpy(ifp->if_xname, device_xname(sc->sc_dev));
315bdea1361Sscw ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
316bdea1361Sscw ifp->if_start = npestart;
317bdea1361Sscw ifp->if_ioctl = npeioctl;
318bdea1361Sscw ifp->if_watchdog = npewatchdog;
319bdea1361Sscw ifp->if_init = npeinit;
320bdea1361Sscw ifp->if_stop = npestop;
321bdea1361Sscw IFQ_SET_READY(&ifp->if_snd);
322bdea1361Sscw
3238586a845Smsaitoh /* VLAN capable */
3248586a845Smsaitoh sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
3258586a845Smsaitoh
326bdea1361Sscw if_attach(ifp);
327e3a04365Snonaka if_deferred_start_init(ifp, NULL);
3283589a8fdSmsaitoh ether_ifattach(ifp, sc->sc_enaddr);
329e20bd029Smatt rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
330a72ef114Stls RND_TYPE_NET, RND_FLAG_DEFAULT);
331227ae4c9Smsaitoh
332227ae4c9Smsaitoh /* callback function to reset MAC */
333227ae4c9Smsaitoh isc->macresetcbfunc = npeinit_resetcb;
334227ae4c9Smsaitoh isc->macresetcbarg = sc;
335bdea1361Sscw }
336bdea1361Sscw
337bdea1361Sscw /*
338bdea1361Sscw * Compute and install the multicast filter.
339bdea1361Sscw */
340bdea1361Sscw static void
npe_setmcast(struct npe_softc * sc)341bdea1361Sscw npe_setmcast(struct npe_softc *sc)
342bdea1361Sscw {
343cdc70479Smsaitoh struct ethercom *ec = &sc->sc_ethercom;
344cdc70479Smsaitoh struct ifnet *ifp = &ec->ec_if;
345bdea1361Sscw uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN];
3463589a8fdSmsaitoh uint32_t reg;
347227ae4c9Smsaitoh uint32_t msg[2];
348bdea1361Sscw int i;
349bdea1361Sscw
3503589a8fdSmsaitoh /* Always use filter. Is here a correct position? */
3513589a8fdSmsaitoh reg = RD4(sc, NPE_MAC_RX_CNTRL1);
3523589a8fdSmsaitoh WR4(sc, NPE_MAC_RX_CNTRL1, reg | NPE_RX_CNTRL1_ADDR_FLTR_EN);
3533589a8fdSmsaitoh
354bdea1361Sscw if (ifp->if_flags & IFF_PROMISC) {
355bdea1361Sscw memset(mask, 0, ETHER_ADDR_LEN);
356bdea1361Sscw memset(addr, 0, ETHER_ADDR_LEN);
357bdea1361Sscw } else if (ifp->if_flags & IFF_ALLMULTI) {
358bdea1361Sscw static const uint8_t allmulti[ETHER_ADDR_LEN] =
359bdea1361Sscw { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
360bdea1361Sscw all_multi:
361bdea1361Sscw memcpy(mask, allmulti, ETHER_ADDR_LEN);
362bdea1361Sscw memcpy(addr, allmulti, ETHER_ADDR_LEN);
363bdea1361Sscw } else {
364bdea1361Sscw uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN];
365bdea1361Sscw struct ether_multistep step;
366bdea1361Sscw struct ether_multi *enm;
367bdea1361Sscw
368bdea1361Sscw memset(clr, 0, ETHER_ADDR_LEN);
369bdea1361Sscw memset(set, 0xff, ETHER_ADDR_LEN);
370bdea1361Sscw
371f515fb39Smsaitoh ETHER_LOCK(ec);
372cdc70479Smsaitoh ETHER_FIRST_MULTI(step, ec, enm);
373bdea1361Sscw while (enm != NULL) {
37412f4368bSmsaitoh if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
37512f4368bSmsaitoh ETHER_ADDR_LEN)) {
376bdea1361Sscw ifp->if_flags |= IFF_ALLMULTI;
377f515fb39Smsaitoh ETHER_UNLOCK(ec);
378bdea1361Sscw goto all_multi;
379bdea1361Sscw }
380bdea1361Sscw
381bdea1361Sscw for (i = 0; i < ETHER_ADDR_LEN; i++) {
382bdea1361Sscw clr[i] |= enm->enm_addrlo[i];
383bdea1361Sscw set[i] &= enm->enm_addrlo[i];
384bdea1361Sscw }
385bdea1361Sscw
386bdea1361Sscw ETHER_NEXT_MULTI(step, enm);
387bdea1361Sscw }
388f515fb39Smsaitoh ETHER_UNLOCK(ec);
389bdea1361Sscw
390bdea1361Sscw for (i = 0; i < ETHER_ADDR_LEN; i++) {
391bdea1361Sscw mask[i] = set[i] | ~clr[i];
392bdea1361Sscw addr[i] = set[i];
393bdea1361Sscw }
394bdea1361Sscw }
395bdea1361Sscw
396bdea1361Sscw /*
397bdea1361Sscw * Write the mask and address registers.
398bdea1361Sscw */
399bdea1361Sscw for (i = 0; i < ETHER_ADDR_LEN; i++) {
400bdea1361Sscw WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]);
401bdea1361Sscw WR4(sc, NPE_MAC_ADDR(i), addr[i]);
402bdea1361Sscw }
403227ae4c9Smsaitoh
404227ae4c9Smsaitoh msg[0] = NPE_ADDRESSFILTERCONFIG << NPE_MAC_MSGID_SHL
405227ae4c9Smsaitoh | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL);
406227ae4c9Smsaitoh msg[1] = ((ifp->if_flags & IFF_PROMISC) ? 1 : 0) << 24
407227ae4c9Smsaitoh | ((RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff) << 16)
408227ae4c9Smsaitoh | (addr[5] << 8) | mask[5];
409227ae4c9Smsaitoh ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
410bdea1361Sscw }
411bdea1361Sscw
412bdea1361Sscw static int
npe_dma_setup(struct npe_softc * sc,struct npedma * dma,const char * name,int nbuf,int maxseg)413bdea1361Sscw npe_dma_setup(struct npe_softc *sc, struct npedma *dma,
414bdea1361Sscw const char *name, int nbuf, int maxseg)
415bdea1361Sscw {
416bdea1361Sscw bus_dma_segment_t seg;
417bdea1361Sscw int rseg, error, i;
41853524e44Schristos void *hwbuf;
419bdea1361Sscw size_t size;
420bdea1361Sscw
4218586a845Smsaitoh memset(dma, 0, sizeof(*dma));
422bdea1361Sscw
423bdea1361Sscw dma->name = name;
424bdea1361Sscw dma->nbuf = nbuf;
425bdea1361Sscw
426bdea1361Sscw size = nbuf * sizeof(struct npehwbuf);
427bdea1361Sscw
428bdea1361Sscw /* XXX COHERENT for now */
429bdea1361Sscw error = bus_dmamem_alloc(sc->sc_dt, size, sizeof(uint32_t), 0, &seg,
430bdea1361Sscw 1, &rseg, BUS_DMA_NOWAIT);
431bdea1361Sscw if (error) {
432e20bd029Smatt aprint_error_dev(sc->sc_dev,
433e20bd029Smatt "unable to %s for %s %s buffers, error %u\n",
434e20bd029Smatt "allocate memory", dma->name, "h/w", error);
435bdea1361Sscw }
436bdea1361Sscw
437bdea1361Sscw error = bus_dmamem_map(sc->sc_dt, &seg, 1, size, &hwbuf,
438bdea1361Sscw BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE);
439bdea1361Sscw if (error) {
440e20bd029Smatt aprint_error_dev(sc->sc_dev,
441e20bd029Smatt "unable to %s for %s %s buffers, error %u\n",
442e20bd029Smatt "map memory", dma->name, "h/w", error);
443bdea1361Sscw free_dmamem:
444bdea1361Sscw bus_dmamem_free(sc->sc_dt, &seg, rseg);
445bdea1361Sscw return error;
446bdea1361Sscw }
447bdea1361Sscw dma->hwbuf = (void *)hwbuf;
448bdea1361Sscw
449bdea1361Sscw error = bus_dmamap_create(sc->sc_dt, size, 1, size, 0,
450bdea1361Sscw BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dma->buf_map);
451bdea1361Sscw if (error) {
452e20bd029Smatt aprint_error_dev(sc->sc_dev,
453e20bd029Smatt "unable to %s for %s %s buffers, error %u\n",
454e20bd029Smatt "create map", dma->name, "h/w", error);
455bdea1361Sscw unmap_dmamem:
456bdea1361Sscw dma->hwbuf = NULL;
457bdea1361Sscw bus_dmamem_unmap(sc->sc_dt, hwbuf, size);
458bdea1361Sscw goto free_dmamem;
459bdea1361Sscw }
460bdea1361Sscw
461bdea1361Sscw error = bus_dmamap_load(sc->sc_dt, dma->buf_map, hwbuf, size, NULL,
462bdea1361Sscw BUS_DMA_NOWAIT);
463bdea1361Sscw if (error) {
464e20bd029Smatt aprint_error_dev(sc->sc_dev,
465e20bd029Smatt "unable to %s for %s %s buffers, error %u\n",
466e20bd029Smatt "load map", dma->name, "h/w", error);
467bdea1361Sscw bus_dmamap_destroy(sc->sc_dt, dma->buf_map);
468bdea1361Sscw goto unmap_dmamem;
469bdea1361Sscw }
470bdea1361Sscw
471*34c477d0Sskrll dma->buf = kmem_zalloc(nbuf * sizeof(struct npebuf), KM_SLEEP);
472bdea1361Sscw dma->buf_phys = dma->buf_map->dm_segs[0].ds_addr;
473bdea1361Sscw for (i = 0; i < dma->nbuf; i++) {
474bdea1361Sscw struct npebuf *npe = &dma->buf[i];
475bdea1361Sscw struct npehwbuf *hw = &dma->hwbuf[i];
476bdea1361Sscw
47712f4368bSmsaitoh /* Calculate offset to shared area */
478bdea1361Sscw npe->ix_neaddr = dma->buf_phys +
479bdea1361Sscw ((uintptr_t)hw - (uintptr_t)dma->hwbuf);
480bdea1361Sscw KASSERT((npe->ix_neaddr & 0x1f) == 0);
4818586a845Smsaitoh error = bus_dmamap_create(sc->sc_dt, MCLBYTES, maxseg,
482bdea1361Sscw MCLBYTES, 0, 0, &npe->ix_map);
483bdea1361Sscw if (error != 0) {
484e20bd029Smatt aprint_error_dev(sc->sc_dev,
485e20bd029Smatt "unable to %s for %s buffer %u, error %u\n",
486e20bd029Smatt "create dmamap", dma->name, i, error);
487bdea1361Sscw /* XXXSCW: Free up maps... */
488bdea1361Sscw return error;
489bdea1361Sscw }
490bdea1361Sscw npe->ix_hw = hw;
491bdea1361Sscw }
492bdea1361Sscw bus_dmamap_sync(sc->sc_dt, dma->buf_map, 0, dma->buf_map->dm_mapsize,
493bdea1361Sscw BUS_DMASYNC_PREWRITE);
494bdea1361Sscw return 0;
495bdea1361Sscw }
496bdea1361Sscw
497bdea1361Sscw #if 0
498bdea1361Sscw static void
499bdea1361Sscw npe_dma_destroy(struct npe_softc *sc, struct npedma *dma)
500bdea1361Sscw {
501bdea1361Sscw int i;
502bdea1361Sscw
503bdea1361Sscw /* XXXSCW: Clean this up */
504bdea1361Sscw
505bdea1361Sscw if (dma->hwbuf != NULL) {
506bdea1361Sscw for (i = 0; i < dma->nbuf; i++) {
507bdea1361Sscw struct npebuf *npe = &dma->buf[i];
508bdea1361Sscw bus_dmamap_destroy(sc->sc_dt, npe->ix_map);
509bdea1361Sscw }
510bdea1361Sscw bus_dmamap_unload(sc->sc_dt, dma->buf_map);
51153524e44Schristos bus_dmamem_free(sc->sc_dt, (void *)dma->hwbuf, dma->buf_map);
512bdea1361Sscw bus_dmamap_destroy(sc->sc_dt, dma->buf_map);
513bdea1361Sscw }
514bdea1361Sscw if (dma->buf != NULL)
515*34c477d0Sskrll kmem_free(dma->buf, dma->nbuf * sizeof(struct npebuf));
516bdea1361Sscw memset(dma, 0, sizeof(*dma));
517bdea1361Sscw }
518bdea1361Sscw #endif
519bdea1361Sscw
520bdea1361Sscw static int
npe_activate(struct npe_softc * sc)521bdea1361Sscw npe_activate(struct npe_softc *sc)
522bdea1361Sscw {
523bdea1361Sscw bus_dma_segment_t seg;
524bdea1361Sscw int unit = sc->sc_unit;
525bdea1361Sscw int error, i, rseg;
52653524e44Schristos void *statbuf;
527bdea1361Sscw
528bdea1361Sscw /* load NPE firmware and start it running */
529bdea1361Sscw error = ixpnpe_init(sc->sc_npe, "npe_fw", npeconfig[unit].imageid);
530bdea1361Sscw if (error != 0)
531bdea1361Sscw return error;
532bdea1361Sscw
533bdea1361Sscw if (bus_space_map(sc->sc_iot, npeconfig[unit].regbase,
534bdea1361Sscw npeconfig[unit].regsize, 0, &sc->sc_ioh)) {
535e20bd029Smatt aprint_error_dev(sc->sc_dev, "Cannot map registers 0x%x:0x%x\n",
536e20bd029Smatt npeconfig[unit].regbase, npeconfig[unit].regsize);
537bdea1361Sscw return ENOMEM;
538bdea1361Sscw }
539bdea1361Sscw
540bdea1361Sscw if (npeconfig[unit].miibase != npeconfig[unit].regbase) {
541bdea1361Sscw /*
542bdea1361Sscw * The PHY's are only accessible from one MAC (it appears)
543bdea1361Sscw * so for other MAC's setup an additional mapping for
544bdea1361Sscw * frobbing the PHY registers.
545bdea1361Sscw */
546bdea1361Sscw if (bus_space_map(sc->sc_iot, npeconfig[unit].miibase,
547bdea1361Sscw npeconfig[unit].miisize, 0, &sc->sc_miih)) {
548e20bd029Smatt aprint_error_dev(sc->sc_dev,
549e20bd029Smatt "Cannot map MII registers 0x%x:0x%x\n",
550e20bd029Smatt npeconfig[unit].miibase, npeconfig[unit].miisize);
551bdea1361Sscw return ENOMEM;
552bdea1361Sscw }
553bdea1361Sscw } else
554bdea1361Sscw sc->sc_miih = sc->sc_ioh;
555bdea1361Sscw error = npe_dma_setup(sc, &sc->txdma, "tx", NPE_TXBUF, NPE_MAXSEG);
556bdea1361Sscw if (error != 0)
557bdea1361Sscw return error;
558bdea1361Sscw error = npe_dma_setup(sc, &sc->rxdma, "rx", NPE_RXBUF, 1);
559bdea1361Sscw if (error != 0)
560bdea1361Sscw return error;
561bdea1361Sscw
562bdea1361Sscw /* setup statistics block */
563bdea1361Sscw error = bus_dmamem_alloc(sc->sc_dt, sizeof(struct npestats),
564bdea1361Sscw sizeof(uint32_t), 0, &seg, 1, &rseg, BUS_DMA_NOWAIT);
565bdea1361Sscw if (error) {
566e20bd029Smatt aprint_error_dev(sc->sc_dev,
567e20bd029Smatt "unable to %s for %s, error %u\n",
568e20bd029Smatt "allocate memory", "stats block", error);
569bdea1361Sscw return error;
570bdea1361Sscw }
571bdea1361Sscw
572bdea1361Sscw error = bus_dmamem_map(sc->sc_dt, &seg, 1, sizeof(struct npestats),
573bdea1361Sscw &statbuf, BUS_DMA_NOWAIT);
574bdea1361Sscw if (error) {
575e20bd029Smatt aprint_error_dev(sc->sc_dev,
576e20bd029Smatt "unable to %s for %s, error %u\n",
577e20bd029Smatt "map memory", "stats block", error);
578bdea1361Sscw return error;
579bdea1361Sscw }
580bdea1361Sscw sc->sc_stats = (void *)statbuf;
581bdea1361Sscw
582bdea1361Sscw error = bus_dmamap_create(sc->sc_dt, sizeof(struct npestats), 1,
583bdea1361Sscw sizeof(struct npestats), 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
584bdea1361Sscw &sc->sc_stats_map);
585bdea1361Sscw if (error) {
586e20bd029Smatt aprint_error_dev(sc->sc_dev,
587e20bd029Smatt "unable to %s for %s, error %u\n",
588e20bd029Smatt "create map", "stats block", error);
589bdea1361Sscw return error;
590bdea1361Sscw }
591bdea1361Sscw
59246710031Smaxv error = bus_dmamap_load(sc->sc_dt, sc->sc_stats_map, sc->sc_stats,
59346710031Smaxv sizeof(struct npestats), NULL, BUS_DMA_NOWAIT);
59446710031Smaxv if (error) {
595e20bd029Smatt aprint_error_dev(sc->sc_dev,
596e20bd029Smatt "unable to %s for %s, error %u\n",
597e20bd029Smatt "load map", "stats block", error);
598bdea1361Sscw return error;
599bdea1361Sscw }
600bdea1361Sscw sc->sc_stats_phys = sc->sc_stats_map->dm_segs[0].ds_addr;
601bdea1361Sscw
602bdea1361Sscw /* XXX disable half-bridge LEARNING+FILTERING feature */
603bdea1361Sscw
604bdea1361Sscw /*
605bdea1361Sscw * Setup h/w rx/tx queues. There are four q's:
606bdea1361Sscw * rx inbound q of rx'd frames
607bdea1361Sscw * rx_free pool of ixpbuf's for receiving frames
608bdea1361Sscw * tx outbound q of frames to send
609bdea1361Sscw * tx_done q of tx frames that have been processed
610bdea1361Sscw *
611bdea1361Sscw * The NPE handles the actual tx/rx process and the q manager
612bdea1361Sscw * handles the queues. The driver just writes entries to the
613bdea1361Sscw * q manager mailbox's and gets callbacks when there are rx'd
614bdea1361Sscw * frames to process or tx'd frames to reap. These callbacks
615bdea1361Sscw * are controlled by the q configurations; e.g. we get a
616bdea1361Sscw * callback when tx_done has 2 or more frames to process and
617e9572cd9Sandvar * when the rx q has at least one frame. These settings can
618bdea1361Sscw * changed at the time the q is configured.
619bdea1361Sscw */
620bdea1361Sscw sc->rx_qid = npeconfig[unit].rx_qid;
621bdea1361Sscw ixpqmgr_qconfig(sc->rx_qid, NPE_RXBUF, 0, 1,
622bdea1361Sscw IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc);
623bdea1361Sscw sc->rx_freeqid = npeconfig[unit].rx_freeqid;
624bdea1361Sscw ixpqmgr_qconfig(sc->rx_freeqid, NPE_RXBUF, 0, NPE_RXBUF/2, 0, NULL, sc);
625bdea1361Sscw /* tell the NPE to direct all traffic to rx_qid */
626bdea1361Sscw #if 0
627bdea1361Sscw for (i = 0; i < 8; i++)
628bdea1361Sscw #else
629e20bd029Smatt printf("%s: remember to fix rx q setup\n", device_xname(sc->sc_dev));
630bdea1361Sscw for (i = 0; i < 4; i++)
631bdea1361Sscw #endif
632bdea1361Sscw npe_setrxqosentry(sc, i, 0, sc->rx_qid);
633bdea1361Sscw
634bdea1361Sscw sc->tx_qid = npeconfig[unit].tx_qid;
635bdea1361Sscw sc->tx_doneqid = npeconfig[unit].tx_doneqid;
636bdea1361Sscw ixpqmgr_qconfig(sc->tx_qid, NPE_TXBUF, 0, NPE_TXBUF, 0, NULL, sc);
637bdea1361Sscw if (tx_doneqid == -1) {
638bdea1361Sscw ixpqmgr_qconfig(sc->tx_doneqid, NPE_TXBUF, 0, 2,
639bdea1361Sscw IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc);
640bdea1361Sscw tx_doneqid = sc->tx_doneqid;
641bdea1361Sscw }
642bdea1361Sscw
643bdea1361Sscw KASSERT(npes[npeconfig[unit].npeid] == NULL);
644bdea1361Sscw npes[npeconfig[unit].npeid] = sc;
645bdea1361Sscw
646bdea1361Sscw return 0;
647bdea1361Sscw }
648bdea1361Sscw
649bdea1361Sscw #if 0
650bdea1361Sscw static void
651bdea1361Sscw npe_deactivate(struct npe_softc *sc);
652bdea1361Sscw {
653bdea1361Sscw int unit = sc->sc_unit;
654bdea1361Sscw
655bdea1361Sscw npes[npeconfig[unit].npeid] = NULL;
656bdea1361Sscw
657bdea1361Sscw /* XXX disable q's */
658bdea1361Sscw if (sc->sc_npe != NULL)
659bdea1361Sscw ixpnpe_stop(sc->sc_npe);
660bdea1361Sscw if (sc->sc_stats != NULL) {
661bdea1361Sscw bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map);
662bdea1361Sscw bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats,
663bdea1361Sscw sc->sc_stats_map);
664bdea1361Sscw bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map);
665bdea1361Sscw }
666bdea1361Sscw if (sc->sc_stats_tag != NULL)
667bdea1361Sscw bus_dma_tag_destroy(sc->sc_stats_tag);
668bdea1361Sscw npe_dma_destroy(sc, &sc->txdma);
669bdea1361Sscw npe_dma_destroy(sc, &sc->rxdma);
670bdea1361Sscw bus_generic_detach(sc->sc_dev);
671a467cf22Sthorpej XXX ifmedia_fini somewhere
672bdea1361Sscw if (sc->sc_mii)
673bdea1361Sscw device_delete_child(sc->sc_dev, sc->sc_mii);
674bdea1361Sscw #if 0
675bdea1361Sscw /* XXX sc_ioh and sc_miih */
676bdea1361Sscw if (sc->mem_res)
677bdea1361Sscw bus_release_resource(dev, SYS_RES_IOPORT,
678bdea1361Sscw rman_get_rid(sc->mem_res), sc->mem_res);
679bdea1361Sscw sc->mem_res = 0;
680bdea1361Sscw #endif
681bdea1361Sscw }
682bdea1361Sscw #endif
683bdea1361Sscw
684bdea1361Sscw static void
npe_addstats(struct npe_softc * sc)685bdea1361Sscw npe_addstats(struct npe_softc *sc)
686bdea1361Sscw {
687bdea1361Sscw struct ifnet *ifp = &sc->sc_ethercom.ec_if;
688bdea1361Sscw struct npestats *ns = sc->sc_stats;
689bdea1361Sscw
6900b131f18Sthorpej net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
6910b131f18Sthorpej if_statadd_ref(nsr, if_oerrors,
692bdea1361Sscw be32toh(ns->dot3StatsInternalMacTransmitErrors)
693bdea1361Sscw + be32toh(ns->dot3StatsCarrierSenseErrors)
694bdea1361Sscw + be32toh(ns->TxVLANIdFilterDiscards)
6950b131f18Sthorpej );
6960b131f18Sthorpej if_statadd_ref(nsr, if_ierrors,
6970b131f18Sthorpej be32toh(ns->dot3StatsFCSErrors)
698bdea1361Sscw + be32toh(ns->dot3StatsInternalMacReceiveErrors)
699bdea1361Sscw + be32toh(ns->RxOverrunDiscards)
700bdea1361Sscw + be32toh(ns->RxUnderflowEntryDiscards)
7010b131f18Sthorpej );
7020b131f18Sthorpej if_statadd_ref(nsr, if_collisions,
703bdea1361Sscw be32toh(ns->dot3StatsSingleCollisionFrames)
704bdea1361Sscw + be32toh(ns->dot3StatsMultipleCollisionFrames)
7050b131f18Sthorpej );
7060b131f18Sthorpej IF_STAT_PUTREF(ifp);
707bdea1361Sscw }
708bdea1361Sscw
709bdea1361Sscw static void
npe_tick(void * xsc)710bdea1361Sscw npe_tick(void *xsc)
711bdea1361Sscw {
712bdea1361Sscw #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL)
713bdea1361Sscw struct npe_softc *sc = xsc;
714bdea1361Sscw uint32_t msg[2];
715bdea1361Sscw
716bdea1361Sscw /*
717bdea1361Sscw * NB: to avoid sleeping with the softc lock held we
718bdea1361Sscw * split the NPE msg processing into two parts. The
719bdea1361Sscw * request for statistics is sent w/o waiting for a
720bdea1361Sscw * reply and then on the next tick we retrieve the
721bdea1361Sscw * results. This works because npe_tick is the only
722bdea1361Sscw * code that talks via the mailbox's (except at setup).
723bdea1361Sscw * This likely can be handled better.
724bdea1361Sscw */
725bdea1361Sscw if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) {
726bdea1361Sscw bus_dmamap_sync(sc->sc_dt, sc->sc_stats_map, 0,
727bdea1361Sscw sizeof(struct npestats), BUS_DMASYNC_POSTREAD);
728bdea1361Sscw npe_addstats(sc);
729bdea1361Sscw }
730bdea1361Sscw npe_updatestats(sc);
731bdea1361Sscw mii_tick(&sc->sc_mii);
732bdea1361Sscw
73312f4368bSmsaitoh /* Schedule next poll */
734bdea1361Sscw callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc);
735bdea1361Sscw #undef ACK
736bdea1361Sscw }
737bdea1361Sscw
738bdea1361Sscw static void
npe_setmac(struct npe_softc * sc,const u_char * eaddr)7396bc0c582Smatt npe_setmac(struct npe_softc *sc, const u_char *eaddr)
740bdea1361Sscw {
7413589a8fdSmsaitoh
742bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]);
743bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]);
744bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]);
745bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]);
746bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]);
747bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]);
748bdea1361Sscw }
749bdea1361Sscw
750bdea1361Sscw static void
npe_getmac(struct npe_softc * sc)7513589a8fdSmsaitoh npe_getmac(struct npe_softc *sc)
752bdea1361Sscw {
7533589a8fdSmsaitoh uint8_t *eaddr = sc->sc_enaddr;
7543589a8fdSmsaitoh
7553589a8fdSmsaitoh if (npe_getmac_md != NULL) {
756e20bd029Smatt (*npe_getmac_md)(device_unit(sc->sc_dev), eaddr);
7573589a8fdSmsaitoh } else {
7583589a8fdSmsaitoh /*
7593589a8fdSmsaitoh * Some system's unicast address appears to be loaded from
7603589a8fdSmsaitoh * EEPROM on reset
7613589a8fdSmsaitoh */
762bdea1361Sscw eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff;
763bdea1361Sscw eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff;
764bdea1361Sscw eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff;
765bdea1361Sscw eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff;
766bdea1361Sscw eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff;
767bdea1361Sscw eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff;
768bdea1361Sscw }
7693589a8fdSmsaitoh }
770bdea1361Sscw
771bdea1361Sscw struct txdone {
772bdea1361Sscw struct npebuf *head;
773bdea1361Sscw struct npebuf **tail;
774bdea1361Sscw int count;
775bdea1361Sscw };
776bdea1361Sscw
777bdea1361Sscw static __inline void
npe_txdone_finish(struct npe_softc * sc,const struct txdone * td)778bdea1361Sscw npe_txdone_finish(struct npe_softc *sc, const struct txdone *td)
779bdea1361Sscw {
780bdea1361Sscw struct ifnet *ifp = &sc->sc_ethercom.ec_if;
781bdea1361Sscw
782bdea1361Sscw *td->tail = sc->tx_free;
783bdea1361Sscw sc->tx_free = td->head;
784bdea1361Sscw /*
785bdea1361Sscw * We're no longer busy, so clear the busy flag and call the
786bdea1361Sscw * start routine to xmit more packets.
787bdea1361Sscw */
7880b131f18Sthorpej if_statadd(ifp, if_opackets, td->count);
789bdea1361Sscw ifp->if_timer = 0;
790e3a04365Snonaka if_schedule_deferred_start(ifp);
791bdea1361Sscw }
792bdea1361Sscw
793bdea1361Sscw /*
794bdea1361Sscw * Q manager callback on tx done queue. Reap mbufs
795bdea1361Sscw * and return tx buffers to the free list. Finally
796bdea1361Sscw * restart output. Note the microcode has only one
797bdea1361Sscw * txdone q wired into it so we must use the NPE ID
798bdea1361Sscw * returned with each npehwbuf to decide where to
799bdea1361Sscw * send buffers.
800bdea1361Sscw */
801bdea1361Sscw static void
npe_txdone(int qid,void * arg)802bdea1361Sscw npe_txdone(int qid, void *arg)
803bdea1361Sscw {
804bdea1361Sscw #define P2V(a, dma) \
805bdea1361Sscw &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)]
806bdea1361Sscw struct npe_softc *sc;
807bdea1361Sscw struct npebuf *npe;
808bdea1361Sscw struct txdone *td, q[NPE_MAX];
809bdea1361Sscw uint32_t entry;
810bdea1361Sscw
811bdea1361Sscw /* XXX no NPE-A support */
812bdea1361Sscw q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0;
813bdea1361Sscw q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0;
814bdea1361Sscw /* XXX max # at a time? */
815bdea1361Sscw while (ixpqmgr_qread(qid, &entry) == 0) {
816bdea1361Sscw sc = npes[NPE_QM_Q_NPE(entry)];
817bdea1361Sscw DPRINTF(sc, "%s: entry 0x%x NPE %u port %u\n",
818bdea1361Sscw __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry));
819507aaf9eSmsaitoh rnd_add_uint32(&sc->rnd_source, entry);
820bdea1361Sscw
821bdea1361Sscw npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma);
822bdea1361Sscw m_freem(npe->ix_m);
823bdea1361Sscw npe->ix_m = NULL;
824bdea1361Sscw
825bdea1361Sscw td = &q[NPE_QM_Q_NPE(entry)];
826bdea1361Sscw *td->tail = npe;
827bdea1361Sscw td->tail = &npe->ix_next;
828bdea1361Sscw td->count++;
829bdea1361Sscw }
830bdea1361Sscw
831bdea1361Sscw if (q[NPE_B].count)
832bdea1361Sscw npe_txdone_finish(npes[NPE_B], &q[NPE_B]);
833bdea1361Sscw if (q[NPE_C].count)
834bdea1361Sscw npe_txdone_finish(npes[NPE_C], &q[NPE_C]);
835bdea1361Sscw #undef P2V
836bdea1361Sscw }
837bdea1361Sscw
838bdea1361Sscw static __inline struct mbuf *
npe_getcl(void)839bdea1361Sscw npe_getcl(void)
840bdea1361Sscw {
841bdea1361Sscw struct mbuf *m;
842bdea1361Sscw
843bdea1361Sscw MGETHDR(m, M_DONTWAIT, MT_DATA);
844bdea1361Sscw if (m != NULL) {
845bdea1361Sscw MCLGET(m, M_DONTWAIT);
846bdea1361Sscw if ((m->m_flags & M_EXT) == 0) {
847bdea1361Sscw m_freem(m);
848bdea1361Sscw m = NULL;
849bdea1361Sscw }
850bdea1361Sscw }
85112f4368bSmsaitoh return m;
852bdea1361Sscw }
853bdea1361Sscw
854bdea1361Sscw static int
npe_rxbuf_init(struct npe_softc * sc,struct npebuf * npe,struct mbuf * m)855bdea1361Sscw npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m)
856bdea1361Sscw {
857bdea1361Sscw struct npehwbuf *hw;
858bdea1361Sscw int error;
859bdea1361Sscw
860bdea1361Sscw if (m == NULL) {
861bdea1361Sscw m = npe_getcl();
862bdea1361Sscw if (m == NULL)
863bdea1361Sscw return ENOBUFS;
864bdea1361Sscw }
8653589a8fdSmsaitoh KASSERT(m->m_ext.ext_size >= (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN));
8663589a8fdSmsaitoh m->m_pkthdr.len = m->m_len = NPE_FRAME_SIZE_DEFAULT;
867bdea1361Sscw /* backload payload and align ip hdr */
8683589a8fdSmsaitoh m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size
8693589a8fdSmsaitoh - (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN));
870bdea1361Sscw error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m,
871bdea1361Sscw BUS_DMA_READ | BUS_DMA_NOWAIT);
872bdea1361Sscw if (error != 0) {
873bdea1361Sscw m_freem(m);
874bdea1361Sscw return error;
875bdea1361Sscw }
876bdea1361Sscw hw = npe->ix_hw;
877bdea1361Sscw hw->ix_ne[0].data = htobe32(npe->ix_map->dm_segs[0].ds_addr);
878bdea1361Sscw /* NB: NPE requires length be a multiple of 64 */
879bdea1361Sscw /* NB: buffer length is shifted in word */
880bdea1361Sscw hw->ix_ne[0].len = htobe32(npe->ix_map->dm_segs[0].ds_len << 16);
881bdea1361Sscw hw->ix_ne[0].next = 0;
882bdea1361Sscw npe->ix_m = m;
883bdea1361Sscw /* Flush the memory in the mbuf */
884bdea1361Sscw bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, npe->ix_map->dm_mapsize,
885bdea1361Sscw BUS_DMASYNC_PREREAD);
886bdea1361Sscw return 0;
887bdea1361Sscw }
888bdea1361Sscw
889bdea1361Sscw /*
890bdea1361Sscw * RX q processing for a specific NPE. Claim entries
891bdea1361Sscw * from the hardware queue and pass the frames up the
892bdea1361Sscw * stack. Pass the rx buffers to the free list.
893bdea1361Sscw */
894bdea1361Sscw static void
npe_rxdone(int qid,void * arg)895bdea1361Sscw npe_rxdone(int qid, void *arg)
896bdea1361Sscw {
897bdea1361Sscw #define P2V(a, dma) \
898bdea1361Sscw &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)]
899bdea1361Sscw struct npe_softc *sc = arg;
900bdea1361Sscw struct npedma *dma = &sc->rxdma;
901bdea1361Sscw uint32_t entry;
902bdea1361Sscw
903bdea1361Sscw while (ixpqmgr_qread(qid, &entry) == 0) {
904bdea1361Sscw struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma);
905bdea1361Sscw struct mbuf *m;
906bdea1361Sscw
907bdea1361Sscw DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n",
908bdea1361Sscw __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len);
909507aaf9eSmsaitoh rnd_add_uint32(&sc->rnd_source, entry);
910bdea1361Sscw /*
911bdea1361Sscw * Allocate a new mbuf to replenish the rx buffer.
912bdea1361Sscw * If doing so fails we drop the rx'd frame so we
913bdea1361Sscw * can reuse the previous mbuf. When we're able to
914bdea1361Sscw * allocate a new mbuf dispatch the mbuf w/ rx'd
915bdea1361Sscw * data up the stack and replace it with the newly
916bdea1361Sscw * allocated one.
917bdea1361Sscw */
918bdea1361Sscw m = npe_getcl();
919bdea1361Sscw if (m != NULL) {
920bdea1361Sscw struct mbuf *mrx = npe->ix_m;
921bdea1361Sscw struct npehwbuf *hw = npe->ix_hw;
922bdea1361Sscw struct ifnet *ifp = &sc->sc_ethercom.ec_if;
923bdea1361Sscw
924bdea1361Sscw /* Flush mbuf memory for rx'd data */
925bdea1361Sscw bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0,
926bdea1361Sscw npe->ix_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
927bdea1361Sscw
928bdea1361Sscw /* XXX flush hw buffer; works now 'cuz coherent */
929bdea1361Sscw /* set m_len etc. per rx frame size */
930bdea1361Sscw mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff;
931bdea1361Sscw mrx->m_pkthdr.len = mrx->m_len;
932758ba73eSozaki-r m_set_rcvif(mrx, ifp);
9333589a8fdSmsaitoh /* Don't add M_HASFCS. See below */
9343589a8fdSmsaitoh
9353589a8fdSmsaitoh #if 1
9363589a8fdSmsaitoh if (mrx->m_pkthdr.len < sizeof(struct ether_header)) {
9373589a8fdSmsaitoh log(LOG_INFO, "%s: too short frame (len=%d)\n",
93812f4368bSmsaitoh device_xname(sc->sc_dev),
93912f4368bSmsaitoh mrx->m_pkthdr.len);
9403589a8fdSmsaitoh /* Back out "newly allocated" mbuf. */
9413589a8fdSmsaitoh m_freem(m);
9420b131f18Sthorpej if_statinc(ifp, if_ierrors);
9433589a8fdSmsaitoh goto fail;
9443589a8fdSmsaitoh }
9453589a8fdSmsaitoh if ((ifp->if_flags & IFF_PROMISC) == 0) {
9463589a8fdSmsaitoh struct ether_header *eh;
9473589a8fdSmsaitoh
9483589a8fdSmsaitoh /*
9493589a8fdSmsaitoh * Workaround for "Non-Intel XScale Technology
9503589a8fdSmsaitoh * Eratta" No. 29. AA:BB:CC:DD:EE:xF's packet
9513589a8fdSmsaitoh * matches the filter (both unicast and
9523589a8fdSmsaitoh * multicast).
9533589a8fdSmsaitoh */
9543589a8fdSmsaitoh eh = mtod(mrx, struct ether_header *);
9553589a8fdSmsaitoh if (ETHER_IS_MULTICAST(eh->ether_dhost) == 0) {
95612f4368bSmsaitoh /* Unicast */
9573589a8fdSmsaitoh
9583589a8fdSmsaitoh if (sc->sc_enaddr[5] != eh->ether_dhost[5]) {
95912f4368bSmsaitoh /* Discard it */
9603589a8fdSmsaitoh #if 0
9613589a8fdSmsaitoh printf("discard it\n");
9623589a8fdSmsaitoh #endif
9633589a8fdSmsaitoh /*
9643589a8fdSmsaitoh * Back out "newly allocated"
9653589a8fdSmsaitoh * mbuf.
9663589a8fdSmsaitoh */
9673589a8fdSmsaitoh m_freem(m);
9683589a8fdSmsaitoh goto fail;
9693589a8fdSmsaitoh }
9703589a8fdSmsaitoh } else if (memcmp(eh->ether_dhost,
9713589a8fdSmsaitoh etherbroadcastaddr, 6) == 0) {
9723589a8fdSmsaitoh /* Always accept broadcast packet*/
9733589a8fdSmsaitoh } else {
9743589a8fdSmsaitoh struct ethercom *ec = &sc->sc_ethercom;
9753589a8fdSmsaitoh struct ether_multi *enm;
9763589a8fdSmsaitoh struct ether_multistep step;
9773589a8fdSmsaitoh int match = 0;
9783589a8fdSmsaitoh
97912f4368bSmsaitoh /* Multicast */
9803589a8fdSmsaitoh
981f515fb39Smsaitoh ETHER_LOCK(ec);
9823589a8fdSmsaitoh ETHER_FIRST_MULTI(step, ec, enm);
9833589a8fdSmsaitoh while (enm != NULL) {
9843589a8fdSmsaitoh uint64_t lowint, highint, dest;
9853589a8fdSmsaitoh
9863589a8fdSmsaitoh lowint = MAC2UINT64(enm->enm_addrlo);
9873589a8fdSmsaitoh highint = MAC2UINT64(enm->enm_addrhi);
9883589a8fdSmsaitoh dest = MAC2UINT64(eh->ether_dhost);
9893589a8fdSmsaitoh #if 0
9903589a8fdSmsaitoh printf("%llx\n", lowint);
9913589a8fdSmsaitoh printf("%llx\n", dest);
9923589a8fdSmsaitoh printf("%llx\n", highint);
9933589a8fdSmsaitoh #endif
9943589a8fdSmsaitoh if ((lowint <= dest) && (dest <= highint)) {
9953589a8fdSmsaitoh match = 1;
9963589a8fdSmsaitoh break;
9973589a8fdSmsaitoh }
9983589a8fdSmsaitoh ETHER_NEXT_MULTI(step, enm);
9993589a8fdSmsaitoh }
1000f515fb39Smsaitoh ETHER_UNLOCK(ec);
1001f515fb39Smsaitoh
10023589a8fdSmsaitoh if (match == 0) {
100312f4368bSmsaitoh /* Discard it */
10043589a8fdSmsaitoh #if 0
10053589a8fdSmsaitoh printf("discard it(M)\n");
10063589a8fdSmsaitoh #endif
10073589a8fdSmsaitoh /*
10083589a8fdSmsaitoh * Back out "newly allocated"
10093589a8fdSmsaitoh * mbuf.
10103589a8fdSmsaitoh */
10113589a8fdSmsaitoh m_freem(m);
10123589a8fdSmsaitoh goto fail;
10133589a8fdSmsaitoh }
10143589a8fdSmsaitoh }
10153589a8fdSmsaitoh }
10163589a8fdSmsaitoh if (mrx->m_pkthdr.len > NPE_FRAME_SIZE_DEFAULT) {
10173589a8fdSmsaitoh log(LOG_INFO, "%s: oversized frame (len=%d)\n",
1018e20bd029Smatt device_xname(sc->sc_dev), mrx->m_pkthdr.len);
10193589a8fdSmsaitoh /* Back out "newly allocated" mbuf. */
10203589a8fdSmsaitoh m_freem(m);
10210b131f18Sthorpej if_statinc(ifp, if_ierrors);
10223589a8fdSmsaitoh goto fail;
10233589a8fdSmsaitoh }
10243589a8fdSmsaitoh #endif
10253589a8fdSmsaitoh
10263589a8fdSmsaitoh /*
10273589a8fdSmsaitoh * Trim FCS!
10283589a8fdSmsaitoh * NPE always adds the FCS by this driver's setting,
10293589a8fdSmsaitoh * so we always trim it here and not add M_HASFCS.
10303589a8fdSmsaitoh */
10313589a8fdSmsaitoh m_adj(mrx, -ETHER_CRC_LEN);
1032bdea1361Sscw
10338586a845Smsaitoh /*
10348586a845Smsaitoh * Tap off here if there is a bpf listener.
10358586a845Smsaitoh */
10365a3149d8Sozaki-r
1037b8256fd8Sozaki-r if_percpuq_enqueue(ifp->if_percpuq, mrx);
1038bdea1361Sscw } else {
10393589a8fdSmsaitoh fail:
1040bdea1361Sscw /* discard frame and re-use mbuf */
1041bdea1361Sscw m = npe->ix_m;
1042bdea1361Sscw }
1043bdea1361Sscw if (npe_rxbuf_init(sc, npe, m) == 0) {
1044bdea1361Sscw /* return npe buf to rx free list */
1045bdea1361Sscw ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr);
1046bdea1361Sscw } else {
1047bdea1361Sscw /* XXX should not happen */
1048bdea1361Sscw }
1049bdea1361Sscw }
1050bdea1361Sscw #undef P2V
1051bdea1361Sscw }
1052bdea1361Sscw
1053bdea1361Sscw static void
npe_startxmit(struct npe_softc * sc)1054bdea1361Sscw npe_startxmit(struct npe_softc *sc)
1055bdea1361Sscw {
1056bdea1361Sscw struct npedma *dma = &sc->txdma;
1057bdea1361Sscw int i;
1058bdea1361Sscw
1059bdea1361Sscw sc->tx_free = NULL;
1060bdea1361Sscw for (i = 0; i < dma->nbuf; i++) {
1061bdea1361Sscw struct npebuf *npe = &dma->buf[i];
1062bdea1361Sscw if (npe->ix_m != NULL) {
1063bdea1361Sscw /* NB: should not happen */
1064bdea1361Sscw printf("%s: %s: free mbuf at entry %u\n",
1065e20bd029Smatt device_xname(sc->sc_dev), __func__, i);
1066bdea1361Sscw m_freem(npe->ix_m);
1067bdea1361Sscw }
1068bdea1361Sscw npe->ix_m = NULL;
1069bdea1361Sscw npe->ix_next = sc->tx_free;
1070bdea1361Sscw sc->tx_free = npe;
1071bdea1361Sscw }
1072bdea1361Sscw }
1073bdea1361Sscw
1074bdea1361Sscw static void
npe_startrecv(struct npe_softc * sc)1075bdea1361Sscw npe_startrecv(struct npe_softc *sc)
1076bdea1361Sscw {
1077bdea1361Sscw struct npedma *dma = &sc->rxdma;
1078bdea1361Sscw struct npebuf *npe;
1079bdea1361Sscw int i;
1080bdea1361Sscw
1081bdea1361Sscw for (i = 0; i < dma->nbuf; i++) {
1082bdea1361Sscw npe = &dma->buf[i];
1083bdea1361Sscw npe_rxbuf_init(sc, npe, npe->ix_m);
108412f4368bSmsaitoh /* Set npe buf on rx free list */
1085bdea1361Sscw ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr);
1086bdea1361Sscw }
1087bdea1361Sscw }
1088bdea1361Sscw
1089bdea1361Sscw static void
npeinit_macreg(struct npe_softc * sc)1090816cf5b8Smsaitoh npeinit_macreg(struct npe_softc *sc)
1091bdea1361Sscw {
1092bdea1361Sscw
1093bdea1361Sscw /*
1094bdea1361Sscw * Reset MAC core.
1095bdea1361Sscw */
1096bdea1361Sscw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
1097bdea1361Sscw DELAY(NPE_MAC_RESET_DELAY);
109812f4368bSmsaitoh /* Configure MAC to generate MDC clock */
1099bdea1361Sscw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
1100bdea1361Sscw
11011ef77801Smsaitoh /* Disable transmitter and receiver in the MAC */
1102bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL1,
1103bdea1361Sscw RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN);
1104bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL1,
1105bdea1361Sscw RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN);
1106bdea1361Sscw
1107bdea1361Sscw /*
1108bdea1361Sscw * Set the MAC core registers.
1109bdea1361Sscw */
1110bdea1361Sscw WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */
1111bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */
1112bdea1361Sscw WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */
111312f4368bSmsaitoh /* Thresholds determined by NPE firmware FS */
1114bdea1361Sscw WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12);
1115bdea1361Sscw WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30);
1116a69b43feSmsaitoh WR4(sc, NPE_MAC_BUF_SIZE_TX, NPE_MAC_BUF_SIZE_TX_DEFAULT);
1117a69b43feSmsaitoh /* tx fifo threshold (bytes) */
1118bdea1361Sscw WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */
1119bdea1361Sscw WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/
1120bdea1361Sscw WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */
1121bdea1361Sscw WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */
1122a69b43feSmsaitoh WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT);
1123a69b43feSmsaitoh /* assumes MII mode */
1124bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL1,
1125bdea1361Sscw NPE_TX_CNTRL1_RETRY /* retry failed xmits */
1126bdea1361Sscw | NPE_TX_CNTRL1_FCS_EN /* append FCS */
1127bdea1361Sscw | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */
1128bdea1361Sscw | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */
1129bdea1361Sscw /* XXX pad strip? */
1130bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL1,
1131bdea1361Sscw NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */
1132bdea1361Sscw | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */
1133bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL2, 0);
1134816cf5b8Smsaitoh }
1135bdea1361Sscw
1136227ae4c9Smsaitoh static void
npeinit_resetcb(void * xsc)1137227ae4c9Smsaitoh npeinit_resetcb(void *xsc)
1138227ae4c9Smsaitoh {
1139227ae4c9Smsaitoh struct npe_softc *sc = xsc;
1140227ae4c9Smsaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1141227ae4c9Smsaitoh uint32_t msg[2];
1142227ae4c9Smsaitoh
11430b131f18Sthorpej if_statinc(ifp, if_oerrors);
1144227ae4c9Smsaitoh npeinit_locked(sc);
1145227ae4c9Smsaitoh
1146227ae4c9Smsaitoh msg[0] = NPE_NOTIFYMACRECOVERYDONE << NPE_MAC_MSGID_SHL
1147227ae4c9Smsaitoh | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL);
1148227ae4c9Smsaitoh msg[1] = 0;
1149227ae4c9Smsaitoh ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1150227ae4c9Smsaitoh }
1151227ae4c9Smsaitoh
1152816cf5b8Smsaitoh /*
1153816cf5b8Smsaitoh * Reset and initialize the chip
1154816cf5b8Smsaitoh */
1155816cf5b8Smsaitoh static void
npeinit_locked(void * xsc)1156816cf5b8Smsaitoh npeinit_locked(void *xsc)
1157816cf5b8Smsaitoh {
1158816cf5b8Smsaitoh struct npe_softc *sc = xsc;
1159816cf5b8Smsaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1160816cf5b8Smsaitoh
1161816cf5b8Smsaitoh /* Cancel any pending I/O. */
1162816cf5b8Smsaitoh npestop(ifp, 0);
1163816cf5b8Smsaitoh
1164816cf5b8Smsaitoh /* Reset the chip to a known state. */
1165816cf5b8Smsaitoh npeinit_macreg(sc);
11666bc0c582Smatt npe_setmac(sc, CLLADDR(ifp->if_sadl));
1167273cfb27Smsaitoh ether_mediachange(ifp);
1168bdea1361Sscw npe_setmcast(sc);
1169bdea1361Sscw
1170bdea1361Sscw npe_startxmit(sc);
1171bdea1361Sscw npe_startrecv(sc);
1172bdea1361Sscw
1173bdea1361Sscw ifp->if_flags |= IFF_RUNNING;
1174bdea1361Sscw ifp->if_timer = 0; /* just in case */
1175bdea1361Sscw
11761ef77801Smsaitoh /* Enable transmitter and receiver in the MAC */
1177bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL1,
1178bdea1361Sscw RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN);
1179bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL1,
1180bdea1361Sscw RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN);
1181bdea1361Sscw
1182bdea1361Sscw callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc);
1183bdea1361Sscw }
1184bdea1361Sscw
1185bdea1361Sscw static int
npeinit(struct ifnet * ifp)1186bdea1361Sscw npeinit(struct ifnet *ifp)
1187bdea1361Sscw {
1188bdea1361Sscw struct npe_softc *sc = ifp->if_softc;
1189bdea1361Sscw int s;
1190bdea1361Sscw
1191bdea1361Sscw s = splnet();
1192bdea1361Sscw npeinit_locked(sc);
1193bdea1361Sscw splx(s);
1194bdea1361Sscw
119512f4368bSmsaitoh return 0;
1196bdea1361Sscw }
1197bdea1361Sscw
1198bdea1361Sscw /*
1199bdea1361Sscw * Defragment an mbuf chain, returning at most maxfrags separate
1200bdea1361Sscw * mbufs+clusters. If this is not possible NULL is returned and
12017d1220acSsnj * the original mbuf chain is left in its present (potentially
1202bdea1361Sscw * modified) state. We use two techniques: collapsing consecutive
1203bdea1361Sscw * mbufs and replacing consecutive mbufs by a cluster.
1204bdea1361Sscw */
1205bdea1361Sscw static __inline struct mbuf *
npe_defrag(struct mbuf * m0)1206bdea1361Sscw npe_defrag(struct mbuf *m0)
1207bdea1361Sscw {
1208bdea1361Sscw struct mbuf *m;
1209bdea1361Sscw
1210bdea1361Sscw MGETHDR(m, M_DONTWAIT, MT_DATA);
1211bdea1361Sscw if (m == NULL)
121212f4368bSmsaitoh return NULL;
12134f37cd5cSmaxv m_copy_pkthdr(m, m0);
1214bdea1361Sscw
1215bdea1361Sscw if ((m->m_len = m0->m_pkthdr.len) > MHLEN) {
1216bdea1361Sscw MCLGET(m, M_DONTWAIT);
1217bdea1361Sscw if ((m->m_flags & M_EXT) == 0) {
1218bdea1361Sscw m_freem(m);
121912f4368bSmsaitoh return NULL;
1220bdea1361Sscw }
1221bdea1361Sscw }
1222bdea1361Sscw
122353524e44Schristos m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
1224bdea1361Sscw m_freem(m0);
1225bdea1361Sscw
122612f4368bSmsaitoh return m;
1227bdea1361Sscw }
1228bdea1361Sscw
1229bdea1361Sscw /*
1230bdea1361Sscw * Dequeue packets and place on the h/w transmit queue.
1231bdea1361Sscw */
1232bdea1361Sscw static void
npestart(struct ifnet * ifp)1233bdea1361Sscw npestart(struct ifnet *ifp)
1234bdea1361Sscw {
1235bdea1361Sscw struct npe_softc *sc = ifp->if_softc;
1236bdea1361Sscw struct npebuf *npe;
1237bdea1361Sscw struct npehwbuf *hw;
1238bdea1361Sscw struct mbuf *m, *n;
1239bdea1361Sscw bus_dma_segment_t *segs;
1240bdea1361Sscw int nseg, len, error, i;
1241bdea1361Sscw uint32_t next;
1242bdea1361Sscw
1243734badd9Sthorpej if ((ifp->if_flags & IFF_RUNNING) == 0)
1244bdea1361Sscw return;
1245bdea1361Sscw
1246bdea1361Sscw while (sc->tx_free != NULL) {
1247bdea1361Sscw IFQ_DEQUEUE(&ifp->if_snd, m);
1248816cf5b8Smsaitoh if (m == NULL)
1249816cf5b8Smsaitoh break;
1250bdea1361Sscw npe = sc->tx_free;
1251bdea1361Sscw error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m,
1252bdea1361Sscw BUS_DMA_WRITE | BUS_DMA_NOWAIT);
1253bdea1361Sscw if (error == EFBIG) {
1254bdea1361Sscw n = npe_defrag(m);
1255bdea1361Sscw if (n == NULL) {
1256bdea1361Sscw printf("%s: %s: too many fragments\n",
1257e20bd029Smatt device_xname(sc->sc_dev), __func__);
1258bdea1361Sscw m_freem(m);
1259bdea1361Sscw return; /* XXX? */
1260bdea1361Sscw }
1261bdea1361Sscw m = n;
1262bdea1361Sscw error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map,
1263bdea1361Sscw m, BUS_DMA_WRITE | BUS_DMA_NOWAIT);
1264bdea1361Sscw }
1265bdea1361Sscw if (error != 0) {
1266bdea1361Sscw printf("%s: %s: error %u\n",
1267e20bd029Smatt device_xname(sc->sc_dev), __func__, error);
1268bdea1361Sscw m_freem(m);
1269bdea1361Sscw return; /* XXX? */
1270bdea1361Sscw }
1271bdea1361Sscw sc->tx_free = npe->ix_next;
1272bdea1361Sscw
1273bdea1361Sscw /*
1274bdea1361Sscw * Tap off here if there is a bpf listener.
1275bdea1361Sscw */
12768517c9d1Smsaitoh bpf_mtap(ifp, m, BPF_D_OUT);
1277bdea1361Sscw
1278bdea1361Sscw bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0,
1279bdea1361Sscw npe->ix_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
1280bdea1361Sscw
1281bdea1361Sscw npe->ix_m = m;
1282bdea1361Sscw hw = npe->ix_hw;
1283bdea1361Sscw len = m->m_pkthdr.len;
1284bdea1361Sscw nseg = npe->ix_map->dm_nsegs;
1285bdea1361Sscw segs = npe->ix_map->dm_segs;
1286bdea1361Sscw next = npe->ix_neaddr + sizeof(hw->ix_ne[0]);
1287bdea1361Sscw for (i = 0; i < nseg; i++) {
1288bdea1361Sscw hw->ix_ne[i].data = htobe32(segs[i].ds_addr);
1289bdea1361Sscw hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len);
1290bdea1361Sscw hw->ix_ne[i].next = htobe32(next);
1291bdea1361Sscw
1292bdea1361Sscw len = 0; /* zero for segments > 1 */
1293bdea1361Sscw next += sizeof(hw->ix_ne[0]);
1294bdea1361Sscw }
1295bdea1361Sscw hw->ix_ne[i-1].next = 0; /* zero last in chain */
1296bdea1361Sscw /* XXX flush descriptor instead of using uncached memory */
1297bdea1361Sscw
1298bdea1361Sscw DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n",
1299bdea1361Sscw __func__, sc->tx_qid, npe->ix_neaddr,
1300bdea1361Sscw hw->ix_ne[0].data, hw->ix_ne[0].len);
1301bdea1361Sscw /* stick it on the tx q */
1302bdea1361Sscw /* XXX add vlan priority */
1303bdea1361Sscw ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr);
1304bdea1361Sscw
1305bdea1361Sscw ifp->if_timer = 5;
1306bdea1361Sscw }
1307bdea1361Sscw }
1308bdea1361Sscw
1309bdea1361Sscw static void
npe_stopxmit(struct npe_softc * sc)1310bdea1361Sscw npe_stopxmit(struct npe_softc *sc)
1311bdea1361Sscw {
1312bdea1361Sscw struct npedma *dma = &sc->txdma;
1313bdea1361Sscw int i;
1314bdea1361Sscw
1315bdea1361Sscw /* XXX qmgr */
1316bdea1361Sscw for (i = 0; i < dma->nbuf; i++) {
1317bdea1361Sscw struct npebuf *npe = &dma->buf[i];
1318bdea1361Sscw
1319bdea1361Sscw if (npe->ix_m != NULL) {
1320bdea1361Sscw bus_dmamap_unload(sc->sc_dt, npe->ix_map);
1321bdea1361Sscw m_freem(npe->ix_m);
1322bdea1361Sscw npe->ix_m = NULL;
1323bdea1361Sscw }
1324bdea1361Sscw }
1325bdea1361Sscw }
1326bdea1361Sscw
1327bdea1361Sscw static void
npe_stoprecv(struct npe_softc * sc)1328bdea1361Sscw npe_stoprecv(struct npe_softc *sc)
1329bdea1361Sscw {
1330bdea1361Sscw struct npedma *dma = &sc->rxdma;
1331bdea1361Sscw int i;
1332bdea1361Sscw
1333bdea1361Sscw /* XXX qmgr */
1334bdea1361Sscw for (i = 0; i < dma->nbuf; i++) {
1335bdea1361Sscw struct npebuf *npe = &dma->buf[i];
1336bdea1361Sscw
1337bdea1361Sscw if (npe->ix_m != NULL) {
1338bdea1361Sscw bus_dmamap_unload(sc->sc_dt, npe->ix_map);
1339bdea1361Sscw m_freem(npe->ix_m);
1340bdea1361Sscw npe->ix_m = NULL;
1341bdea1361Sscw }
1342bdea1361Sscw }
1343bdea1361Sscw }
1344bdea1361Sscw
1345bdea1361Sscw /*
1346bdea1361Sscw * Turn off interrupts, and stop the nic.
1347bdea1361Sscw */
1348bdea1361Sscw void
npestop(struct ifnet * ifp,int disable)1349bdea1361Sscw npestop(struct ifnet *ifp, int disable)
1350bdea1361Sscw {
1351bdea1361Sscw struct npe_softc *sc = ifp->if_softc;
1352bdea1361Sscw
13531ef77801Smsaitoh /* Disable transmitter and receiver in the MAC */
1354bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL1,
1355bdea1361Sscw RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN);
1356bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL1,
1357bdea1361Sscw RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN);
1358bdea1361Sscw
1359bdea1361Sscw callout_stop(&sc->sc_tick_ch);
1360bdea1361Sscw
1361bdea1361Sscw npe_stopxmit(sc);
1362bdea1361Sscw npe_stoprecv(sc);
1363bdea1361Sscw /* XXX go into loopback & drain q's? */
1364bdea1361Sscw /* XXX but beware of disabling tx above */
1365bdea1361Sscw
1366bdea1361Sscw /*
1367bdea1361Sscw * The MAC core rx/tx disable may leave the MAC hardware in an
1368bdea1361Sscw * unpredictable state. A hw reset is executed before resetting
1369bdea1361Sscw * all the MAC parameters to a known value.
1370bdea1361Sscw */
1371bdea1361Sscw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
1372bdea1361Sscw DELAY(NPE_MAC_RESET_DELAY);
1373bdea1361Sscw WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT);
1374bdea1361Sscw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
1375816cf5b8Smsaitoh
1376816cf5b8Smsaitoh ifp->if_timer = 0;
1377734badd9Sthorpej ifp->if_flags &= ~IFF_RUNNING;
1378bdea1361Sscw }
1379bdea1361Sscw
1380bdea1361Sscw void
npewatchdog(struct ifnet * ifp)1381bdea1361Sscw npewatchdog(struct ifnet *ifp)
1382bdea1361Sscw {
1383bdea1361Sscw struct npe_softc *sc = ifp->if_softc;
1384bdea1361Sscw int s;
1385bdea1361Sscw
1386e20bd029Smatt aprint_error_dev(sc->sc_dev, "device timeout\n");
1387bdea1361Sscw s = splnet();
13880b131f18Sthorpej if_statinc(ifp, if_oerrors);
1389bdea1361Sscw npeinit_locked(sc);
1390bdea1361Sscw splx(s);
1391bdea1361Sscw }
1392bdea1361Sscw
1393bdea1361Sscw static int
npeioctl(struct ifnet * ifp,u_long cmd,void * data)139453524e44Schristos npeioctl(struct ifnet *ifp, u_long cmd, void *data)
1395bdea1361Sscw {
1396bdea1361Sscw struct npe_softc *sc = ifp->if_softc;
1397816cf5b8Smsaitoh struct ifreq *ifr = (struct ifreq *) data;
1398bdea1361Sscw int s, error = 0;
1399bdea1361Sscw
1400bdea1361Sscw s = splnet();
1401bdea1361Sscw
1402816cf5b8Smsaitoh switch (cmd) {
1403816cf5b8Smsaitoh case SIOCSIFMEDIA:
1404816cf5b8Smsaitoh #if 0 /* not yet */
1405816cf5b8Smsaitoh /* Flow control requires full-duplex mode. */
1406816cf5b8Smsaitoh if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
1407816cf5b8Smsaitoh (ifr->ifr_media & IFM_FDX) == 0)
1408816cf5b8Smsaitoh ifr->ifr_media &= ~IFM_ETH_FMASK;
1409816cf5b8Smsaitoh if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
1410816cf5b8Smsaitoh if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
1411816cf5b8Smsaitoh /* We can do both TXPAUSE and RXPAUSE. */
1412816cf5b8Smsaitoh ifr->ifr_media |=
1413816cf5b8Smsaitoh IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
1414816cf5b8Smsaitoh }
1415816cf5b8Smsaitoh sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
1416816cf5b8Smsaitoh }
1417816cf5b8Smsaitoh #endif
1418816cf5b8Smsaitoh error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
1419816cf5b8Smsaitoh break;
1420816cf5b8Smsaitoh case SIOCSIFFLAGS:
1421816cf5b8Smsaitoh if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_RUNNING) {
1422816cf5b8Smsaitoh /*
1423816cf5b8Smsaitoh * If interface is marked down and it is running,
1424816cf5b8Smsaitoh * then stop and disable it.
1425816cf5b8Smsaitoh */
1426918d3993Sriastradh if_stop(ifp, 1);
1427816cf5b8Smsaitoh } else if ((ifp->if_flags & (IFF_UP |IFF_RUNNING)) == IFF_UP) {
1428816cf5b8Smsaitoh /*
1429816cf5b8Smsaitoh * If interface is marked up and it is stopped, then
1430816cf5b8Smsaitoh * start it.
1431816cf5b8Smsaitoh */
1432b9691d4dSriastradh error = if_init(ifp);
1433816cf5b8Smsaitoh } else if ((ifp->if_flags & IFF_UP) != 0) {
1434397a83b3Smsaitoh u_short diff;
1435816cf5b8Smsaitoh
1436816cf5b8Smsaitoh /* Up (AND RUNNING). */
1437816cf5b8Smsaitoh
1438816cf5b8Smsaitoh diff = (ifp->if_flags ^ sc->sc_if_flags)
1439816cf5b8Smsaitoh & (IFF_PROMISC | IFF_ALLMULTI);
1440816cf5b8Smsaitoh if ((diff & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
1441816cf5b8Smsaitoh /*
14422d52435aSandvar * If the difference between last flag and
1443816cf5b8Smsaitoh * new flag only IFF_PROMISC or IFF_ALLMULTI,
1444816cf5b8Smsaitoh * set multicast filter only (don't reset to
1445816cf5b8Smsaitoh * prevent link down).
1446816cf5b8Smsaitoh */
1447816cf5b8Smsaitoh npe_setmcast(sc);
1448816cf5b8Smsaitoh } else {
1449816cf5b8Smsaitoh /*
1450816cf5b8Smsaitoh * Reset the interface to pick up changes in
1451816cf5b8Smsaitoh * any other flags that affect the hardware
1452816cf5b8Smsaitoh * state.
1453816cf5b8Smsaitoh */
1454b9691d4dSriastradh error = if_init(ifp);
1455816cf5b8Smsaitoh }
1456816cf5b8Smsaitoh }
1457816cf5b8Smsaitoh sc->sc_if_flags = ifp->if_flags;
1458816cf5b8Smsaitoh break;
1459816cf5b8Smsaitoh default:
1460bdea1361Sscw error = ether_ioctl(ifp, cmd, data);
1461bdea1361Sscw if (error == ENETRESET) {
1462816cf5b8Smsaitoh /*
1463816cf5b8Smsaitoh * Multicast list has changed; set the hardware filter
1464816cf5b8Smsaitoh * accordingly.
1465816cf5b8Smsaitoh */
1466816cf5b8Smsaitoh npe_setmcast(sc);
1467bdea1361Sscw error = 0;
1468bdea1361Sscw }
1469816cf5b8Smsaitoh }
1470bdea1361Sscw
1471bdea1361Sscw npestart(ifp);
1472bdea1361Sscw
1473bdea1361Sscw splx(s);
1474bdea1361Sscw return error;
1475bdea1361Sscw }
1476bdea1361Sscw
1477bdea1361Sscw /*
1478bdea1361Sscw * Setup a traffic class -> rx queue mapping.
1479bdea1361Sscw */
1480bdea1361Sscw static int
npe_setrxqosentry(struct npe_softc * sc,int classix,int trafclass,int qid)1481bdea1361Sscw npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid)
1482bdea1361Sscw {
1483bdea1361Sscw int npeid = npeconfig[sc->sc_unit].npeid;
1484bdea1361Sscw uint32_t msg[2];
1485bdea1361Sscw
1486273cfb27Smsaitoh msg[0] = (NPE_SETRXQOSENTRY << NPE_MAC_MSGID_SHL) | (npeid << 20)
1487273cfb27Smsaitoh | classix;
1488bdea1361Sscw msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4);
1489bdea1361Sscw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1490bdea1361Sscw }
1491bdea1361Sscw
1492bdea1361Sscw /*
1493bdea1361Sscw * Update and reset the statistics in the NPE.
1494bdea1361Sscw */
1495bdea1361Sscw static int
npe_updatestats(struct npe_softc * sc)1496bdea1361Sscw npe_updatestats(struct npe_softc *sc)
1497bdea1361Sscw {
1498bdea1361Sscw uint32_t msg[2];
1499bdea1361Sscw
1500bdea1361Sscw msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL;
1501bdea1361Sscw msg[1] = sc->sc_stats_phys; /* physical address of stat block */
1502bdea1361Sscw return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */
1503bdea1361Sscw }
1504bdea1361Sscw
1505bdea1361Sscw #if 0
1506bdea1361Sscw /*
1507bdea1361Sscw * Get the current statistics block.
1508bdea1361Sscw */
1509bdea1361Sscw static int
1510bdea1361Sscw npe_getstats(struct npe_softc *sc)
1511bdea1361Sscw {
1512bdea1361Sscw uint32_t msg[2];
1513bdea1361Sscw
1514bdea1361Sscw msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL;
1515bdea1361Sscw msg[1] = sc->sc_stats_phys; /* physical address of stat block */
1516bdea1361Sscw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1517bdea1361Sscw }
1518bdea1361Sscw
1519bdea1361Sscw /*
1520bdea1361Sscw * Query the image id of the loaded firmware.
1521bdea1361Sscw */
1522bdea1361Sscw static uint32_t
1523bdea1361Sscw npe_getimageid(struct npe_softc *sc)
1524bdea1361Sscw {
1525bdea1361Sscw uint32_t msg[2];
1526bdea1361Sscw
1527bdea1361Sscw msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL;
1528bdea1361Sscw msg[1] = 0;
1529bdea1361Sscw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0;
1530bdea1361Sscw }
1531bdea1361Sscw
1532bdea1361Sscw /*
1533bdea1361Sscw * Enable/disable loopback.
1534bdea1361Sscw */
1535bdea1361Sscw static int
1536bdea1361Sscw npe_setloopback(struct npe_softc *sc, int ena)
1537bdea1361Sscw {
1538bdea1361Sscw uint32_t msg[2];
1539bdea1361Sscw
1540bdea1361Sscw msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0);
1541bdea1361Sscw msg[1] = 0;
1542bdea1361Sscw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1543bdea1361Sscw }
1544bdea1361Sscw #endif
1545bdea1361Sscw
1546bdea1361Sscw /*
1547bdea1361Sscw * MII bus support routines.
1548bdea1361Sscw *
1549bdea1361Sscw * NB: ixp425 has one PHY per NPE
1550bdea1361Sscw */
1551bdea1361Sscw static uint32_t
npe_mii_mdio_read(struct npe_softc * sc,int reg)1552bdea1361Sscw npe_mii_mdio_read(struct npe_softc *sc, int reg)
1553bdea1361Sscw {
1554bdea1361Sscw #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg)
1555bdea1361Sscw uint32_t v;
1556bdea1361Sscw
1557bdea1361Sscw /* NB: registers are known to be sequential */
1558bdea1361Sscw v = (MII_RD4(sc, reg+0) & 0xff) << 0;
1559bdea1361Sscw v |= (MII_RD4(sc, reg+4) & 0xff) << 8;
1560bdea1361Sscw v |= (MII_RD4(sc, reg+8) & 0xff) << 16;
1561bdea1361Sscw v |= (MII_RD4(sc, reg+12) & 0xff) << 24;
1562bdea1361Sscw return v;
1563bdea1361Sscw #undef MII_RD4
1564bdea1361Sscw }
1565bdea1361Sscw
1566bdea1361Sscw static void
npe_mii_mdio_write(struct npe_softc * sc,int reg,uint32_t cmd)1567bdea1361Sscw npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd)
1568bdea1361Sscw {
1569bdea1361Sscw #define MII_WR4(sc, reg, v) \
1570bdea1361Sscw bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v)
1571bdea1361Sscw
1572bdea1361Sscw /* NB: registers are known to be sequential */
1573bdea1361Sscw MII_WR4(sc, reg+0, cmd & 0xff);
1574bdea1361Sscw MII_WR4(sc, reg+4, (cmd >> 8) & 0xff);
1575bdea1361Sscw MII_WR4(sc, reg+8, (cmd >> 16) & 0xff);
1576bdea1361Sscw MII_WR4(sc, reg+12, (cmd >> 24) & 0xff);
1577bdea1361Sscw #undef MII_WR4
1578bdea1361Sscw }
1579bdea1361Sscw
1580bdea1361Sscw static int
npe_mii_mdio_wait(struct npe_softc * sc)1581bdea1361Sscw npe_mii_mdio_wait(struct npe_softc *sc)
1582bdea1361Sscw {
1583bdea1361Sscw #define MAXTRIES 100 /* XXX */
1584bdea1361Sscw uint32_t v;
1585bdea1361Sscw int i;
1586bdea1361Sscw
1587bdea1361Sscw for (i = 0; i < MAXTRIES; i++) {
1588bdea1361Sscw v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD);
1589bdea1361Sscw if ((v & NPE_MII_GO) == 0)
1590e746222fSmsaitoh return 0;
1591bdea1361Sscw }
1592e746222fSmsaitoh return ETIMEDOUT;
1593bdea1361Sscw #undef MAXTRIES
1594bdea1361Sscw }
1595bdea1361Sscw
1596bdea1361Sscw static int
npe_miibus_readreg(device_t self,int phy,int reg,uint16_t * val)1597e746222fSmsaitoh npe_miibus_readreg(device_t self, int phy, int reg, uint16_t *val)
1598bdea1361Sscw {
1599e20bd029Smatt struct npe_softc *sc = device_private(self);
1600bdea1361Sscw uint32_t v;
1601bdea1361Sscw
1602bdea1361Sscw if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy)
1603e746222fSmsaitoh return -1;
1604bdea1361Sscw v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL)
1605bdea1361Sscw | NPE_MII_GO;
1606bdea1361Sscw npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v);
1607e746222fSmsaitoh if (npe_mii_mdio_wait(sc) == 0)
1608bdea1361Sscw v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS);
1609bdea1361Sscw else
1610bdea1361Sscw v = 0xffff | NPE_MII_READ_FAIL;
1611e746222fSmsaitoh
1612e746222fSmsaitoh if ((v & NPE_MII_READ_FAIL) != 0)
1613e746222fSmsaitoh return -1;
1614e746222fSmsaitoh
1615e746222fSmsaitoh *val = v & 0xffff;
1616e746222fSmsaitoh return 0;
1617bdea1361Sscw #undef MAXTRIES
1618bdea1361Sscw }
1619bdea1361Sscw
1620e746222fSmsaitoh static int
npe_miibus_writereg(device_t self,int phy,int reg,uint16_t val)1621e746222fSmsaitoh npe_miibus_writereg(device_t self, int phy, int reg, uint16_t val)
1622bdea1361Sscw {
1623e20bd029Smatt struct npe_softc *sc = device_private(self);
1624bdea1361Sscw uint32_t v;
1625bdea1361Sscw
1626bdea1361Sscw if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy)
1627e746222fSmsaitoh return -1;
1628bdea1361Sscw v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL)
1629e746222fSmsaitoh | val | NPE_MII_WRITE
1630bdea1361Sscw | NPE_MII_GO;
1631bdea1361Sscw npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v);
1632e746222fSmsaitoh
1633e746222fSmsaitoh return npe_mii_mdio_wait(sc);
1634bdea1361Sscw }
1635bdea1361Sscw
1636bdea1361Sscw static void
npe_miibus_statchg(struct ifnet * ifp)1637e20bd029Smatt npe_miibus_statchg(struct ifnet *ifp)
1638bdea1361Sscw {
1639e20bd029Smatt struct npe_softc *sc = ifp->if_softc;
1640bdea1361Sscw uint32_t tx1, rx1;
1641227ae4c9Smsaitoh uint32_t randoff;
1642bdea1361Sscw
164312f4368bSmsaitoh /* Sync MAC duplex state */
1644bdea1361Sscw tx1 = RD4(sc, NPE_MAC_TX_CNTRL1);
1645bdea1361Sscw rx1 = RD4(sc, NPE_MAC_RX_CNTRL1);
1646bdea1361Sscw if (sc->sc_mii.mii_media_active & IFM_FDX) {
1647227ae4c9Smsaitoh WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT);
1648bdea1361Sscw tx1 &= ~NPE_TX_CNTRL1_DUPLEX;
1649bdea1361Sscw rx1 |= NPE_RX_CNTRL1_PAUSE_EN;
1650bdea1361Sscw } else {
1651227ae4c9Smsaitoh struct timeval now;
1652227ae4c9Smsaitoh getmicrotime(&now);
1653227ae4c9Smsaitoh randoff = (RD4(sc, NPE_MAC_UNI_ADDR_6) ^ now.tv_usec)
1654227ae4c9Smsaitoh & 0x7f;
1655227ae4c9Smsaitoh WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT
1656227ae4c9Smsaitoh + randoff);
1657bdea1361Sscw tx1 |= NPE_TX_CNTRL1_DUPLEX;
1658bdea1361Sscw rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN;
1659bdea1361Sscw }
1660bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL1, rx1);
1661bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL1, tx1);
1662bdea1361Sscw }
1663