1*8e933452Stls /* $NetBSD: ixp425_if_npe.c,v 1.21 2011/11/19 22:51:19 tls Exp $ */ 2bdea1361Sscw 3bdea1361Sscw /*- 4bdea1361Sscw * Copyright (c) 2006 Sam Leffler. All rights reserved. 5bdea1361Sscw * 6bdea1361Sscw * Redistribution and use in source and binary forms, with or without 7bdea1361Sscw * modification, are permitted provided that the following conditions 8bdea1361Sscw * are met: 9bdea1361Sscw * 1. Redistributions of source code must retain the above copyright 10bdea1361Sscw * notice, this list of conditions and the following disclaimer. 11bdea1361Sscw * 2. Redistributions in binary form must reproduce the above copyright 12bdea1361Sscw * notice, this list of conditions and the following disclaimer in the 13bdea1361Sscw * documentation and/or other materials provided with the distribution. 14bdea1361Sscw * 15bdea1361Sscw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16bdea1361Sscw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17bdea1361Sscw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18bdea1361Sscw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19bdea1361Sscw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20bdea1361Sscw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21bdea1361Sscw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22bdea1361Sscw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23bdea1361Sscw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24bdea1361Sscw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25bdea1361Sscw */ 26bdea1361Sscw 27bdea1361Sscw #include <sys/cdefs.h> 28bdea1361Sscw #if 0 29bdea1361Sscw __FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/if_npe.c,v 1.1 2006/11/19 23:55:23 sam Exp $"); 30bdea1361Sscw #endif 31*8e933452Stls __KERNEL_RCSID(0, "$NetBSD: ixp425_if_npe.c,v 1.21 2011/11/19 22:51:19 tls Exp $"); 32bdea1361Sscw 33bdea1361Sscw /* 34bdea1361Sscw * Intel XScale NPE Ethernet driver. 35bdea1361Sscw * 36bdea1361Sscw * This driver handles the two ports present on the IXP425. 37bdea1361Sscw * Packet processing is done by the Network Processing Engines 38bdea1361Sscw * (NPE's) that work together with a MAC and PHY. The MAC 39bdea1361Sscw * is also mapped to the XScale cpu; the PHY is accessed via 40bdea1361Sscw * the MAC. NPE-XScale communication happens through h/w 41bdea1361Sscw * queues managed by the Q Manager block. 42bdea1361Sscw * 43bdea1361Sscw * The code here replaces the ethAcc, ethMii, and ethDB classes 44bdea1361Sscw * in the Intel Access Library (IAL) and the OS-specific driver. 45bdea1361Sscw * 46bdea1361Sscw * XXX add vlan support 47bdea1361Sscw * XXX NPE-C port doesn't work yet 48bdea1361Sscw */ 49bdea1361Sscw 50507aaf9eSmsaitoh #include "rnd.h" 51bdea1361Sscw 52bdea1361Sscw #include <sys/param.h> 53bdea1361Sscw #include <sys/systm.h> 54bdea1361Sscw #include <sys/kernel.h> 55bdea1361Sscw #include <sys/device.h> 56bdea1361Sscw #include <sys/callout.h> 57bdea1361Sscw #include <sys/mbuf.h> 58bdea1361Sscw #include <sys/malloc.h> 59bdea1361Sscw #include <sys/socket.h> 60bdea1361Sscw #include <sys/endian.h> 61bdea1361Sscw #include <sys/ioctl.h> 623589a8fdSmsaitoh #include <sys/syslog.h> 63bdea1361Sscw 64af51edd2Sdyoung #include <sys/bus.h> 65bdea1361Sscw 66bdea1361Sscw #include <net/if.h> 67bdea1361Sscw #include <net/if_dl.h> 68bdea1361Sscw #include <net/if_media.h> 69bdea1361Sscw #include <net/if_ether.h> 70bdea1361Sscw 71bdea1361Sscw #include <net/bpf.h> 72bdea1361Sscw 73507aaf9eSmsaitoh #if NRND > 0 74507aaf9eSmsaitoh #include <sys/rnd.h> 75507aaf9eSmsaitoh #endif 76507aaf9eSmsaitoh 77bdea1361Sscw #include <arm/xscale/ixp425reg.h> 78bdea1361Sscw #include <arm/xscale/ixp425var.h> 79bdea1361Sscw #include <arm/xscale/ixp425_qmgr.h> 80bdea1361Sscw #include <arm/xscale/ixp425_npevar.h> 81bdea1361Sscw #include <arm/xscale/ixp425_if_npereg.h> 82bdea1361Sscw 83bdea1361Sscw #include <dev/mii/miivar.h> 84bdea1361Sscw 85bdea1361Sscw #include "locators.h" 86bdea1361Sscw 87bdea1361Sscw struct npebuf { 88bdea1361Sscw struct npebuf *ix_next; /* chain to next buffer */ 89bdea1361Sscw void *ix_m; /* backpointer to mbuf */ 90bdea1361Sscw bus_dmamap_t ix_map; /* bus dma map for associated data */ 91bdea1361Sscw struct npehwbuf *ix_hw; /* associated h/w block */ 92bdea1361Sscw uint32_t ix_neaddr; /* phys address of ix_hw */ 93bdea1361Sscw }; 94bdea1361Sscw 95bdea1361Sscw struct npedma { 96bdea1361Sscw const char* name; 97bdea1361Sscw int nbuf; /* # npebuf's allocated */ 98bdea1361Sscw bus_dmamap_t m_map; 99bdea1361Sscw struct npehwbuf *hwbuf; /* NPE h/w buffers */ 100bdea1361Sscw bus_dmamap_t buf_map; 101bdea1361Sscw bus_addr_t buf_phys; /* phys addr of buffers */ 102bdea1361Sscw struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 103bdea1361Sscw }; 104bdea1361Sscw 105bdea1361Sscw struct npe_softc { 106bdea1361Sscw struct device sc_dev; 107bdea1361Sscw struct ethercom sc_ethercom; 1083589a8fdSmsaitoh uint8_t sc_enaddr[ETHER_ADDR_LEN]; 109bdea1361Sscw struct mii_data sc_mii; 110bdea1361Sscw bus_space_tag_t sc_iot; 111bdea1361Sscw bus_dma_tag_t sc_dt; 112bdea1361Sscw bus_space_handle_t sc_ioh; /* MAC register window */ 113bdea1361Sscw bus_space_handle_t sc_miih; /* MII register window */ 114bdea1361Sscw struct ixpnpe_softc *sc_npe; /* NPE support */ 115bdea1361Sscw int sc_unit; 116bdea1361Sscw int sc_phy; 117bdea1361Sscw struct callout sc_tick_ch; /* Tick callout */ 118bdea1361Sscw struct npedma txdma; 119bdea1361Sscw struct npebuf *tx_free; /* list of free tx buffers */ 120bdea1361Sscw struct npedma rxdma; 121bdea1361Sscw int rx_qid; /* rx qid */ 122bdea1361Sscw int rx_freeqid; /* rx free buffers qid */ 123bdea1361Sscw int tx_qid; /* tx qid */ 124bdea1361Sscw int tx_doneqid; /* tx completed qid */ 125bdea1361Sscw struct npestats *sc_stats; 126bdea1361Sscw bus_dmamap_t sc_stats_map; 127bdea1361Sscw bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 128816cf5b8Smsaitoh int sc_if_flags; /* keep last if_flags */ 129507aaf9eSmsaitoh #if NRND > 0 130*8e933452Stls krndsource_t rnd_source; /* random source */ 131507aaf9eSmsaitoh #endif 132bdea1361Sscw }; 133bdea1361Sscw 134bdea1361Sscw /* 135bdea1361Sscw * Per-unit static configuration for IXP425. The tx and 136bdea1361Sscw * rx free Q id's are fixed by the NPE microcode. The 137bdea1361Sscw * rx Q id's are programmed to be separate to simplify 138bdea1361Sscw * multi-port processing. It may be better to handle 139bdea1361Sscw * all traffic through one Q (as done by the Intel drivers). 140bdea1361Sscw * 141bdea1361Sscw * Note that the PHY's are accessible only from MAC A 142bdea1361Sscw * on the IXP425. This and other platform-specific 143bdea1361Sscw * assumptions probably need to be handled through hints. 144bdea1361Sscw */ 145bdea1361Sscw static const struct { 146bdea1361Sscw const char *desc; /* device description */ 147bdea1361Sscw int npeid; /* NPE assignment */ 148227ae4c9Smsaitoh int macport; /* Port number of the MAC */ 149bdea1361Sscw uint32_t imageid; /* NPE firmware image id */ 150bdea1361Sscw uint32_t regbase; 151bdea1361Sscw int regsize; 152bdea1361Sscw uint32_t miibase; 153bdea1361Sscw int miisize; 154bdea1361Sscw uint8_t rx_qid; 155bdea1361Sscw uint8_t rx_freeqid; 156bdea1361Sscw uint8_t tx_qid; 157bdea1361Sscw uint8_t tx_doneqid; 158bdea1361Sscw } npeconfig[NPE_PORTS_MAX] = { 159bdea1361Sscw { .desc = "IXP NPE-B", 160bdea1361Sscw .npeid = NPE_B, 161227ae4c9Smsaitoh .macport = 0x10, 162bdea1361Sscw .imageid = IXP425_NPE_B_IMAGEID, 163bdea1361Sscw .regbase = IXP425_MAC_A_HWBASE, 164bdea1361Sscw .regsize = IXP425_MAC_A_SIZE, 165bdea1361Sscw .miibase = IXP425_MAC_A_HWBASE, 166bdea1361Sscw .miisize = IXP425_MAC_A_SIZE, 167bdea1361Sscw .rx_qid = 4, 168bdea1361Sscw .rx_freeqid = 27, 169bdea1361Sscw .tx_qid = 24, 170bdea1361Sscw .tx_doneqid = 31 171bdea1361Sscw }, 172bdea1361Sscw { .desc = "IXP NPE-C", 173bdea1361Sscw .npeid = NPE_C, 174227ae4c9Smsaitoh .macport = 0x20, 175bdea1361Sscw .imageid = IXP425_NPE_C_IMAGEID, 176bdea1361Sscw .regbase = IXP425_MAC_B_HWBASE, 177bdea1361Sscw .regsize = IXP425_MAC_B_SIZE, 178bdea1361Sscw .miibase = IXP425_MAC_A_HWBASE, 179bdea1361Sscw .miisize = IXP425_MAC_A_SIZE, 180bdea1361Sscw .rx_qid = 12, 181bdea1361Sscw .rx_freeqid = 28, 182bdea1361Sscw .tx_qid = 25, 183bdea1361Sscw .tx_doneqid = 31 184bdea1361Sscw }, 185bdea1361Sscw }; 186bdea1361Sscw static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 187bdea1361Sscw 188bdea1361Sscw static __inline uint32_t 189bdea1361Sscw RD4(struct npe_softc *sc, bus_size_t off) 190bdea1361Sscw { 191bdea1361Sscw return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 192bdea1361Sscw } 193bdea1361Sscw 194bdea1361Sscw static __inline void 195bdea1361Sscw WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 196bdea1361Sscw { 197bdea1361Sscw bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 198bdea1361Sscw } 199bdea1361Sscw 200bdea1361Sscw static int npe_activate(struct npe_softc *); 201bdea1361Sscw #if 0 202bdea1361Sscw static void npe_deactivate(struct npe_softc *); 203bdea1361Sscw #endif 204bdea1361Sscw static void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr); 2056bc0c582Smatt static void npe_setmac(struct npe_softc *sc, const u_char *eaddr); 2063589a8fdSmsaitoh static void npe_getmac(struct npe_softc *sc); 207bdea1361Sscw static void npe_txdone(int qid, void *arg); 208bdea1361Sscw static int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 209bdea1361Sscw struct mbuf *); 210bdea1361Sscw static void npe_rxdone(int qid, void *arg); 211816cf5b8Smsaitoh static void npeinit_macreg(struct npe_softc *); 212bdea1361Sscw static int npeinit(struct ifnet *); 213227ae4c9Smsaitoh static void npeinit_resetcb(void *); 214816cf5b8Smsaitoh static void npeinit_locked(void *); 215bdea1361Sscw static void npestart(struct ifnet *); 216bdea1361Sscw static void npestop(struct ifnet *, int); 217bdea1361Sscw static void npewatchdog(struct ifnet *); 21853524e44Schristos static int npeioctl(struct ifnet * ifp, u_long, void *); 219bdea1361Sscw 220bdea1361Sscw static int npe_setrxqosentry(struct npe_softc *, int classix, 221bdea1361Sscw int trafclass, int qid); 222bdea1361Sscw static int npe_updatestats(struct npe_softc *); 223bdea1361Sscw #if 0 224bdea1361Sscw static int npe_getstats(struct npe_softc *); 225bdea1361Sscw static uint32_t npe_getimageid(struct npe_softc *); 226bdea1361Sscw static int npe_setloopback(struct npe_softc *, int ena); 227bdea1361Sscw #endif 228bdea1361Sscw 229bdea1361Sscw static int npe_miibus_readreg(struct device *, int, int); 230bdea1361Sscw static void npe_miibus_writereg(struct device *, int, int, int); 231bdea1361Sscw static void npe_miibus_statchg(struct device *); 232bdea1361Sscw 233bdea1361Sscw static int npe_debug; 234bdea1361Sscw #define DPRINTF(sc, fmt, ...) do { \ 235bdea1361Sscw if (npe_debug) printf(fmt, __VA_ARGS__); \ 236bdea1361Sscw } while (0) 237bdea1361Sscw #define DPRINTFn(n, sc, fmt, ...) do { \ 238bdea1361Sscw if (npe_debug >= n) printf(fmt, __VA_ARGS__); \ 239bdea1361Sscw } while (0) 240bdea1361Sscw 241bdea1361Sscw #define NPE_TXBUF 128 242bdea1361Sscw #define NPE_RXBUF 64 243bdea1361Sscw 244bdea1361Sscw #ifndef ETHER_ALIGN 245bdea1361Sscw #define ETHER_ALIGN 2 /* XXX: Ditch this */ 246bdea1361Sscw #endif 247bdea1361Sscw 2483589a8fdSmsaitoh #define MAC2UINT64(addr) (((uint64_t)addr[0] << 40) \ 2493589a8fdSmsaitoh + ((uint64_t)addr[1] << 32) \ 2503589a8fdSmsaitoh + ((uint64_t)addr[2] << 24) \ 2513589a8fdSmsaitoh + ((uint64_t)addr[3] << 16) \ 2523589a8fdSmsaitoh + ((uint64_t)addr[4] << 8) \ 2533589a8fdSmsaitoh + (uint64_t)addr[5]) 2543589a8fdSmsaitoh 255bdea1361Sscw /* NB: all tx done processing goes through one queue */ 256bdea1361Sscw static int tx_doneqid = -1; 257bdea1361Sscw 2583589a8fdSmsaitoh void (*npe_getmac_md)(int, uint8_t *); 2593589a8fdSmsaitoh 260bdea1361Sscw static int npe_match(struct device *, struct cfdata *, void *); 261bdea1361Sscw static void npe_attach(struct device *, struct device *, void *); 262bdea1361Sscw 263bdea1361Sscw CFATTACH_DECL(npe, sizeof(struct npe_softc), 264bdea1361Sscw npe_match, npe_attach, NULL, NULL); 265bdea1361Sscw 266bdea1361Sscw static int 267bdea1361Sscw npe_match(struct device *parent, struct cfdata *cf, void *arg) 268bdea1361Sscw { 269bdea1361Sscw struct ixpnpe_attach_args *na = arg; 270bdea1361Sscw 271bdea1361Sscw return (na->na_unit == NPE_B || na->na_unit == NPE_C); 272bdea1361Sscw } 273bdea1361Sscw 274bdea1361Sscw static void 275bdea1361Sscw npe_attach(struct device *parent, struct device *self, void *arg) 276bdea1361Sscw { 277bdea1361Sscw struct npe_softc *sc = (void *)self; 278bdea1361Sscw struct ixpnpe_attach_args *na = arg; 279227ae4c9Smsaitoh struct ixpnpe_softc *isc = (struct ixpnpe_softc *)parent; 280bdea1361Sscw struct ifnet *ifp; 281bdea1361Sscw 282bdea1361Sscw aprint_naive("\n"); 283bdea1361Sscw aprint_normal(": Ethernet co-processor\n"); 284bdea1361Sscw 285bdea1361Sscw sc->sc_iot = na->na_iot; 286bdea1361Sscw sc->sc_dt = na->na_dt; 287bdea1361Sscw sc->sc_npe = na->na_npe; 288bdea1361Sscw sc->sc_unit = (na->na_unit == NPE_B) ? 0 : 1; 289bdea1361Sscw sc->sc_phy = na->na_phy; 290bdea1361Sscw 291bdea1361Sscw memset(&sc->sc_ethercom, 0, sizeof(sc->sc_ethercom)); 292bdea1361Sscw memset(&sc->sc_mii, 0, sizeof(sc->sc_mii)); 293bdea1361Sscw 29488ab7da9Sad callout_init(&sc->sc_tick_ch, 0); 295bdea1361Sscw 296bdea1361Sscw if (npe_activate(sc)) { 297bdea1361Sscw aprint_error("%s: Failed to activate NPE (missing " 298bdea1361Sscw "microcode?)\n", sc->sc_dev.dv_xname); 299bdea1361Sscw return; 300bdea1361Sscw } 301bdea1361Sscw 3023589a8fdSmsaitoh npe_getmac(sc); 303b9c2a505Smsaitoh npeinit_macreg(sc); 304bdea1361Sscw 305bdea1361Sscw aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 3063589a8fdSmsaitoh ether_sprintf(sc->sc_enaddr)); 307bdea1361Sscw 308bdea1361Sscw ifp = &sc->sc_ethercom.ec_if; 309bdea1361Sscw sc->sc_mii.mii_ifp = ifp; 310bdea1361Sscw sc->sc_mii.mii_readreg = npe_miibus_readreg; 311bdea1361Sscw sc->sc_mii.mii_writereg = npe_miibus_writereg; 312bdea1361Sscw sc->sc_mii.mii_statchg = npe_miibus_statchg; 313b480b622Sdyoung sc->sc_ethercom.ec_mii = &sc->sc_mii; 314bdea1361Sscw 315273cfb27Smsaitoh ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 316273cfb27Smsaitoh npe_ifmedia_status); 317273cfb27Smsaitoh 318273cfb27Smsaitoh mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 319273cfb27Smsaitoh MII_OFFSET_ANY, MIIF_DOPAUSE); 320273cfb27Smsaitoh if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 321273cfb27Smsaitoh ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 322273cfb27Smsaitoh ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 323273cfb27Smsaitoh } else 324bdea1361Sscw ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 325bdea1361Sscw 326bdea1361Sscw ifp->if_softc = sc; 327bdea1361Sscw strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 328bdea1361Sscw ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 329bdea1361Sscw ifp->if_start = npestart; 330bdea1361Sscw ifp->if_ioctl = npeioctl; 331bdea1361Sscw ifp->if_watchdog = npewatchdog; 332bdea1361Sscw ifp->if_init = npeinit; 333bdea1361Sscw ifp->if_stop = npestop; 334bdea1361Sscw IFQ_SET_READY(&ifp->if_snd); 335bdea1361Sscw 3368586a845Smsaitoh /* VLAN capable */ 3378586a845Smsaitoh sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 3388586a845Smsaitoh 339bdea1361Sscw if_attach(ifp); 3403589a8fdSmsaitoh ether_ifattach(ifp, sc->sc_enaddr); 341507aaf9eSmsaitoh #if NRND > 0 342507aaf9eSmsaitoh rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 343507aaf9eSmsaitoh RND_TYPE_NET, 0); 344507aaf9eSmsaitoh #endif 345227ae4c9Smsaitoh 346227ae4c9Smsaitoh /* callback function to reset MAC */ 347227ae4c9Smsaitoh isc->macresetcbfunc = npeinit_resetcb; 348227ae4c9Smsaitoh isc->macresetcbarg = sc; 349bdea1361Sscw } 350bdea1361Sscw 351bdea1361Sscw /* 352bdea1361Sscw * Compute and install the multicast filter. 353bdea1361Sscw */ 354bdea1361Sscw static void 355bdea1361Sscw npe_setmcast(struct npe_softc *sc) 356bdea1361Sscw { 357bdea1361Sscw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 358bdea1361Sscw uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 3593589a8fdSmsaitoh uint32_t reg; 360227ae4c9Smsaitoh uint32_t msg[2]; 361bdea1361Sscw int i; 362bdea1361Sscw 3633589a8fdSmsaitoh /* Always use filter. Is here a correct position? */ 3643589a8fdSmsaitoh reg = RD4(sc, NPE_MAC_RX_CNTRL1); 3653589a8fdSmsaitoh WR4(sc, NPE_MAC_RX_CNTRL1, reg | NPE_RX_CNTRL1_ADDR_FLTR_EN); 3663589a8fdSmsaitoh 367bdea1361Sscw if (ifp->if_flags & IFF_PROMISC) { 368bdea1361Sscw memset(mask, 0, ETHER_ADDR_LEN); 369bdea1361Sscw memset(addr, 0, ETHER_ADDR_LEN); 370bdea1361Sscw } else if (ifp->if_flags & IFF_ALLMULTI) { 371bdea1361Sscw static const uint8_t allmulti[ETHER_ADDR_LEN] = 372bdea1361Sscw { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 373bdea1361Sscw all_multi: 374bdea1361Sscw memcpy(mask, allmulti, ETHER_ADDR_LEN); 375bdea1361Sscw memcpy(addr, allmulti, ETHER_ADDR_LEN); 376bdea1361Sscw } else { 377bdea1361Sscw uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 378bdea1361Sscw struct ether_multistep step; 379bdea1361Sscw struct ether_multi *enm; 380bdea1361Sscw 381bdea1361Sscw memset(clr, 0, ETHER_ADDR_LEN); 382bdea1361Sscw memset(set, 0xff, ETHER_ADDR_LEN); 383bdea1361Sscw 384bdea1361Sscw ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 385bdea1361Sscw while (enm != NULL) { 386bdea1361Sscw if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 387bdea1361Sscw ifp->if_flags |= IFF_ALLMULTI; 388bdea1361Sscw goto all_multi; 389bdea1361Sscw } 390bdea1361Sscw 391bdea1361Sscw for (i = 0; i < ETHER_ADDR_LEN; i++) { 392bdea1361Sscw clr[i] |= enm->enm_addrlo[i]; 393bdea1361Sscw set[i] &= enm->enm_addrlo[i]; 394bdea1361Sscw } 395bdea1361Sscw 396bdea1361Sscw ETHER_NEXT_MULTI(step, enm); 397bdea1361Sscw } 398bdea1361Sscw 399bdea1361Sscw for (i = 0; i < ETHER_ADDR_LEN; i++) { 400bdea1361Sscw mask[i] = set[i] | ~clr[i]; 401bdea1361Sscw addr[i] = set[i]; 402bdea1361Sscw } 403bdea1361Sscw } 404bdea1361Sscw 405bdea1361Sscw /* 406bdea1361Sscw * Write the mask and address registers. 407bdea1361Sscw */ 408bdea1361Sscw for (i = 0; i < ETHER_ADDR_LEN; i++) { 409bdea1361Sscw WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 410bdea1361Sscw WR4(sc, NPE_MAC_ADDR(i), addr[i]); 411bdea1361Sscw } 412227ae4c9Smsaitoh 413227ae4c9Smsaitoh msg[0] = NPE_ADDRESSFILTERCONFIG << NPE_MAC_MSGID_SHL 414227ae4c9Smsaitoh | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL); 415227ae4c9Smsaitoh msg[1] = ((ifp->if_flags & IFF_PROMISC) ? 1 : 0) << 24 416227ae4c9Smsaitoh | ((RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff) << 16) 417227ae4c9Smsaitoh | (addr[5] << 8) | mask[5]; 418227ae4c9Smsaitoh ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 419bdea1361Sscw } 420bdea1361Sscw 421bdea1361Sscw static int 422bdea1361Sscw npe_dma_setup(struct npe_softc *sc, struct npedma *dma, 423bdea1361Sscw const char *name, int nbuf, int maxseg) 424bdea1361Sscw { 425bdea1361Sscw bus_dma_segment_t seg; 426bdea1361Sscw int rseg, error, i; 42753524e44Schristos void *hwbuf; 428bdea1361Sscw size_t size; 429bdea1361Sscw 4308586a845Smsaitoh memset(dma, 0, sizeof(*dma)); 431bdea1361Sscw 432bdea1361Sscw dma->name = name; 433bdea1361Sscw dma->nbuf = nbuf; 434bdea1361Sscw 435bdea1361Sscw size = nbuf * sizeof(struct npehwbuf); 436bdea1361Sscw 437bdea1361Sscw /* XXX COHERENT for now */ 438bdea1361Sscw error = bus_dmamem_alloc(sc->sc_dt, size, sizeof(uint32_t), 0, &seg, 439bdea1361Sscw 1, &rseg, BUS_DMA_NOWAIT); 440bdea1361Sscw if (error) { 441bdea1361Sscw printf("%s: unable to allocate memory for %s h/w buffers, " 442bdea1361Sscw "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 443bdea1361Sscw } 444bdea1361Sscw 445bdea1361Sscw error = bus_dmamem_map(sc->sc_dt, &seg, 1, size, &hwbuf, 446bdea1361Sscw BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE); 447bdea1361Sscw if (error) { 448bdea1361Sscw printf("%s: unable to map memory for %s h/w buffers, " 449bdea1361Sscw "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 450bdea1361Sscw free_dmamem: 451bdea1361Sscw bus_dmamem_free(sc->sc_dt, &seg, rseg); 452bdea1361Sscw return error; 453bdea1361Sscw } 454bdea1361Sscw dma->hwbuf = (void *)hwbuf; 455bdea1361Sscw 456bdea1361Sscw error = bus_dmamap_create(sc->sc_dt, size, 1, size, 0, 457bdea1361Sscw BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dma->buf_map); 458bdea1361Sscw if (error) { 459bdea1361Sscw printf("%s: unable to create map for %s h/w buffers, " 460bdea1361Sscw "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 461bdea1361Sscw unmap_dmamem: 462bdea1361Sscw dma->hwbuf = NULL; 463bdea1361Sscw bus_dmamem_unmap(sc->sc_dt, hwbuf, size); 464bdea1361Sscw goto free_dmamem; 465bdea1361Sscw } 466bdea1361Sscw 467bdea1361Sscw error = bus_dmamap_load(sc->sc_dt, dma->buf_map, hwbuf, size, NULL, 468bdea1361Sscw BUS_DMA_NOWAIT); 469bdea1361Sscw if (error) { 470bdea1361Sscw printf("%s: unable to load map for %s h/w buffers, " 471bdea1361Sscw "error %u\n", sc->sc_dev.dv_xname, dma->name, error); 472bdea1361Sscw destroy_dmamap: 473bdea1361Sscw bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 474bdea1361Sscw goto unmap_dmamem; 475bdea1361Sscw } 476bdea1361Sscw 477bdea1361Sscw /* XXX M_TEMP */ 478bdea1361Sscw dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO); 479bdea1361Sscw if (dma->buf == NULL) { 480bdea1361Sscw printf("%s: unable to allocate memory for %s s/w buffers\n", 481bdea1361Sscw sc->sc_dev.dv_xname, dma->name); 482bdea1361Sscw bus_dmamap_unload(sc->sc_dt, dma->buf_map); 483bdea1361Sscw error = ENOMEM; 484bdea1361Sscw goto destroy_dmamap; 485bdea1361Sscw } 486bdea1361Sscw 487bdea1361Sscw dma->buf_phys = dma->buf_map->dm_segs[0].ds_addr; 488bdea1361Sscw for (i = 0; i < dma->nbuf; i++) { 489bdea1361Sscw struct npebuf *npe = &dma->buf[i]; 490bdea1361Sscw struct npehwbuf *hw = &dma->hwbuf[i]; 491bdea1361Sscw 492bdea1361Sscw /* calculate offset to shared area */ 493bdea1361Sscw npe->ix_neaddr = dma->buf_phys + 494bdea1361Sscw ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 495bdea1361Sscw KASSERT((npe->ix_neaddr & 0x1f) == 0); 4968586a845Smsaitoh error = bus_dmamap_create(sc->sc_dt, MCLBYTES, maxseg, 497bdea1361Sscw MCLBYTES, 0, 0, &npe->ix_map); 498bdea1361Sscw if (error != 0) { 499bdea1361Sscw printf("%s: unable to create dmamap for %s buffer %u, " 500bdea1361Sscw "error %u\n", sc->sc_dev.dv_xname, dma->name, i, 501bdea1361Sscw error); 502bdea1361Sscw /* XXXSCW: Free up maps... */ 503bdea1361Sscw return error; 504bdea1361Sscw } 505bdea1361Sscw npe->ix_hw = hw; 506bdea1361Sscw } 507bdea1361Sscw bus_dmamap_sync(sc->sc_dt, dma->buf_map, 0, dma->buf_map->dm_mapsize, 508bdea1361Sscw BUS_DMASYNC_PREWRITE); 509bdea1361Sscw return 0; 510bdea1361Sscw } 511bdea1361Sscw 512bdea1361Sscw #if 0 513bdea1361Sscw static void 514bdea1361Sscw npe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 515bdea1361Sscw { 516bdea1361Sscw int i; 517bdea1361Sscw 518bdea1361Sscw /* XXXSCW: Clean this up */ 519bdea1361Sscw 520bdea1361Sscw if (dma->hwbuf != NULL) { 521bdea1361Sscw for (i = 0; i < dma->nbuf; i++) { 522bdea1361Sscw struct npebuf *npe = &dma->buf[i]; 523bdea1361Sscw bus_dmamap_destroy(sc->sc_dt, npe->ix_map); 524bdea1361Sscw } 525bdea1361Sscw bus_dmamap_unload(sc->sc_dt, dma->buf_map); 52653524e44Schristos bus_dmamem_free(sc->sc_dt, (void *)dma->hwbuf, dma->buf_map); 527bdea1361Sscw bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 528bdea1361Sscw } 529bdea1361Sscw if (dma->buf != NULL) 530bdea1361Sscw free(dma->buf, M_TEMP); 531bdea1361Sscw memset(dma, 0, sizeof(*dma)); 532bdea1361Sscw } 533bdea1361Sscw #endif 534bdea1361Sscw 535bdea1361Sscw static int 536bdea1361Sscw npe_activate(struct npe_softc *sc) 537bdea1361Sscw { 538bdea1361Sscw bus_dma_segment_t seg; 539bdea1361Sscw int unit = sc->sc_unit; 540bdea1361Sscw int error, i, rseg; 54153524e44Schristos void *statbuf; 542bdea1361Sscw 543bdea1361Sscw /* load NPE firmware and start it running */ 544bdea1361Sscw error = ixpnpe_init(sc->sc_npe, "npe_fw", npeconfig[unit].imageid); 545bdea1361Sscw if (error != 0) 546bdea1361Sscw return error; 547bdea1361Sscw 548bdea1361Sscw if (bus_space_map(sc->sc_iot, npeconfig[unit].regbase, 549bdea1361Sscw npeconfig[unit].regsize, 0, &sc->sc_ioh)) { 550bdea1361Sscw printf("%s: Cannot map registers 0x%x:0x%x\n", 551bdea1361Sscw sc->sc_dev.dv_xname, npeconfig[unit].regbase, 552bdea1361Sscw npeconfig[unit].regsize); 553bdea1361Sscw return ENOMEM; 554bdea1361Sscw } 555bdea1361Sscw 556bdea1361Sscw if (npeconfig[unit].miibase != npeconfig[unit].regbase) { 557bdea1361Sscw /* 558bdea1361Sscw * The PHY's are only accessible from one MAC (it appears) 559bdea1361Sscw * so for other MAC's setup an additional mapping for 560bdea1361Sscw * frobbing the PHY registers. 561bdea1361Sscw */ 562bdea1361Sscw if (bus_space_map(sc->sc_iot, npeconfig[unit].miibase, 563bdea1361Sscw npeconfig[unit].miisize, 0, &sc->sc_miih)) { 564bdea1361Sscw printf("%s: Cannot map MII registers 0x%x:0x%x\n", 565bdea1361Sscw sc->sc_dev.dv_xname, npeconfig[unit].miibase, 566bdea1361Sscw npeconfig[unit].miisize); 567bdea1361Sscw return ENOMEM; 568bdea1361Sscw } 569bdea1361Sscw } else 570bdea1361Sscw sc->sc_miih = sc->sc_ioh; 571bdea1361Sscw error = npe_dma_setup(sc, &sc->txdma, "tx", NPE_TXBUF, NPE_MAXSEG); 572bdea1361Sscw if (error != 0) 573bdea1361Sscw return error; 574bdea1361Sscw error = npe_dma_setup(sc, &sc->rxdma, "rx", NPE_RXBUF, 1); 575bdea1361Sscw if (error != 0) 576bdea1361Sscw return error; 577bdea1361Sscw 578bdea1361Sscw /* setup statistics block */ 579bdea1361Sscw error = bus_dmamem_alloc(sc->sc_dt, sizeof(struct npestats), 580bdea1361Sscw sizeof(uint32_t), 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 581bdea1361Sscw if (error) { 582bdea1361Sscw printf("%s: unable to allocate memory for stats block, " 583bdea1361Sscw "error %u\n", sc->sc_dev.dv_xname, error); 584bdea1361Sscw return error; 585bdea1361Sscw } 586bdea1361Sscw 587bdea1361Sscw error = bus_dmamem_map(sc->sc_dt, &seg, 1, sizeof(struct npestats), 588bdea1361Sscw &statbuf, BUS_DMA_NOWAIT); 589bdea1361Sscw if (error) { 590bdea1361Sscw printf("%s: unable to map memory for stats block, " 591bdea1361Sscw "error %u\n", sc->sc_dev.dv_xname, error); 592bdea1361Sscw return error; 593bdea1361Sscw } 594bdea1361Sscw sc->sc_stats = (void *)statbuf; 595bdea1361Sscw 596bdea1361Sscw error = bus_dmamap_create(sc->sc_dt, sizeof(struct npestats), 1, 597bdea1361Sscw sizeof(struct npestats), 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 598bdea1361Sscw &sc->sc_stats_map); 599bdea1361Sscw if (error) { 600bdea1361Sscw printf("%s: unable to create map for stats block, " 601bdea1361Sscw "error %u\n", sc->sc_dev.dv_xname, error); 602bdea1361Sscw return error; 603bdea1361Sscw } 604bdea1361Sscw 605bdea1361Sscw if (bus_dmamap_load(sc->sc_dt, sc->sc_stats_map, sc->sc_stats, 606bdea1361Sscw sizeof(struct npestats), NULL, BUS_DMA_NOWAIT) != 0) { 607bdea1361Sscw printf("%s: unable to load memory for stats block, error %u\n", 608bdea1361Sscw sc->sc_dev.dv_xname, error); 609bdea1361Sscw return error; 610bdea1361Sscw } 611bdea1361Sscw sc->sc_stats_phys = sc->sc_stats_map->dm_segs[0].ds_addr; 612bdea1361Sscw 613bdea1361Sscw /* XXX disable half-bridge LEARNING+FILTERING feature */ 614bdea1361Sscw 615bdea1361Sscw /* 616bdea1361Sscw * Setup h/w rx/tx queues. There are four q's: 617bdea1361Sscw * rx inbound q of rx'd frames 618bdea1361Sscw * rx_free pool of ixpbuf's for receiving frames 619bdea1361Sscw * tx outbound q of frames to send 620bdea1361Sscw * tx_done q of tx frames that have been processed 621bdea1361Sscw * 622bdea1361Sscw * The NPE handles the actual tx/rx process and the q manager 623bdea1361Sscw * handles the queues. The driver just writes entries to the 624bdea1361Sscw * q manager mailbox's and gets callbacks when there are rx'd 625bdea1361Sscw * frames to process or tx'd frames to reap. These callbacks 626bdea1361Sscw * are controlled by the q configurations; e.g. we get a 627bdea1361Sscw * callback when tx_done has 2 or more frames to process and 628bdea1361Sscw * when the rx q has at least one frame. These setings can 629bdea1361Sscw * changed at the time the q is configured. 630bdea1361Sscw */ 631bdea1361Sscw sc->rx_qid = npeconfig[unit].rx_qid; 632bdea1361Sscw ixpqmgr_qconfig(sc->rx_qid, NPE_RXBUF, 0, 1, 633bdea1361Sscw IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc); 634bdea1361Sscw sc->rx_freeqid = npeconfig[unit].rx_freeqid; 635bdea1361Sscw ixpqmgr_qconfig(sc->rx_freeqid, NPE_RXBUF, 0, NPE_RXBUF/2, 0, NULL, sc); 636bdea1361Sscw /* tell the NPE to direct all traffic to rx_qid */ 637bdea1361Sscw #if 0 638bdea1361Sscw for (i = 0; i < 8; i++) 639bdea1361Sscw #else 640bdea1361Sscw printf("%s: remember to fix rx q setup\n", sc->sc_dev.dv_xname); 641bdea1361Sscw for (i = 0; i < 4; i++) 642bdea1361Sscw #endif 643bdea1361Sscw npe_setrxqosentry(sc, i, 0, sc->rx_qid); 644bdea1361Sscw 645bdea1361Sscw sc->tx_qid = npeconfig[unit].tx_qid; 646bdea1361Sscw sc->tx_doneqid = npeconfig[unit].tx_doneqid; 647bdea1361Sscw ixpqmgr_qconfig(sc->tx_qid, NPE_TXBUF, 0, NPE_TXBUF, 0, NULL, sc); 648bdea1361Sscw if (tx_doneqid == -1) { 649bdea1361Sscw ixpqmgr_qconfig(sc->tx_doneqid, NPE_TXBUF, 0, 2, 650bdea1361Sscw IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 651bdea1361Sscw tx_doneqid = sc->tx_doneqid; 652bdea1361Sscw } 653bdea1361Sscw 654bdea1361Sscw KASSERT(npes[npeconfig[unit].npeid] == NULL); 655bdea1361Sscw npes[npeconfig[unit].npeid] = sc; 656bdea1361Sscw 657bdea1361Sscw return 0; 658bdea1361Sscw } 659bdea1361Sscw 660bdea1361Sscw #if 0 661bdea1361Sscw static void 662bdea1361Sscw npe_deactivate(struct npe_softc *sc); 663bdea1361Sscw { 664bdea1361Sscw int unit = sc->sc_unit; 665bdea1361Sscw 666bdea1361Sscw npes[npeconfig[unit].npeid] = NULL; 667bdea1361Sscw 668bdea1361Sscw /* XXX disable q's */ 669bdea1361Sscw if (sc->sc_npe != NULL) 670bdea1361Sscw ixpnpe_stop(sc->sc_npe); 671bdea1361Sscw if (sc->sc_stats != NULL) { 672bdea1361Sscw bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 673bdea1361Sscw bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 674bdea1361Sscw sc->sc_stats_map); 675bdea1361Sscw bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map); 676bdea1361Sscw } 677bdea1361Sscw if (sc->sc_stats_tag != NULL) 678bdea1361Sscw bus_dma_tag_destroy(sc->sc_stats_tag); 679bdea1361Sscw npe_dma_destroy(sc, &sc->txdma); 680bdea1361Sscw npe_dma_destroy(sc, &sc->rxdma); 681bdea1361Sscw bus_generic_detach(sc->sc_dev); 682bdea1361Sscw if (sc->sc_mii) 683bdea1361Sscw device_delete_child(sc->sc_dev, sc->sc_mii); 684bdea1361Sscw #if 0 685bdea1361Sscw /* XXX sc_ioh and sc_miih */ 686bdea1361Sscw if (sc->mem_res) 687bdea1361Sscw bus_release_resource(dev, SYS_RES_IOPORT, 688bdea1361Sscw rman_get_rid(sc->mem_res), sc->mem_res); 689bdea1361Sscw sc->mem_res = 0; 690bdea1361Sscw #endif 691bdea1361Sscw } 692bdea1361Sscw #endif 693bdea1361Sscw 694bdea1361Sscw /* 695bdea1361Sscw * Notify the world which media we're using. 696bdea1361Sscw */ 697bdea1361Sscw static void 698bdea1361Sscw npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 699bdea1361Sscw { 700bdea1361Sscw struct npe_softc *sc = ifp->if_softc; 701bdea1361Sscw 702bdea1361Sscw mii_pollstat(&sc->sc_mii); 703bdea1361Sscw 704bdea1361Sscw ifmr->ifm_active = sc->sc_mii.mii_media_active; 705bdea1361Sscw ifmr->ifm_status = sc->sc_mii.mii_media_status; 706bdea1361Sscw } 707bdea1361Sscw 708bdea1361Sscw static void 709bdea1361Sscw npe_addstats(struct npe_softc *sc) 710bdea1361Sscw { 711bdea1361Sscw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 712bdea1361Sscw struct npestats *ns = sc->sc_stats; 713bdea1361Sscw 714bdea1361Sscw ifp->if_oerrors += 715bdea1361Sscw be32toh(ns->dot3StatsInternalMacTransmitErrors) 716bdea1361Sscw + be32toh(ns->dot3StatsCarrierSenseErrors) 717bdea1361Sscw + be32toh(ns->TxVLANIdFilterDiscards) 718bdea1361Sscw ; 719bdea1361Sscw ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 720bdea1361Sscw + be32toh(ns->dot3StatsInternalMacReceiveErrors) 721bdea1361Sscw + be32toh(ns->RxOverrunDiscards) 722bdea1361Sscw + be32toh(ns->RxUnderflowEntryDiscards) 723bdea1361Sscw ; 724bdea1361Sscw ifp->if_collisions += 725bdea1361Sscw be32toh(ns->dot3StatsSingleCollisionFrames) 726bdea1361Sscw + be32toh(ns->dot3StatsMultipleCollisionFrames) 727bdea1361Sscw ; 728bdea1361Sscw } 729bdea1361Sscw 730bdea1361Sscw static void 731bdea1361Sscw npe_tick(void *xsc) 732bdea1361Sscw { 733bdea1361Sscw #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 734bdea1361Sscw struct npe_softc *sc = xsc; 735bdea1361Sscw uint32_t msg[2]; 736bdea1361Sscw 737bdea1361Sscw /* 738bdea1361Sscw * NB: to avoid sleeping with the softc lock held we 739bdea1361Sscw * split the NPE msg processing into two parts. The 740bdea1361Sscw * request for statistics is sent w/o waiting for a 741bdea1361Sscw * reply and then on the next tick we retrieve the 742bdea1361Sscw * results. This works because npe_tick is the only 743bdea1361Sscw * code that talks via the mailbox's (except at setup). 744bdea1361Sscw * This likely can be handled better. 745bdea1361Sscw */ 746bdea1361Sscw if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 747bdea1361Sscw bus_dmamap_sync(sc->sc_dt, sc->sc_stats_map, 0, 748bdea1361Sscw sizeof(struct npestats), BUS_DMASYNC_POSTREAD); 749bdea1361Sscw npe_addstats(sc); 750bdea1361Sscw } 751bdea1361Sscw npe_updatestats(sc); 752bdea1361Sscw mii_tick(&sc->sc_mii); 753bdea1361Sscw 754bdea1361Sscw /* schedule next poll */ 755bdea1361Sscw callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 756bdea1361Sscw #undef ACK 757bdea1361Sscw } 758bdea1361Sscw 759bdea1361Sscw static void 7606bc0c582Smatt npe_setmac(struct npe_softc *sc, const u_char *eaddr) 761bdea1361Sscw { 7623589a8fdSmsaitoh 763bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 764bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 765bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 766bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 767bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 768bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 769bdea1361Sscw } 770bdea1361Sscw 771bdea1361Sscw static void 7723589a8fdSmsaitoh npe_getmac(struct npe_softc *sc) 773bdea1361Sscw { 7743589a8fdSmsaitoh uint8_t *eaddr = sc->sc_enaddr; 7753589a8fdSmsaitoh 7763589a8fdSmsaitoh if (npe_getmac_md != NULL) { 7773589a8fdSmsaitoh (*npe_getmac_md)(sc->sc_dev.dv_unit, eaddr); 7783589a8fdSmsaitoh } else { 7793589a8fdSmsaitoh /* 7803589a8fdSmsaitoh * Some system's unicast address appears to be loaded from 7813589a8fdSmsaitoh * EEPROM on reset 7823589a8fdSmsaitoh */ 783bdea1361Sscw eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 784bdea1361Sscw eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 785bdea1361Sscw eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 786bdea1361Sscw eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 787bdea1361Sscw eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 788bdea1361Sscw eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 789bdea1361Sscw } 7903589a8fdSmsaitoh } 791bdea1361Sscw 792bdea1361Sscw struct txdone { 793bdea1361Sscw struct npebuf *head; 794bdea1361Sscw struct npebuf **tail; 795bdea1361Sscw int count; 796bdea1361Sscw }; 797bdea1361Sscw 798bdea1361Sscw static __inline void 799bdea1361Sscw npe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 800bdea1361Sscw { 801bdea1361Sscw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 802bdea1361Sscw 803bdea1361Sscw *td->tail = sc->tx_free; 804bdea1361Sscw sc->tx_free = td->head; 805bdea1361Sscw /* 806bdea1361Sscw * We're no longer busy, so clear the busy flag and call the 807bdea1361Sscw * start routine to xmit more packets. 808bdea1361Sscw */ 809bdea1361Sscw ifp->if_opackets += td->count; 810bdea1361Sscw ifp->if_flags &= ~IFF_OACTIVE; 811bdea1361Sscw ifp->if_timer = 0; 812bdea1361Sscw npestart(ifp); 813bdea1361Sscw } 814bdea1361Sscw 815bdea1361Sscw /* 816bdea1361Sscw * Q manager callback on tx done queue. Reap mbufs 817bdea1361Sscw * and return tx buffers to the free list. Finally 818bdea1361Sscw * restart output. Note the microcode has only one 819bdea1361Sscw * txdone q wired into it so we must use the NPE ID 820bdea1361Sscw * returned with each npehwbuf to decide where to 821bdea1361Sscw * send buffers. 822bdea1361Sscw */ 823bdea1361Sscw static void 824bdea1361Sscw npe_txdone(int qid, void *arg) 825bdea1361Sscw { 826bdea1361Sscw #define P2V(a, dma) \ 827bdea1361Sscw &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 828bdea1361Sscw struct npe_softc *sc; 829bdea1361Sscw struct npebuf *npe; 830bdea1361Sscw struct txdone *td, q[NPE_MAX]; 831bdea1361Sscw uint32_t entry; 832bdea1361Sscw 833bdea1361Sscw /* XXX no NPE-A support */ 834bdea1361Sscw q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 835bdea1361Sscw q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 836bdea1361Sscw /* XXX max # at a time? */ 837bdea1361Sscw while (ixpqmgr_qread(qid, &entry) == 0) { 838bdea1361Sscw sc = npes[NPE_QM_Q_NPE(entry)]; 839bdea1361Sscw DPRINTF(sc, "%s: entry 0x%x NPE %u port %u\n", 840bdea1361Sscw __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 841507aaf9eSmsaitoh #if NRND > 0 842507aaf9eSmsaitoh if (RND_ENABLED(&sc->rnd_source)) 843507aaf9eSmsaitoh rnd_add_uint32(&sc->rnd_source, entry); 844507aaf9eSmsaitoh #endif 845bdea1361Sscw 846bdea1361Sscw npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 847bdea1361Sscw m_freem(npe->ix_m); 848bdea1361Sscw npe->ix_m = NULL; 849bdea1361Sscw 850bdea1361Sscw td = &q[NPE_QM_Q_NPE(entry)]; 851bdea1361Sscw *td->tail = npe; 852bdea1361Sscw td->tail = &npe->ix_next; 853bdea1361Sscw td->count++; 854bdea1361Sscw } 855bdea1361Sscw 856bdea1361Sscw if (q[NPE_B].count) 857bdea1361Sscw npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 858bdea1361Sscw if (q[NPE_C].count) 859bdea1361Sscw npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 860bdea1361Sscw #undef P2V 861bdea1361Sscw } 862bdea1361Sscw 863bdea1361Sscw static __inline struct mbuf * 864bdea1361Sscw npe_getcl(void) 865bdea1361Sscw { 866bdea1361Sscw struct mbuf *m; 867bdea1361Sscw 868bdea1361Sscw MGETHDR(m, M_DONTWAIT, MT_DATA); 869bdea1361Sscw if (m != NULL) { 870bdea1361Sscw MCLGET(m, M_DONTWAIT); 871bdea1361Sscw if ((m->m_flags & M_EXT) == 0) { 872bdea1361Sscw m_freem(m); 873bdea1361Sscw m = NULL; 874bdea1361Sscw } 875bdea1361Sscw } 876bdea1361Sscw return (m); 877bdea1361Sscw } 878bdea1361Sscw 879bdea1361Sscw static int 880bdea1361Sscw npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 881bdea1361Sscw { 882bdea1361Sscw struct npehwbuf *hw; 883bdea1361Sscw int error; 884bdea1361Sscw 885bdea1361Sscw if (m == NULL) { 886bdea1361Sscw m = npe_getcl(); 887bdea1361Sscw if (m == NULL) 888bdea1361Sscw return ENOBUFS; 889bdea1361Sscw } 8903589a8fdSmsaitoh KASSERT(m->m_ext.ext_size >= (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 8913589a8fdSmsaitoh m->m_pkthdr.len = m->m_len = NPE_FRAME_SIZE_DEFAULT; 892bdea1361Sscw /* backload payload and align ip hdr */ 8933589a8fdSmsaitoh m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size 8943589a8fdSmsaitoh - (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 895bdea1361Sscw error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 896bdea1361Sscw BUS_DMA_READ|BUS_DMA_NOWAIT); 897bdea1361Sscw if (error != 0) { 898bdea1361Sscw m_freem(m); 899bdea1361Sscw return error; 900bdea1361Sscw } 901bdea1361Sscw hw = npe->ix_hw; 902bdea1361Sscw hw->ix_ne[0].data = htobe32(npe->ix_map->dm_segs[0].ds_addr); 903bdea1361Sscw /* NB: NPE requires length be a multiple of 64 */ 904bdea1361Sscw /* NB: buffer length is shifted in word */ 905bdea1361Sscw hw->ix_ne[0].len = htobe32(npe->ix_map->dm_segs[0].ds_len << 16); 906bdea1361Sscw hw->ix_ne[0].next = 0; 907bdea1361Sscw npe->ix_m = m; 908bdea1361Sscw /* Flush the memory in the mbuf */ 909bdea1361Sscw bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, npe->ix_map->dm_mapsize, 910bdea1361Sscw BUS_DMASYNC_PREREAD); 911bdea1361Sscw return 0; 912bdea1361Sscw } 913bdea1361Sscw 914bdea1361Sscw /* 915bdea1361Sscw * RX q processing for a specific NPE. Claim entries 916bdea1361Sscw * from the hardware queue and pass the frames up the 917bdea1361Sscw * stack. Pass the rx buffers to the free list. 918bdea1361Sscw */ 919bdea1361Sscw static void 920bdea1361Sscw npe_rxdone(int qid, void *arg) 921bdea1361Sscw { 922bdea1361Sscw #define P2V(a, dma) \ 923bdea1361Sscw &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 924bdea1361Sscw struct npe_softc *sc = arg; 925bdea1361Sscw struct npedma *dma = &sc->rxdma; 926bdea1361Sscw uint32_t entry; 927bdea1361Sscw 928bdea1361Sscw while (ixpqmgr_qread(qid, &entry) == 0) { 929bdea1361Sscw struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 930bdea1361Sscw struct mbuf *m; 931bdea1361Sscw 932bdea1361Sscw DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 933bdea1361Sscw __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 934507aaf9eSmsaitoh #if NRND > 0 935507aaf9eSmsaitoh if (RND_ENABLED(&sc->rnd_source)) 936507aaf9eSmsaitoh rnd_add_uint32(&sc->rnd_source, entry); 937507aaf9eSmsaitoh #endif 938bdea1361Sscw /* 939bdea1361Sscw * Allocate a new mbuf to replenish the rx buffer. 940bdea1361Sscw * If doing so fails we drop the rx'd frame so we 941bdea1361Sscw * can reuse the previous mbuf. When we're able to 942bdea1361Sscw * allocate a new mbuf dispatch the mbuf w/ rx'd 943bdea1361Sscw * data up the stack and replace it with the newly 944bdea1361Sscw * allocated one. 945bdea1361Sscw */ 946bdea1361Sscw m = npe_getcl(); 947bdea1361Sscw if (m != NULL) { 948bdea1361Sscw struct mbuf *mrx = npe->ix_m; 949bdea1361Sscw struct npehwbuf *hw = npe->ix_hw; 950bdea1361Sscw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 951bdea1361Sscw 952bdea1361Sscw /* Flush mbuf memory for rx'd data */ 953bdea1361Sscw bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 954bdea1361Sscw npe->ix_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 955bdea1361Sscw 956bdea1361Sscw /* XXX flush hw buffer; works now 'cuz coherent */ 957bdea1361Sscw /* set m_len etc. per rx frame size */ 958bdea1361Sscw mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 959bdea1361Sscw mrx->m_pkthdr.len = mrx->m_len; 960bdea1361Sscw mrx->m_pkthdr.rcvif = ifp; 9613589a8fdSmsaitoh /* Don't add M_HASFCS. See below */ 9623589a8fdSmsaitoh 9633589a8fdSmsaitoh #if 1 9643589a8fdSmsaitoh if (mrx->m_pkthdr.len < sizeof(struct ether_header)) { 9653589a8fdSmsaitoh log(LOG_INFO, "%s: too short frame (len=%d)\n", 9663589a8fdSmsaitoh sc->sc_dev.dv_xname, mrx->m_pkthdr.len); 9673589a8fdSmsaitoh /* Back out "newly allocated" mbuf. */ 9683589a8fdSmsaitoh m_freem(m); 9693589a8fdSmsaitoh ifp->if_ierrors++; 9703589a8fdSmsaitoh goto fail; 9713589a8fdSmsaitoh } 9723589a8fdSmsaitoh if ((ifp->if_flags & IFF_PROMISC) == 0) { 9733589a8fdSmsaitoh struct ether_header *eh; 9743589a8fdSmsaitoh 9753589a8fdSmsaitoh /* 9763589a8fdSmsaitoh * Workaround for "Non-Intel XScale Technology 9773589a8fdSmsaitoh * Eratta" No. 29. AA:BB:CC:DD:EE:xF's packet 9783589a8fdSmsaitoh * matches the filter (both unicast and 9793589a8fdSmsaitoh * multicast). 9803589a8fdSmsaitoh */ 9813589a8fdSmsaitoh eh = mtod(mrx, struct ether_header *); 9823589a8fdSmsaitoh if (ETHER_IS_MULTICAST(eh->ether_dhost) == 0) { 9833589a8fdSmsaitoh /* unicast */ 9843589a8fdSmsaitoh 9853589a8fdSmsaitoh if (sc->sc_enaddr[5] != eh->ether_dhost[5]) { 9863589a8fdSmsaitoh /* discard it */ 9873589a8fdSmsaitoh #if 0 9883589a8fdSmsaitoh printf("discard it\n"); 9893589a8fdSmsaitoh #endif 9903589a8fdSmsaitoh /* 9913589a8fdSmsaitoh * Back out "newly allocated" 9923589a8fdSmsaitoh * mbuf. 9933589a8fdSmsaitoh */ 9943589a8fdSmsaitoh m_freem(m); 9953589a8fdSmsaitoh goto fail; 9963589a8fdSmsaitoh } 9973589a8fdSmsaitoh } else if (memcmp(eh->ether_dhost, 9983589a8fdSmsaitoh etherbroadcastaddr, 6) == 0) { 9993589a8fdSmsaitoh /* Always accept broadcast packet*/ 10003589a8fdSmsaitoh } else { 10013589a8fdSmsaitoh struct ethercom *ec = &sc->sc_ethercom; 10023589a8fdSmsaitoh struct ether_multi *enm; 10033589a8fdSmsaitoh struct ether_multistep step; 10043589a8fdSmsaitoh int match = 0; 10053589a8fdSmsaitoh 10063589a8fdSmsaitoh /* multicast */ 10073589a8fdSmsaitoh 10083589a8fdSmsaitoh ETHER_FIRST_MULTI(step, ec, enm); 10093589a8fdSmsaitoh while (enm != NULL) { 10103589a8fdSmsaitoh uint64_t lowint, highint, dest; 10113589a8fdSmsaitoh 10123589a8fdSmsaitoh lowint = MAC2UINT64(enm->enm_addrlo); 10133589a8fdSmsaitoh highint = MAC2UINT64(enm->enm_addrhi); 10143589a8fdSmsaitoh dest = MAC2UINT64(eh->ether_dhost); 10153589a8fdSmsaitoh #if 0 10163589a8fdSmsaitoh printf("%llx\n", lowint); 10173589a8fdSmsaitoh printf("%llx\n", dest); 10183589a8fdSmsaitoh printf("%llx\n", highint); 10193589a8fdSmsaitoh #endif 10203589a8fdSmsaitoh if ((lowint <= dest) && (dest <= highint)) { 10213589a8fdSmsaitoh match = 1; 10223589a8fdSmsaitoh break; 10233589a8fdSmsaitoh } 10243589a8fdSmsaitoh ETHER_NEXT_MULTI(step, enm); 10253589a8fdSmsaitoh } 10263589a8fdSmsaitoh if (match == 0) { 10273589a8fdSmsaitoh /* discard it */ 10283589a8fdSmsaitoh #if 0 10293589a8fdSmsaitoh printf("discard it(M)\n"); 10303589a8fdSmsaitoh #endif 10313589a8fdSmsaitoh /* 10323589a8fdSmsaitoh * Back out "newly allocated" 10333589a8fdSmsaitoh * mbuf. 10343589a8fdSmsaitoh */ 10353589a8fdSmsaitoh m_freem(m); 10363589a8fdSmsaitoh goto fail; 10373589a8fdSmsaitoh } 10383589a8fdSmsaitoh } 10393589a8fdSmsaitoh } 10403589a8fdSmsaitoh if (mrx->m_pkthdr.len > NPE_FRAME_SIZE_DEFAULT) { 10413589a8fdSmsaitoh log(LOG_INFO, "%s: oversized frame (len=%d)\n", 10423589a8fdSmsaitoh sc->sc_dev.dv_xname, mrx->m_pkthdr.len); 10433589a8fdSmsaitoh /* Back out "newly allocated" mbuf. */ 10443589a8fdSmsaitoh m_freem(m); 10453589a8fdSmsaitoh ifp->if_ierrors++; 10463589a8fdSmsaitoh goto fail; 10473589a8fdSmsaitoh } 10483589a8fdSmsaitoh #endif 10493589a8fdSmsaitoh 10503589a8fdSmsaitoh /* 10513589a8fdSmsaitoh * Trim FCS! 10523589a8fdSmsaitoh * NPE always adds the FCS by this driver's setting, 10533589a8fdSmsaitoh * so we always trim it here and not add M_HASFCS. 10543589a8fdSmsaitoh */ 10553589a8fdSmsaitoh m_adj(mrx, -ETHER_CRC_LEN); 1056bdea1361Sscw 1057bdea1361Sscw ifp->if_ipackets++; 10588586a845Smsaitoh /* 10598586a845Smsaitoh * Tap off here if there is a bpf listener. 10608586a845Smsaitoh */ 106158e86755Sjoerg bpf_mtap(ifp, mrx); 1062bdea1361Sscw ifp->if_input(ifp, mrx); 1063bdea1361Sscw } else { 10643589a8fdSmsaitoh fail: 1065bdea1361Sscw /* discard frame and re-use mbuf */ 1066bdea1361Sscw m = npe->ix_m; 1067bdea1361Sscw } 1068bdea1361Sscw if (npe_rxbuf_init(sc, npe, m) == 0) { 1069bdea1361Sscw /* return npe buf to rx free list */ 1070bdea1361Sscw ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1071bdea1361Sscw } else { 1072bdea1361Sscw /* XXX should not happen */ 1073bdea1361Sscw } 1074bdea1361Sscw } 1075bdea1361Sscw #undef P2V 1076bdea1361Sscw } 1077bdea1361Sscw 1078bdea1361Sscw static void 1079bdea1361Sscw npe_startxmit(struct npe_softc *sc) 1080bdea1361Sscw { 1081bdea1361Sscw struct npedma *dma = &sc->txdma; 1082bdea1361Sscw int i; 1083bdea1361Sscw 1084bdea1361Sscw sc->tx_free = NULL; 1085bdea1361Sscw for (i = 0; i < dma->nbuf; i++) { 1086bdea1361Sscw struct npebuf *npe = &dma->buf[i]; 1087bdea1361Sscw if (npe->ix_m != NULL) { 1088bdea1361Sscw /* NB: should not happen */ 1089bdea1361Sscw printf("%s: %s: free mbuf at entry %u\n", 1090bdea1361Sscw sc->sc_dev.dv_xname, __func__, i); 1091bdea1361Sscw m_freem(npe->ix_m); 1092bdea1361Sscw } 1093bdea1361Sscw npe->ix_m = NULL; 1094bdea1361Sscw npe->ix_next = sc->tx_free; 1095bdea1361Sscw sc->tx_free = npe; 1096bdea1361Sscw } 1097bdea1361Sscw } 1098bdea1361Sscw 1099bdea1361Sscw static void 1100bdea1361Sscw npe_startrecv(struct npe_softc *sc) 1101bdea1361Sscw { 1102bdea1361Sscw struct npedma *dma = &sc->rxdma; 1103bdea1361Sscw struct npebuf *npe; 1104bdea1361Sscw int i; 1105bdea1361Sscw 1106bdea1361Sscw for (i = 0; i < dma->nbuf; i++) { 1107bdea1361Sscw npe = &dma->buf[i]; 1108bdea1361Sscw npe_rxbuf_init(sc, npe, npe->ix_m); 1109bdea1361Sscw /* set npe buf on rx free list */ 1110bdea1361Sscw ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1111bdea1361Sscw } 1112bdea1361Sscw } 1113bdea1361Sscw 1114bdea1361Sscw static void 1115816cf5b8Smsaitoh npeinit_macreg(struct npe_softc *sc) 1116bdea1361Sscw { 1117bdea1361Sscw 1118bdea1361Sscw /* 1119bdea1361Sscw * Reset MAC core. 1120bdea1361Sscw */ 1121bdea1361Sscw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1122bdea1361Sscw DELAY(NPE_MAC_RESET_DELAY); 1123bdea1361Sscw /* configure MAC to generate MDC clock */ 1124bdea1361Sscw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1125bdea1361Sscw 1126bdea1361Sscw /* disable transmitter and reciver in the MAC */ 1127bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL1, 1128bdea1361Sscw RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1129bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL1, 1130bdea1361Sscw RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1131bdea1361Sscw 1132bdea1361Sscw /* 1133bdea1361Sscw * Set the MAC core registers. 1134bdea1361Sscw */ 1135bdea1361Sscw WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1136bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1137bdea1361Sscw WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1138bdea1361Sscw /* thresholds determined by NPE firmware FS */ 1139bdea1361Sscw WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1140bdea1361Sscw WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1141a69b43feSmsaitoh WR4(sc, NPE_MAC_BUF_SIZE_TX, NPE_MAC_BUF_SIZE_TX_DEFAULT); 1142a69b43feSmsaitoh /* tx fifo threshold (bytes) */ 1143bdea1361Sscw WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1144bdea1361Sscw WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1145bdea1361Sscw WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1146bdea1361Sscw WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1147a69b43feSmsaitoh WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT); 1148a69b43feSmsaitoh /* assumes MII mode */ 1149bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL1, 1150bdea1361Sscw NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1151bdea1361Sscw | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1152bdea1361Sscw | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1153bdea1361Sscw | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1154bdea1361Sscw /* XXX pad strip? */ 1155bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL1, 1156bdea1361Sscw NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */ 1157bdea1361Sscw | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */ 1158bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1159816cf5b8Smsaitoh } 1160bdea1361Sscw 1161227ae4c9Smsaitoh static void 1162227ae4c9Smsaitoh npeinit_resetcb(void *xsc) 1163227ae4c9Smsaitoh { 1164227ae4c9Smsaitoh struct npe_softc *sc = xsc; 1165227ae4c9Smsaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1166227ae4c9Smsaitoh uint32_t msg[2]; 1167227ae4c9Smsaitoh 1168227ae4c9Smsaitoh ifp->if_oerrors++; 1169227ae4c9Smsaitoh npeinit_locked(sc); 1170227ae4c9Smsaitoh 1171227ae4c9Smsaitoh msg[0] = NPE_NOTIFYMACRECOVERYDONE << NPE_MAC_MSGID_SHL 1172227ae4c9Smsaitoh | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL); 1173227ae4c9Smsaitoh msg[1] = 0; 1174227ae4c9Smsaitoh ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1175227ae4c9Smsaitoh } 1176227ae4c9Smsaitoh 1177816cf5b8Smsaitoh /* 1178816cf5b8Smsaitoh * Reset and initialize the chip 1179816cf5b8Smsaitoh */ 1180816cf5b8Smsaitoh static void 1181816cf5b8Smsaitoh npeinit_locked(void *xsc) 1182816cf5b8Smsaitoh { 1183816cf5b8Smsaitoh struct npe_softc *sc = xsc; 1184816cf5b8Smsaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1185816cf5b8Smsaitoh 1186816cf5b8Smsaitoh /* Cancel any pending I/O. */ 1187816cf5b8Smsaitoh npestop(ifp, 0); 1188816cf5b8Smsaitoh 1189816cf5b8Smsaitoh /* Reset the chip to a known state. */ 1190816cf5b8Smsaitoh npeinit_macreg(sc); 11916bc0c582Smatt npe_setmac(sc, CLLADDR(ifp->if_sadl)); 1192273cfb27Smsaitoh ether_mediachange(ifp); 1193bdea1361Sscw npe_setmcast(sc); 1194bdea1361Sscw 1195bdea1361Sscw npe_startxmit(sc); 1196bdea1361Sscw npe_startrecv(sc); 1197bdea1361Sscw 1198bdea1361Sscw ifp->if_flags |= IFF_RUNNING; 1199bdea1361Sscw ifp->if_flags &= ~IFF_OACTIVE; 1200bdea1361Sscw ifp->if_timer = 0; /* just in case */ 1201bdea1361Sscw 1202bdea1361Sscw /* enable transmitter and reciver in the MAC */ 1203bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL1, 1204bdea1361Sscw RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1205bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL1, 1206bdea1361Sscw RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1207bdea1361Sscw 1208bdea1361Sscw callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 1209bdea1361Sscw } 1210bdea1361Sscw 1211bdea1361Sscw static int 1212bdea1361Sscw npeinit(struct ifnet *ifp) 1213bdea1361Sscw { 1214bdea1361Sscw struct npe_softc *sc = ifp->if_softc; 1215bdea1361Sscw int s; 1216bdea1361Sscw 1217bdea1361Sscw s = splnet(); 1218bdea1361Sscw npeinit_locked(sc); 1219bdea1361Sscw splx(s); 1220bdea1361Sscw 1221bdea1361Sscw return (0); 1222bdea1361Sscw } 1223bdea1361Sscw 1224bdea1361Sscw /* 1225bdea1361Sscw * Defragment an mbuf chain, returning at most maxfrags separate 1226bdea1361Sscw * mbufs+clusters. If this is not possible NULL is returned and 1227bdea1361Sscw * the original mbuf chain is left in it's present (potentially 1228bdea1361Sscw * modified) state. We use two techniques: collapsing consecutive 1229bdea1361Sscw * mbufs and replacing consecutive mbufs by a cluster. 1230bdea1361Sscw */ 1231bdea1361Sscw static __inline struct mbuf * 1232bdea1361Sscw npe_defrag(struct mbuf *m0) 1233bdea1361Sscw { 1234bdea1361Sscw struct mbuf *m; 1235bdea1361Sscw 1236bdea1361Sscw MGETHDR(m, M_DONTWAIT, MT_DATA); 1237bdea1361Sscw if (m == NULL) 1238bdea1361Sscw return (NULL); 1239bdea1361Sscw M_COPY_PKTHDR(m, m0); 1240bdea1361Sscw 1241bdea1361Sscw if ((m->m_len = m0->m_pkthdr.len) > MHLEN) { 1242bdea1361Sscw MCLGET(m, M_DONTWAIT); 1243bdea1361Sscw if ((m->m_flags & M_EXT) == 0) { 1244bdea1361Sscw m_freem(m); 1245bdea1361Sscw return (NULL); 1246bdea1361Sscw } 1247bdea1361Sscw } 1248bdea1361Sscw 124953524e44Schristos m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1250bdea1361Sscw m_freem(m0); 1251bdea1361Sscw 1252bdea1361Sscw return (m); 1253bdea1361Sscw } 1254bdea1361Sscw 1255bdea1361Sscw /* 1256bdea1361Sscw * Dequeue packets and place on the h/w transmit queue. 1257bdea1361Sscw */ 1258bdea1361Sscw static void 1259bdea1361Sscw npestart(struct ifnet *ifp) 1260bdea1361Sscw { 1261bdea1361Sscw struct npe_softc *sc = ifp->if_softc; 1262bdea1361Sscw struct npebuf *npe; 1263bdea1361Sscw struct npehwbuf *hw; 1264bdea1361Sscw struct mbuf *m, *n; 1265bdea1361Sscw bus_dma_segment_t *segs; 1266bdea1361Sscw int nseg, len, error, i; 1267bdea1361Sscw uint32_t next; 1268bdea1361Sscw 1269816cf5b8Smsaitoh if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1270bdea1361Sscw return; 1271bdea1361Sscw 1272bdea1361Sscw while (sc->tx_free != NULL) { 1273bdea1361Sscw IFQ_DEQUEUE(&ifp->if_snd, m); 1274816cf5b8Smsaitoh if (m == NULL) 1275816cf5b8Smsaitoh break; 1276bdea1361Sscw npe = sc->tx_free; 1277bdea1361Sscw error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 1278bdea1361Sscw BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1279bdea1361Sscw if (error == EFBIG) { 1280bdea1361Sscw n = npe_defrag(m); 1281bdea1361Sscw if (n == NULL) { 1282bdea1361Sscw printf("%s: %s: too many fragments\n", 1283bdea1361Sscw sc->sc_dev.dv_xname, __func__); 1284bdea1361Sscw m_freem(m); 1285bdea1361Sscw return; /* XXX? */ 1286bdea1361Sscw } 1287bdea1361Sscw m = n; 1288bdea1361Sscw error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, 1289bdea1361Sscw m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1290bdea1361Sscw } 1291bdea1361Sscw if (error != 0) { 1292bdea1361Sscw printf("%s: %s: error %u\n", 1293bdea1361Sscw sc->sc_dev.dv_xname, __func__, error); 1294bdea1361Sscw m_freem(m); 1295bdea1361Sscw return; /* XXX? */ 1296bdea1361Sscw } 1297bdea1361Sscw sc->tx_free = npe->ix_next; 1298bdea1361Sscw 1299bdea1361Sscw /* 1300bdea1361Sscw * Tap off here if there is a bpf listener. 1301bdea1361Sscw */ 130258e86755Sjoerg bpf_mtap(ifp, m); 1303bdea1361Sscw 1304bdea1361Sscw bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 1305bdea1361Sscw npe->ix_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1306bdea1361Sscw 1307bdea1361Sscw npe->ix_m = m; 1308bdea1361Sscw hw = npe->ix_hw; 1309bdea1361Sscw len = m->m_pkthdr.len; 1310bdea1361Sscw nseg = npe->ix_map->dm_nsegs; 1311bdea1361Sscw segs = npe->ix_map->dm_segs; 1312bdea1361Sscw next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1313bdea1361Sscw for (i = 0; i < nseg; i++) { 1314bdea1361Sscw hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1315bdea1361Sscw hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1316bdea1361Sscw hw->ix_ne[i].next = htobe32(next); 1317bdea1361Sscw 1318bdea1361Sscw len = 0; /* zero for segments > 1 */ 1319bdea1361Sscw next += sizeof(hw->ix_ne[0]); 1320bdea1361Sscw } 1321bdea1361Sscw hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1322bdea1361Sscw /* XXX flush descriptor instead of using uncached memory */ 1323bdea1361Sscw 1324bdea1361Sscw DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1325bdea1361Sscw __func__, sc->tx_qid, npe->ix_neaddr, 1326bdea1361Sscw hw->ix_ne[0].data, hw->ix_ne[0].len); 1327bdea1361Sscw /* stick it on the tx q */ 1328bdea1361Sscw /* XXX add vlan priority */ 1329bdea1361Sscw ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1330bdea1361Sscw 1331bdea1361Sscw ifp->if_timer = 5; 1332bdea1361Sscw } 1333bdea1361Sscw if (sc->tx_free == NULL) 1334bdea1361Sscw ifp->if_flags |= IFF_OACTIVE; 1335bdea1361Sscw } 1336bdea1361Sscw 1337bdea1361Sscw static void 1338bdea1361Sscw npe_stopxmit(struct npe_softc *sc) 1339bdea1361Sscw { 1340bdea1361Sscw struct npedma *dma = &sc->txdma; 1341bdea1361Sscw int i; 1342bdea1361Sscw 1343bdea1361Sscw /* XXX qmgr */ 1344bdea1361Sscw for (i = 0; i < dma->nbuf; i++) { 1345bdea1361Sscw struct npebuf *npe = &dma->buf[i]; 1346bdea1361Sscw 1347bdea1361Sscw if (npe->ix_m != NULL) { 1348bdea1361Sscw bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1349bdea1361Sscw m_freem(npe->ix_m); 1350bdea1361Sscw npe->ix_m = NULL; 1351bdea1361Sscw } 1352bdea1361Sscw } 1353bdea1361Sscw } 1354bdea1361Sscw 1355bdea1361Sscw static void 1356bdea1361Sscw npe_stoprecv(struct npe_softc *sc) 1357bdea1361Sscw { 1358bdea1361Sscw struct npedma *dma = &sc->rxdma; 1359bdea1361Sscw int i; 1360bdea1361Sscw 1361bdea1361Sscw /* XXX qmgr */ 1362bdea1361Sscw for (i = 0; i < dma->nbuf; i++) { 1363bdea1361Sscw struct npebuf *npe = &dma->buf[i]; 1364bdea1361Sscw 1365bdea1361Sscw if (npe->ix_m != NULL) { 1366bdea1361Sscw bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1367bdea1361Sscw m_freem(npe->ix_m); 1368bdea1361Sscw npe->ix_m = NULL; 1369bdea1361Sscw } 1370bdea1361Sscw } 1371bdea1361Sscw } 1372bdea1361Sscw 1373bdea1361Sscw /* 1374bdea1361Sscw * Turn off interrupts, and stop the nic. 1375bdea1361Sscw */ 1376bdea1361Sscw void 1377bdea1361Sscw npestop(struct ifnet *ifp, int disable) 1378bdea1361Sscw { 1379bdea1361Sscw struct npe_softc *sc = ifp->if_softc; 1380bdea1361Sscw 1381bdea1361Sscw /* disable transmitter and reciver in the MAC */ 1382bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL1, 1383bdea1361Sscw RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1384bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL1, 1385bdea1361Sscw RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1386bdea1361Sscw 1387bdea1361Sscw callout_stop(&sc->sc_tick_ch); 1388bdea1361Sscw 1389bdea1361Sscw npe_stopxmit(sc); 1390bdea1361Sscw npe_stoprecv(sc); 1391bdea1361Sscw /* XXX go into loopback & drain q's? */ 1392bdea1361Sscw /* XXX but beware of disabling tx above */ 1393bdea1361Sscw 1394bdea1361Sscw /* 1395bdea1361Sscw * The MAC core rx/tx disable may leave the MAC hardware in an 1396bdea1361Sscw * unpredictable state. A hw reset is executed before resetting 1397bdea1361Sscw * all the MAC parameters to a known value. 1398bdea1361Sscw */ 1399bdea1361Sscw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1400bdea1361Sscw DELAY(NPE_MAC_RESET_DELAY); 1401bdea1361Sscw WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1402bdea1361Sscw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1403816cf5b8Smsaitoh 1404816cf5b8Smsaitoh ifp->if_timer = 0; 1405816cf5b8Smsaitoh ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1406bdea1361Sscw } 1407bdea1361Sscw 1408bdea1361Sscw void 1409bdea1361Sscw npewatchdog(struct ifnet *ifp) 1410bdea1361Sscw { 1411bdea1361Sscw struct npe_softc *sc = ifp->if_softc; 1412bdea1361Sscw int s; 1413bdea1361Sscw 1414bdea1361Sscw printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1415bdea1361Sscw s = splnet(); 1416bdea1361Sscw ifp->if_oerrors++; 1417bdea1361Sscw npeinit_locked(sc); 1418bdea1361Sscw splx(s); 1419bdea1361Sscw } 1420bdea1361Sscw 1421bdea1361Sscw static int 142253524e44Schristos npeioctl(struct ifnet *ifp, u_long cmd, void *data) 1423bdea1361Sscw { 1424bdea1361Sscw struct npe_softc *sc = ifp->if_softc; 1425816cf5b8Smsaitoh struct ifreq *ifr = (struct ifreq *) data; 1426bdea1361Sscw int s, error = 0; 1427bdea1361Sscw 1428bdea1361Sscw s = splnet(); 1429bdea1361Sscw 1430816cf5b8Smsaitoh switch (cmd) { 1431816cf5b8Smsaitoh case SIOCSIFMEDIA: 1432816cf5b8Smsaitoh case SIOCGIFMEDIA: 1433816cf5b8Smsaitoh #if 0 /* not yet */ 1434816cf5b8Smsaitoh /* Flow control requires full-duplex mode. */ 1435816cf5b8Smsaitoh if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1436816cf5b8Smsaitoh (ifr->ifr_media & IFM_FDX) == 0) 1437816cf5b8Smsaitoh ifr->ifr_media &= ~IFM_ETH_FMASK; 1438816cf5b8Smsaitoh if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1439816cf5b8Smsaitoh if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1440816cf5b8Smsaitoh /* We can do both TXPAUSE and RXPAUSE. */ 1441816cf5b8Smsaitoh ifr->ifr_media |= 1442816cf5b8Smsaitoh IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1443816cf5b8Smsaitoh } 1444816cf5b8Smsaitoh sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1445816cf5b8Smsaitoh } 1446816cf5b8Smsaitoh #endif 1447816cf5b8Smsaitoh error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1448816cf5b8Smsaitoh break; 1449816cf5b8Smsaitoh case SIOCSIFFLAGS: 1450816cf5b8Smsaitoh if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == IFF_RUNNING) { 1451816cf5b8Smsaitoh /* 1452816cf5b8Smsaitoh * If interface is marked down and it is running, 1453816cf5b8Smsaitoh * then stop and disable it. 1454816cf5b8Smsaitoh */ 1455816cf5b8Smsaitoh (*ifp->if_stop)(ifp, 1); 1456816cf5b8Smsaitoh } else if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == IFF_UP) { 1457816cf5b8Smsaitoh /* 1458816cf5b8Smsaitoh * If interface is marked up and it is stopped, then 1459816cf5b8Smsaitoh * start it. 1460816cf5b8Smsaitoh */ 1461816cf5b8Smsaitoh error = (*ifp->if_init)(ifp); 1462816cf5b8Smsaitoh } else if ((ifp->if_flags & IFF_UP) != 0) { 1463816cf5b8Smsaitoh int diff; 1464816cf5b8Smsaitoh 1465816cf5b8Smsaitoh /* Up (AND RUNNING). */ 1466816cf5b8Smsaitoh 1467816cf5b8Smsaitoh diff = (ifp->if_flags ^ sc->sc_if_flags) 1468816cf5b8Smsaitoh & (IFF_PROMISC|IFF_ALLMULTI); 1469816cf5b8Smsaitoh if ((diff & (IFF_PROMISC|IFF_ALLMULTI)) != 0) { 1470816cf5b8Smsaitoh /* 1471816cf5b8Smsaitoh * If the difference bettween last flag and 1472816cf5b8Smsaitoh * new flag only IFF_PROMISC or IFF_ALLMULTI, 1473816cf5b8Smsaitoh * set multicast filter only (don't reset to 1474816cf5b8Smsaitoh * prevent link down). 1475816cf5b8Smsaitoh */ 1476816cf5b8Smsaitoh npe_setmcast(sc); 1477816cf5b8Smsaitoh } else { 1478816cf5b8Smsaitoh /* 1479816cf5b8Smsaitoh * Reset the interface to pick up changes in 1480816cf5b8Smsaitoh * any other flags that affect the hardware 1481816cf5b8Smsaitoh * state. 1482816cf5b8Smsaitoh */ 1483816cf5b8Smsaitoh error = (*ifp->if_init)(ifp); 1484816cf5b8Smsaitoh } 1485816cf5b8Smsaitoh } 1486816cf5b8Smsaitoh sc->sc_if_flags = ifp->if_flags; 1487816cf5b8Smsaitoh break; 1488816cf5b8Smsaitoh default: 1489bdea1361Sscw error = ether_ioctl(ifp, cmd, data); 1490bdea1361Sscw if (error == ENETRESET) { 1491816cf5b8Smsaitoh /* 1492816cf5b8Smsaitoh * Multicast list has changed; set the hardware filter 1493816cf5b8Smsaitoh * accordingly. 1494816cf5b8Smsaitoh */ 1495816cf5b8Smsaitoh npe_setmcast(sc); 1496bdea1361Sscw error = 0; 1497bdea1361Sscw } 1498816cf5b8Smsaitoh } 1499bdea1361Sscw 1500bdea1361Sscw npestart(ifp); 1501bdea1361Sscw 1502bdea1361Sscw splx(s); 1503bdea1361Sscw return error; 1504bdea1361Sscw } 1505bdea1361Sscw 1506bdea1361Sscw /* 1507bdea1361Sscw * Setup a traffic class -> rx queue mapping. 1508bdea1361Sscw */ 1509bdea1361Sscw static int 1510bdea1361Sscw npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1511bdea1361Sscw { 1512bdea1361Sscw int npeid = npeconfig[sc->sc_unit].npeid; 1513bdea1361Sscw uint32_t msg[2]; 1514bdea1361Sscw 1515273cfb27Smsaitoh msg[0] = (NPE_SETRXQOSENTRY << NPE_MAC_MSGID_SHL) | (npeid << 20) 1516273cfb27Smsaitoh | classix; 1517bdea1361Sscw msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1518bdea1361Sscw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1519bdea1361Sscw } 1520bdea1361Sscw 1521bdea1361Sscw /* 1522bdea1361Sscw * Update and reset the statistics in the NPE. 1523bdea1361Sscw */ 1524bdea1361Sscw static int 1525bdea1361Sscw npe_updatestats(struct npe_softc *sc) 1526bdea1361Sscw { 1527bdea1361Sscw uint32_t msg[2]; 1528bdea1361Sscw 1529bdea1361Sscw msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1530bdea1361Sscw msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1531bdea1361Sscw return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */ 1532bdea1361Sscw } 1533bdea1361Sscw 1534bdea1361Sscw #if 0 1535bdea1361Sscw /* 1536bdea1361Sscw * Get the current statistics block. 1537bdea1361Sscw */ 1538bdea1361Sscw static int 1539bdea1361Sscw npe_getstats(struct npe_softc *sc) 1540bdea1361Sscw { 1541bdea1361Sscw uint32_t msg[2]; 1542bdea1361Sscw 1543bdea1361Sscw msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1544bdea1361Sscw msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1545bdea1361Sscw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1546bdea1361Sscw } 1547bdea1361Sscw 1548bdea1361Sscw /* 1549bdea1361Sscw * Query the image id of the loaded firmware. 1550bdea1361Sscw */ 1551bdea1361Sscw static uint32_t 1552bdea1361Sscw npe_getimageid(struct npe_softc *sc) 1553bdea1361Sscw { 1554bdea1361Sscw uint32_t msg[2]; 1555bdea1361Sscw 1556bdea1361Sscw msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1557bdea1361Sscw msg[1] = 0; 1558bdea1361Sscw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1559bdea1361Sscw } 1560bdea1361Sscw 1561bdea1361Sscw /* 1562bdea1361Sscw * Enable/disable loopback. 1563bdea1361Sscw */ 1564bdea1361Sscw static int 1565bdea1361Sscw npe_setloopback(struct npe_softc *sc, int ena) 1566bdea1361Sscw { 1567bdea1361Sscw uint32_t msg[2]; 1568bdea1361Sscw 1569bdea1361Sscw msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1570bdea1361Sscw msg[1] = 0; 1571bdea1361Sscw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1572bdea1361Sscw } 1573bdea1361Sscw #endif 1574bdea1361Sscw 1575bdea1361Sscw /* 1576bdea1361Sscw * MII bus support routines. 1577bdea1361Sscw * 1578bdea1361Sscw * NB: ixp425 has one PHY per NPE 1579bdea1361Sscw */ 1580bdea1361Sscw static uint32_t 1581bdea1361Sscw npe_mii_mdio_read(struct npe_softc *sc, int reg) 1582bdea1361Sscw { 1583bdea1361Sscw #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1584bdea1361Sscw uint32_t v; 1585bdea1361Sscw 1586bdea1361Sscw /* NB: registers are known to be sequential */ 1587bdea1361Sscw v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1588bdea1361Sscw v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1589bdea1361Sscw v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1590bdea1361Sscw v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1591bdea1361Sscw return v; 1592bdea1361Sscw #undef MII_RD4 1593bdea1361Sscw } 1594bdea1361Sscw 1595bdea1361Sscw static void 1596bdea1361Sscw npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1597bdea1361Sscw { 1598bdea1361Sscw #define MII_WR4(sc, reg, v) \ 1599bdea1361Sscw bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1600bdea1361Sscw 1601bdea1361Sscw /* NB: registers are known to be sequential */ 1602bdea1361Sscw MII_WR4(sc, reg+0, cmd & 0xff); 1603bdea1361Sscw MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1604bdea1361Sscw MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1605bdea1361Sscw MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1606bdea1361Sscw #undef MII_WR4 1607bdea1361Sscw } 1608bdea1361Sscw 1609bdea1361Sscw static int 1610bdea1361Sscw npe_mii_mdio_wait(struct npe_softc *sc) 1611bdea1361Sscw { 1612bdea1361Sscw #define MAXTRIES 100 /* XXX */ 1613bdea1361Sscw uint32_t v; 1614bdea1361Sscw int i; 1615bdea1361Sscw 1616bdea1361Sscw for (i = 0; i < MAXTRIES; i++) { 1617bdea1361Sscw v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1618bdea1361Sscw if ((v & NPE_MII_GO) == 0) 1619bdea1361Sscw return 1; 1620bdea1361Sscw } 1621bdea1361Sscw return 0; /* NB: timeout */ 1622bdea1361Sscw #undef MAXTRIES 1623bdea1361Sscw } 1624bdea1361Sscw 1625bdea1361Sscw static int 1626bdea1361Sscw npe_miibus_readreg(struct device *self, int phy, int reg) 1627bdea1361Sscw { 1628bdea1361Sscw struct npe_softc *sc = (void *)self; 1629bdea1361Sscw uint32_t v; 1630bdea1361Sscw 1631bdea1361Sscw if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1632bdea1361Sscw return 0xffff; 1633bdea1361Sscw v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1634bdea1361Sscw | NPE_MII_GO; 1635bdea1361Sscw npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 163692bdf645Sscw if (npe_mii_mdio_wait(sc)) 1637bdea1361Sscw v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1638bdea1361Sscw else 1639bdea1361Sscw v = 0xffff | NPE_MII_READ_FAIL; 1640bdea1361Sscw return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff); 1641bdea1361Sscw #undef MAXTRIES 1642bdea1361Sscw } 1643bdea1361Sscw 1644bdea1361Sscw static void 1645bdea1361Sscw npe_miibus_writereg(struct device *self, int phy, int reg, int data) 1646bdea1361Sscw { 1647bdea1361Sscw struct npe_softc *sc = (void *)self; 1648bdea1361Sscw uint32_t v; 1649bdea1361Sscw 1650bdea1361Sscw if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1651bdea1361Sscw return; 1652bdea1361Sscw v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1653bdea1361Sscw | data | NPE_MII_WRITE 1654bdea1361Sscw | NPE_MII_GO; 1655bdea1361Sscw npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1656bdea1361Sscw /* XXX complain about timeout */ 1657bdea1361Sscw (void) npe_mii_mdio_wait(sc); 1658bdea1361Sscw } 1659bdea1361Sscw 1660bdea1361Sscw static void 1661bdea1361Sscw npe_miibus_statchg(struct device *self) 1662bdea1361Sscw { 1663bdea1361Sscw struct npe_softc *sc = (void *)self; 1664bdea1361Sscw uint32_t tx1, rx1; 1665227ae4c9Smsaitoh uint32_t randoff; 1666bdea1361Sscw 1667bdea1361Sscw /* sync MAC duplex state */ 1668bdea1361Sscw tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1669bdea1361Sscw rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1670bdea1361Sscw if (sc->sc_mii.mii_media_active & IFM_FDX) { 1671227ae4c9Smsaitoh WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT); 1672bdea1361Sscw tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1673bdea1361Sscw rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1674bdea1361Sscw } else { 1675227ae4c9Smsaitoh struct timeval now; 1676227ae4c9Smsaitoh getmicrotime(&now); 1677227ae4c9Smsaitoh randoff = (RD4(sc, NPE_MAC_UNI_ADDR_6) ^ now.tv_usec) 1678227ae4c9Smsaitoh & 0x7f; 1679227ae4c9Smsaitoh WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT 1680227ae4c9Smsaitoh + randoff); 1681bdea1361Sscw tx1 |= NPE_TX_CNTRL1_DUPLEX; 1682bdea1361Sscw rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1683bdea1361Sscw } 1684bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1685bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1686bdea1361Sscw } 1687