1*e746222fSmsaitoh /* $NetBSD: ixp425_if_npe.c,v 1.36 2019/01/22 03:42:25 msaitoh Exp $ */ 2bdea1361Sscw 3bdea1361Sscw /*- 4bdea1361Sscw * Copyright (c) 2006 Sam Leffler. All rights reserved. 5bdea1361Sscw * 6bdea1361Sscw * Redistribution and use in source and binary forms, with or without 7bdea1361Sscw * modification, are permitted provided that the following conditions 8bdea1361Sscw * are met: 9bdea1361Sscw * 1. Redistributions of source code must retain the above copyright 10bdea1361Sscw * notice, this list of conditions and the following disclaimer. 11bdea1361Sscw * 2. Redistributions in binary form must reproduce the above copyright 12bdea1361Sscw * notice, this list of conditions and the following disclaimer in the 13bdea1361Sscw * documentation and/or other materials provided with the distribution. 14bdea1361Sscw * 15bdea1361Sscw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16bdea1361Sscw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17bdea1361Sscw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18bdea1361Sscw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19bdea1361Sscw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20bdea1361Sscw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21bdea1361Sscw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22bdea1361Sscw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23bdea1361Sscw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24bdea1361Sscw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25bdea1361Sscw */ 26bdea1361Sscw 27bdea1361Sscw #include <sys/cdefs.h> 28bdea1361Sscw #if 0 29bdea1361Sscw __FBSDID("$FreeBSD: src/sys/arm/xscale/ixp425/if_npe.c,v 1.1 2006/11/19 23:55:23 sam Exp $"); 30bdea1361Sscw #endif 31*e746222fSmsaitoh __KERNEL_RCSID(0, "$NetBSD: ixp425_if_npe.c,v 1.36 2019/01/22 03:42:25 msaitoh Exp $"); 32bdea1361Sscw 33bdea1361Sscw /* 34bdea1361Sscw * Intel XScale NPE Ethernet driver. 35bdea1361Sscw * 36bdea1361Sscw * This driver handles the two ports present on the IXP425. 37bdea1361Sscw * Packet processing is done by the Network Processing Engines 38bdea1361Sscw * (NPE's) that work together with a MAC and PHY. The MAC 39bdea1361Sscw * is also mapped to the XScale cpu; the PHY is accessed via 40bdea1361Sscw * the MAC. NPE-XScale communication happens through h/w 41bdea1361Sscw * queues managed by the Q Manager block. 42bdea1361Sscw * 43bdea1361Sscw * The code here replaces the ethAcc, ethMii, and ethDB classes 44bdea1361Sscw * in the Intel Access Library (IAL) and the OS-specific driver. 45bdea1361Sscw * 46bdea1361Sscw * XXX add vlan support 47bdea1361Sscw * XXX NPE-C port doesn't work yet 48bdea1361Sscw */ 49bdea1361Sscw 50bdea1361Sscw #include <sys/param.h> 51bdea1361Sscw #include <sys/systm.h> 52bdea1361Sscw #include <sys/kernel.h> 53bdea1361Sscw #include <sys/device.h> 54bdea1361Sscw #include <sys/callout.h> 55bdea1361Sscw #include <sys/mbuf.h> 56bdea1361Sscw #include <sys/malloc.h> 57bdea1361Sscw #include <sys/socket.h> 58bdea1361Sscw #include <sys/endian.h> 59bdea1361Sscw #include <sys/ioctl.h> 603589a8fdSmsaitoh #include <sys/syslog.h> 61bdea1361Sscw 62af51edd2Sdyoung #include <sys/bus.h> 63bdea1361Sscw 64bdea1361Sscw #include <net/if.h> 65bdea1361Sscw #include <net/if_dl.h> 66bdea1361Sscw #include <net/if_media.h> 67bdea1361Sscw #include <net/if_ether.h> 68bdea1361Sscw 69bdea1361Sscw #include <net/bpf.h> 70bdea1361Sscw 717347b26dSriastradh #include <sys/rndsource.h> 72507aaf9eSmsaitoh 73bdea1361Sscw #include <arm/xscale/ixp425reg.h> 74bdea1361Sscw #include <arm/xscale/ixp425var.h> 75bdea1361Sscw #include <arm/xscale/ixp425_qmgr.h> 76bdea1361Sscw #include <arm/xscale/ixp425_npevar.h> 77bdea1361Sscw #include <arm/xscale/ixp425_if_npereg.h> 78bdea1361Sscw 79bdea1361Sscw #include <dev/mii/miivar.h> 80bdea1361Sscw 81bdea1361Sscw #include "locators.h" 82bdea1361Sscw 83bdea1361Sscw struct npebuf { 84bdea1361Sscw struct npebuf *ix_next; /* chain to next buffer */ 85bdea1361Sscw void *ix_m; /* backpointer to mbuf */ 86bdea1361Sscw bus_dmamap_t ix_map; /* bus dma map for associated data */ 87bdea1361Sscw struct npehwbuf *ix_hw; /* associated h/w block */ 88bdea1361Sscw uint32_t ix_neaddr; /* phys address of ix_hw */ 89bdea1361Sscw }; 90bdea1361Sscw 91bdea1361Sscw struct npedma { 92bdea1361Sscw const char* name; 93bdea1361Sscw int nbuf; /* # npebuf's allocated */ 94bdea1361Sscw bus_dmamap_t m_map; 95bdea1361Sscw struct npehwbuf *hwbuf; /* NPE h/w buffers */ 96bdea1361Sscw bus_dmamap_t buf_map; 97bdea1361Sscw bus_addr_t buf_phys; /* phys addr of buffers */ 98bdea1361Sscw struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 99bdea1361Sscw }; 100bdea1361Sscw 101bdea1361Sscw struct npe_softc { 102e20bd029Smatt device_t sc_dev; 103bdea1361Sscw struct ethercom sc_ethercom; 1043589a8fdSmsaitoh uint8_t sc_enaddr[ETHER_ADDR_LEN]; 105bdea1361Sscw struct mii_data sc_mii; 106bdea1361Sscw bus_space_tag_t sc_iot; 107bdea1361Sscw bus_dma_tag_t sc_dt; 108bdea1361Sscw bus_space_handle_t sc_ioh; /* MAC register window */ 109bdea1361Sscw bus_space_handle_t sc_miih; /* MII register window */ 110bdea1361Sscw struct ixpnpe_softc *sc_npe; /* NPE support */ 111bdea1361Sscw int sc_unit; 112bdea1361Sscw int sc_phy; 113bdea1361Sscw struct callout sc_tick_ch; /* Tick callout */ 114bdea1361Sscw struct npedma txdma; 115bdea1361Sscw struct npebuf *tx_free; /* list of free tx buffers */ 116bdea1361Sscw struct npedma rxdma; 117bdea1361Sscw int rx_qid; /* rx qid */ 118bdea1361Sscw int rx_freeqid; /* rx free buffers qid */ 119bdea1361Sscw int tx_qid; /* tx qid */ 120bdea1361Sscw int tx_doneqid; /* tx completed qid */ 121bdea1361Sscw struct npestats *sc_stats; 122bdea1361Sscw bus_dmamap_t sc_stats_map; 123bdea1361Sscw bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 124816cf5b8Smsaitoh int sc_if_flags; /* keep last if_flags */ 1258e933452Stls krndsource_t rnd_source; /* random source */ 126bdea1361Sscw }; 127bdea1361Sscw 128bdea1361Sscw /* 129bdea1361Sscw * Per-unit static configuration for IXP425. The tx and 130bdea1361Sscw * rx free Q id's are fixed by the NPE microcode. The 131bdea1361Sscw * rx Q id's are programmed to be separate to simplify 132bdea1361Sscw * multi-port processing. It may be better to handle 133bdea1361Sscw * all traffic through one Q (as done by the Intel drivers). 134bdea1361Sscw * 135bdea1361Sscw * Note that the PHY's are accessible only from MAC A 136bdea1361Sscw * on the IXP425. This and other platform-specific 137bdea1361Sscw * assumptions probably need to be handled through hints. 138bdea1361Sscw */ 139bdea1361Sscw static const struct { 140bdea1361Sscw const char *desc; /* device description */ 141bdea1361Sscw int npeid; /* NPE assignment */ 142227ae4c9Smsaitoh int macport; /* Port number of the MAC */ 143bdea1361Sscw uint32_t imageid; /* NPE firmware image id */ 144bdea1361Sscw uint32_t regbase; 145bdea1361Sscw int regsize; 146bdea1361Sscw uint32_t miibase; 147bdea1361Sscw int miisize; 148bdea1361Sscw uint8_t rx_qid; 149bdea1361Sscw uint8_t rx_freeqid; 150bdea1361Sscw uint8_t tx_qid; 151bdea1361Sscw uint8_t tx_doneqid; 152bdea1361Sscw } npeconfig[NPE_PORTS_MAX] = { 153bdea1361Sscw { .desc = "IXP NPE-B", 154bdea1361Sscw .npeid = NPE_B, 155227ae4c9Smsaitoh .macport = 0x10, 156bdea1361Sscw .imageid = IXP425_NPE_B_IMAGEID, 157bdea1361Sscw .regbase = IXP425_MAC_A_HWBASE, 158bdea1361Sscw .regsize = IXP425_MAC_A_SIZE, 159bdea1361Sscw .miibase = IXP425_MAC_A_HWBASE, 160bdea1361Sscw .miisize = IXP425_MAC_A_SIZE, 161bdea1361Sscw .rx_qid = 4, 162bdea1361Sscw .rx_freeqid = 27, 163bdea1361Sscw .tx_qid = 24, 164bdea1361Sscw .tx_doneqid = 31 165bdea1361Sscw }, 166bdea1361Sscw { .desc = "IXP NPE-C", 167bdea1361Sscw .npeid = NPE_C, 168227ae4c9Smsaitoh .macport = 0x20, 169bdea1361Sscw .imageid = IXP425_NPE_C_IMAGEID, 170bdea1361Sscw .regbase = IXP425_MAC_B_HWBASE, 171bdea1361Sscw .regsize = IXP425_MAC_B_SIZE, 172bdea1361Sscw .miibase = IXP425_MAC_A_HWBASE, 173bdea1361Sscw .miisize = IXP425_MAC_A_SIZE, 174bdea1361Sscw .rx_qid = 12, 175bdea1361Sscw .rx_freeqid = 28, 176bdea1361Sscw .tx_qid = 25, 177bdea1361Sscw .tx_doneqid = 31 178bdea1361Sscw }, 179bdea1361Sscw }; 180bdea1361Sscw static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 181bdea1361Sscw 182bdea1361Sscw static __inline uint32_t 183bdea1361Sscw RD4(struct npe_softc *sc, bus_size_t off) 184bdea1361Sscw { 185bdea1361Sscw return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 186bdea1361Sscw } 187bdea1361Sscw 188bdea1361Sscw static __inline void 189bdea1361Sscw WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 190bdea1361Sscw { 191bdea1361Sscw bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 192bdea1361Sscw } 193bdea1361Sscw 194bdea1361Sscw static int npe_activate(struct npe_softc *); 195bdea1361Sscw #if 0 196bdea1361Sscw static void npe_deactivate(struct npe_softc *); 197bdea1361Sscw #endif 198bdea1361Sscw static void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr); 1996bc0c582Smatt static void npe_setmac(struct npe_softc *sc, const u_char *eaddr); 2003589a8fdSmsaitoh static void npe_getmac(struct npe_softc *sc); 201bdea1361Sscw static void npe_txdone(int qid, void *arg); 202bdea1361Sscw static int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 203bdea1361Sscw struct mbuf *); 204bdea1361Sscw static void npe_rxdone(int qid, void *arg); 205816cf5b8Smsaitoh static void npeinit_macreg(struct npe_softc *); 206bdea1361Sscw static int npeinit(struct ifnet *); 207227ae4c9Smsaitoh static void npeinit_resetcb(void *); 208816cf5b8Smsaitoh static void npeinit_locked(void *); 209bdea1361Sscw static void npestart(struct ifnet *); 210bdea1361Sscw static void npestop(struct ifnet *, int); 211bdea1361Sscw static void npewatchdog(struct ifnet *); 21253524e44Schristos static int npeioctl(struct ifnet * ifp, u_long, void *); 213bdea1361Sscw 214bdea1361Sscw static int npe_setrxqosentry(struct npe_softc *, int classix, 215bdea1361Sscw int trafclass, int qid); 216bdea1361Sscw static int npe_updatestats(struct npe_softc *); 217bdea1361Sscw #if 0 218bdea1361Sscw static int npe_getstats(struct npe_softc *); 219bdea1361Sscw static uint32_t npe_getimageid(struct npe_softc *); 220bdea1361Sscw static int npe_setloopback(struct npe_softc *, int ena); 221bdea1361Sscw #endif 222bdea1361Sscw 223*e746222fSmsaitoh static int npe_miibus_readreg(device_t, int, int, uint16_t *); 224*e746222fSmsaitoh static int npe_miibus_writereg(device_t, int, int, uint16_t); 225e20bd029Smatt static void npe_miibus_statchg(struct ifnet *); 226bdea1361Sscw 227bdea1361Sscw static int npe_debug; 228bdea1361Sscw #define DPRINTF(sc, fmt, ...) do { \ 229bdea1361Sscw if (npe_debug) printf(fmt, __VA_ARGS__); \ 230bdea1361Sscw } while (0) 231bdea1361Sscw #define DPRINTFn(n, sc, fmt, ...) do { \ 232bdea1361Sscw if (npe_debug >= n) printf(fmt, __VA_ARGS__); \ 233bdea1361Sscw } while (0) 234bdea1361Sscw 235bdea1361Sscw #define NPE_TXBUF 128 236bdea1361Sscw #define NPE_RXBUF 64 237bdea1361Sscw 238bdea1361Sscw #ifndef ETHER_ALIGN 239bdea1361Sscw #define ETHER_ALIGN 2 /* XXX: Ditch this */ 240bdea1361Sscw #endif 241bdea1361Sscw 2423589a8fdSmsaitoh #define MAC2UINT64(addr) (((uint64_t)addr[0] << 40) \ 2433589a8fdSmsaitoh + ((uint64_t)addr[1] << 32) \ 2443589a8fdSmsaitoh + ((uint64_t)addr[2] << 24) \ 2453589a8fdSmsaitoh + ((uint64_t)addr[3] << 16) \ 2463589a8fdSmsaitoh + ((uint64_t)addr[4] << 8) \ 2473589a8fdSmsaitoh + (uint64_t)addr[5]) 2483589a8fdSmsaitoh 249bdea1361Sscw /* NB: all tx done processing goes through one queue */ 250bdea1361Sscw static int tx_doneqid = -1; 251bdea1361Sscw 2523589a8fdSmsaitoh void (*npe_getmac_md)(int, uint8_t *); 2533589a8fdSmsaitoh 254e20bd029Smatt static int npe_match(device_t, cfdata_t, void *); 255e20bd029Smatt static void npe_attach(device_t, device_t, void *); 256bdea1361Sscw 257e20bd029Smatt CFATTACH_DECL_NEW(npe, sizeof(struct npe_softc), 258bdea1361Sscw npe_match, npe_attach, NULL, NULL); 259bdea1361Sscw 260bdea1361Sscw static int 261e20bd029Smatt npe_match(device_t parent, cfdata_t cf, void *arg) 262bdea1361Sscw { 263bdea1361Sscw struct ixpnpe_attach_args *na = arg; 264bdea1361Sscw 265bdea1361Sscw return (na->na_unit == NPE_B || na->na_unit == NPE_C); 266bdea1361Sscw } 267bdea1361Sscw 268bdea1361Sscw static void 269e20bd029Smatt npe_attach(device_t parent, device_t self, void *arg) 270bdea1361Sscw { 271e20bd029Smatt struct npe_softc *sc = device_private(self); 272e20bd029Smatt struct ixpnpe_softc *isc = device_private(parent); 273bdea1361Sscw struct ixpnpe_attach_args *na = arg; 274bdea1361Sscw struct ifnet *ifp; 275bdea1361Sscw 276bdea1361Sscw aprint_naive("\n"); 277bdea1361Sscw aprint_normal(": Ethernet co-processor\n"); 278bdea1361Sscw 279e20bd029Smatt sc->sc_dev = self; 280bdea1361Sscw sc->sc_iot = na->na_iot; 281bdea1361Sscw sc->sc_dt = na->na_dt; 282bdea1361Sscw sc->sc_npe = na->na_npe; 283bdea1361Sscw sc->sc_unit = (na->na_unit == NPE_B) ? 0 : 1; 284bdea1361Sscw sc->sc_phy = na->na_phy; 285bdea1361Sscw 286bdea1361Sscw memset(&sc->sc_ethercom, 0, sizeof(sc->sc_ethercom)); 287bdea1361Sscw memset(&sc->sc_mii, 0, sizeof(sc->sc_mii)); 288bdea1361Sscw 28988ab7da9Sad callout_init(&sc->sc_tick_ch, 0); 290bdea1361Sscw 291bdea1361Sscw if (npe_activate(sc)) { 292e20bd029Smatt aprint_error_dev(sc->sc_dev, 293e20bd029Smatt "Failed to activate NPE (missing microcode?)\n"); 294bdea1361Sscw return; 295bdea1361Sscw } 296bdea1361Sscw 2973589a8fdSmsaitoh npe_getmac(sc); 298b9c2a505Smsaitoh npeinit_macreg(sc); 299bdea1361Sscw 300e20bd029Smatt aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 3013589a8fdSmsaitoh ether_sprintf(sc->sc_enaddr)); 302bdea1361Sscw 303bdea1361Sscw ifp = &sc->sc_ethercom.ec_if; 304bdea1361Sscw sc->sc_mii.mii_ifp = ifp; 305bdea1361Sscw sc->sc_mii.mii_readreg = npe_miibus_readreg; 306bdea1361Sscw sc->sc_mii.mii_writereg = npe_miibus_writereg; 307bdea1361Sscw sc->sc_mii.mii_statchg = npe_miibus_statchg; 308b480b622Sdyoung sc->sc_ethercom.ec_mii = &sc->sc_mii; 309bdea1361Sscw 310273cfb27Smsaitoh ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 311273cfb27Smsaitoh npe_ifmedia_status); 312273cfb27Smsaitoh 313e20bd029Smatt mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 314273cfb27Smsaitoh MII_OFFSET_ANY, MIIF_DOPAUSE); 315273cfb27Smsaitoh if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 316273cfb27Smsaitoh ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 317273cfb27Smsaitoh ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 318273cfb27Smsaitoh } else 319bdea1361Sscw ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 320bdea1361Sscw 321bdea1361Sscw ifp->if_softc = sc; 322e20bd029Smatt strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 323bdea1361Sscw ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 324bdea1361Sscw ifp->if_start = npestart; 325bdea1361Sscw ifp->if_ioctl = npeioctl; 326bdea1361Sscw ifp->if_watchdog = npewatchdog; 327bdea1361Sscw ifp->if_init = npeinit; 328bdea1361Sscw ifp->if_stop = npestop; 329bdea1361Sscw IFQ_SET_READY(&ifp->if_snd); 330bdea1361Sscw 3318586a845Smsaitoh /* VLAN capable */ 3328586a845Smsaitoh sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 3338586a845Smsaitoh 334bdea1361Sscw if_attach(ifp); 335e3a04365Snonaka if_deferred_start_init(ifp, NULL); 3363589a8fdSmsaitoh ether_ifattach(ifp, sc->sc_enaddr); 337e20bd029Smatt rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 338a72ef114Stls RND_TYPE_NET, RND_FLAG_DEFAULT); 339227ae4c9Smsaitoh 340227ae4c9Smsaitoh /* callback function to reset MAC */ 341227ae4c9Smsaitoh isc->macresetcbfunc = npeinit_resetcb; 342227ae4c9Smsaitoh isc->macresetcbarg = sc; 343bdea1361Sscw } 344bdea1361Sscw 345bdea1361Sscw /* 346bdea1361Sscw * Compute and install the multicast filter. 347bdea1361Sscw */ 348bdea1361Sscw static void 349bdea1361Sscw npe_setmcast(struct npe_softc *sc) 350bdea1361Sscw { 351bdea1361Sscw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 352bdea1361Sscw uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 3533589a8fdSmsaitoh uint32_t reg; 354227ae4c9Smsaitoh uint32_t msg[2]; 355bdea1361Sscw int i; 356bdea1361Sscw 3573589a8fdSmsaitoh /* Always use filter. Is here a correct position? */ 3583589a8fdSmsaitoh reg = RD4(sc, NPE_MAC_RX_CNTRL1); 3593589a8fdSmsaitoh WR4(sc, NPE_MAC_RX_CNTRL1, reg | NPE_RX_CNTRL1_ADDR_FLTR_EN); 3603589a8fdSmsaitoh 361bdea1361Sscw if (ifp->if_flags & IFF_PROMISC) { 362bdea1361Sscw memset(mask, 0, ETHER_ADDR_LEN); 363bdea1361Sscw memset(addr, 0, ETHER_ADDR_LEN); 364bdea1361Sscw } else if (ifp->if_flags & IFF_ALLMULTI) { 365bdea1361Sscw static const uint8_t allmulti[ETHER_ADDR_LEN] = 366bdea1361Sscw { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 367bdea1361Sscw all_multi: 368bdea1361Sscw memcpy(mask, allmulti, ETHER_ADDR_LEN); 369bdea1361Sscw memcpy(addr, allmulti, ETHER_ADDR_LEN); 370bdea1361Sscw } else { 371bdea1361Sscw uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 372bdea1361Sscw struct ether_multistep step; 373bdea1361Sscw struct ether_multi *enm; 374bdea1361Sscw 375bdea1361Sscw memset(clr, 0, ETHER_ADDR_LEN); 376bdea1361Sscw memset(set, 0xff, ETHER_ADDR_LEN); 377bdea1361Sscw 378bdea1361Sscw ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 379bdea1361Sscw while (enm != NULL) { 380bdea1361Sscw if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 381bdea1361Sscw ifp->if_flags |= IFF_ALLMULTI; 382bdea1361Sscw goto all_multi; 383bdea1361Sscw } 384bdea1361Sscw 385bdea1361Sscw for (i = 0; i < ETHER_ADDR_LEN; i++) { 386bdea1361Sscw clr[i] |= enm->enm_addrlo[i]; 387bdea1361Sscw set[i] &= enm->enm_addrlo[i]; 388bdea1361Sscw } 389bdea1361Sscw 390bdea1361Sscw ETHER_NEXT_MULTI(step, enm); 391bdea1361Sscw } 392bdea1361Sscw 393bdea1361Sscw for (i = 0; i < ETHER_ADDR_LEN; i++) { 394bdea1361Sscw mask[i] = set[i] | ~clr[i]; 395bdea1361Sscw addr[i] = set[i]; 396bdea1361Sscw } 397bdea1361Sscw } 398bdea1361Sscw 399bdea1361Sscw /* 400bdea1361Sscw * Write the mask and address registers. 401bdea1361Sscw */ 402bdea1361Sscw for (i = 0; i < ETHER_ADDR_LEN; i++) { 403bdea1361Sscw WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 404bdea1361Sscw WR4(sc, NPE_MAC_ADDR(i), addr[i]); 405bdea1361Sscw } 406227ae4c9Smsaitoh 407227ae4c9Smsaitoh msg[0] = NPE_ADDRESSFILTERCONFIG << NPE_MAC_MSGID_SHL 408227ae4c9Smsaitoh | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL); 409227ae4c9Smsaitoh msg[1] = ((ifp->if_flags & IFF_PROMISC) ? 1 : 0) << 24 410227ae4c9Smsaitoh | ((RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff) << 16) 411227ae4c9Smsaitoh | (addr[5] << 8) | mask[5]; 412227ae4c9Smsaitoh ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 413bdea1361Sscw } 414bdea1361Sscw 415bdea1361Sscw static int 416bdea1361Sscw npe_dma_setup(struct npe_softc *sc, struct npedma *dma, 417bdea1361Sscw const char *name, int nbuf, int maxseg) 418bdea1361Sscw { 419bdea1361Sscw bus_dma_segment_t seg; 420bdea1361Sscw int rseg, error, i; 42153524e44Schristos void *hwbuf; 422bdea1361Sscw size_t size; 423bdea1361Sscw 4248586a845Smsaitoh memset(dma, 0, sizeof(*dma)); 425bdea1361Sscw 426bdea1361Sscw dma->name = name; 427bdea1361Sscw dma->nbuf = nbuf; 428bdea1361Sscw 429bdea1361Sscw size = nbuf * sizeof(struct npehwbuf); 430bdea1361Sscw 431bdea1361Sscw /* XXX COHERENT for now */ 432bdea1361Sscw error = bus_dmamem_alloc(sc->sc_dt, size, sizeof(uint32_t), 0, &seg, 433bdea1361Sscw 1, &rseg, BUS_DMA_NOWAIT); 434bdea1361Sscw if (error) { 435e20bd029Smatt aprint_error_dev(sc->sc_dev, 436e20bd029Smatt "unable to %s for %s %s buffers, error %u\n", 437e20bd029Smatt "allocate memory", dma->name, "h/w", error); 438bdea1361Sscw } 439bdea1361Sscw 440bdea1361Sscw error = bus_dmamem_map(sc->sc_dt, &seg, 1, size, &hwbuf, 441bdea1361Sscw BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_NOCACHE); 442bdea1361Sscw if (error) { 443e20bd029Smatt aprint_error_dev(sc->sc_dev, 444e20bd029Smatt "unable to %s for %s %s buffers, error %u\n", 445e20bd029Smatt "map memory", dma->name, "h/w", error); 446bdea1361Sscw free_dmamem: 447bdea1361Sscw bus_dmamem_free(sc->sc_dt, &seg, rseg); 448bdea1361Sscw return error; 449bdea1361Sscw } 450bdea1361Sscw dma->hwbuf = (void *)hwbuf; 451bdea1361Sscw 452bdea1361Sscw error = bus_dmamap_create(sc->sc_dt, size, 1, size, 0, 453bdea1361Sscw BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dma->buf_map); 454bdea1361Sscw if (error) { 455e20bd029Smatt aprint_error_dev(sc->sc_dev, 456e20bd029Smatt "unable to %s for %s %s buffers, error %u\n", 457e20bd029Smatt "create map", dma->name, "h/w", error); 458bdea1361Sscw unmap_dmamem: 459bdea1361Sscw dma->hwbuf = NULL; 460bdea1361Sscw bus_dmamem_unmap(sc->sc_dt, hwbuf, size); 461bdea1361Sscw goto free_dmamem; 462bdea1361Sscw } 463bdea1361Sscw 464bdea1361Sscw error = bus_dmamap_load(sc->sc_dt, dma->buf_map, hwbuf, size, NULL, 465bdea1361Sscw BUS_DMA_NOWAIT); 466bdea1361Sscw if (error) { 467e20bd029Smatt aprint_error_dev(sc->sc_dev, 468e20bd029Smatt "unable to %s for %s %s buffers, error %u\n", 469e20bd029Smatt "load map", dma->name, "h/w", error); 470bdea1361Sscw destroy_dmamap: 471bdea1361Sscw bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 472bdea1361Sscw goto unmap_dmamem; 473bdea1361Sscw } 474bdea1361Sscw 475bdea1361Sscw /* XXX M_TEMP */ 476bdea1361Sscw dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO); 477bdea1361Sscw if (dma->buf == NULL) { 478e20bd029Smatt aprint_error_dev(sc->sc_dev, 479e20bd029Smatt "unable to %s for %s %s buffers, error %u\n", 480e20bd029Smatt "allocate memory", dma->name, "h/w", error); 481bdea1361Sscw bus_dmamap_unload(sc->sc_dt, dma->buf_map); 482bdea1361Sscw error = ENOMEM; 483bdea1361Sscw goto destroy_dmamap; 484bdea1361Sscw } 485bdea1361Sscw 486bdea1361Sscw dma->buf_phys = dma->buf_map->dm_segs[0].ds_addr; 487bdea1361Sscw for (i = 0; i < dma->nbuf; i++) { 488bdea1361Sscw struct npebuf *npe = &dma->buf[i]; 489bdea1361Sscw struct npehwbuf *hw = &dma->hwbuf[i]; 490bdea1361Sscw 491bdea1361Sscw /* calculate offset to shared area */ 492bdea1361Sscw npe->ix_neaddr = dma->buf_phys + 493bdea1361Sscw ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 494bdea1361Sscw KASSERT((npe->ix_neaddr & 0x1f) == 0); 4958586a845Smsaitoh error = bus_dmamap_create(sc->sc_dt, MCLBYTES, maxseg, 496bdea1361Sscw MCLBYTES, 0, 0, &npe->ix_map); 497bdea1361Sscw if (error != 0) { 498e20bd029Smatt aprint_error_dev(sc->sc_dev, 499e20bd029Smatt "unable to %s for %s buffer %u, error %u\n", 500e20bd029Smatt "create dmamap", dma->name, i, error); 501bdea1361Sscw /* XXXSCW: Free up maps... */ 502bdea1361Sscw return error; 503bdea1361Sscw } 504bdea1361Sscw npe->ix_hw = hw; 505bdea1361Sscw } 506bdea1361Sscw bus_dmamap_sync(sc->sc_dt, dma->buf_map, 0, dma->buf_map->dm_mapsize, 507bdea1361Sscw BUS_DMASYNC_PREWRITE); 508bdea1361Sscw return 0; 509bdea1361Sscw } 510bdea1361Sscw 511bdea1361Sscw #if 0 512bdea1361Sscw static void 513bdea1361Sscw npe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 514bdea1361Sscw { 515bdea1361Sscw int i; 516bdea1361Sscw 517bdea1361Sscw /* XXXSCW: Clean this up */ 518bdea1361Sscw 519bdea1361Sscw if (dma->hwbuf != NULL) { 520bdea1361Sscw for (i = 0; i < dma->nbuf; i++) { 521bdea1361Sscw struct npebuf *npe = &dma->buf[i]; 522bdea1361Sscw bus_dmamap_destroy(sc->sc_dt, npe->ix_map); 523bdea1361Sscw } 524bdea1361Sscw bus_dmamap_unload(sc->sc_dt, dma->buf_map); 52553524e44Schristos bus_dmamem_free(sc->sc_dt, (void *)dma->hwbuf, dma->buf_map); 526bdea1361Sscw bus_dmamap_destroy(sc->sc_dt, dma->buf_map); 527bdea1361Sscw } 528bdea1361Sscw if (dma->buf != NULL) 529bdea1361Sscw free(dma->buf, M_TEMP); 530bdea1361Sscw memset(dma, 0, sizeof(*dma)); 531bdea1361Sscw } 532bdea1361Sscw #endif 533bdea1361Sscw 534bdea1361Sscw static int 535bdea1361Sscw npe_activate(struct npe_softc *sc) 536bdea1361Sscw { 537bdea1361Sscw bus_dma_segment_t seg; 538bdea1361Sscw int unit = sc->sc_unit; 539bdea1361Sscw int error, i, rseg; 54053524e44Schristos void *statbuf; 541bdea1361Sscw 542bdea1361Sscw /* load NPE firmware and start it running */ 543bdea1361Sscw error = ixpnpe_init(sc->sc_npe, "npe_fw", npeconfig[unit].imageid); 544bdea1361Sscw if (error != 0) 545bdea1361Sscw return error; 546bdea1361Sscw 547bdea1361Sscw if (bus_space_map(sc->sc_iot, npeconfig[unit].regbase, 548bdea1361Sscw npeconfig[unit].regsize, 0, &sc->sc_ioh)) { 549e20bd029Smatt aprint_error_dev(sc->sc_dev, "Cannot map registers 0x%x:0x%x\n", 550e20bd029Smatt npeconfig[unit].regbase, npeconfig[unit].regsize); 551bdea1361Sscw return ENOMEM; 552bdea1361Sscw } 553bdea1361Sscw 554bdea1361Sscw if (npeconfig[unit].miibase != npeconfig[unit].regbase) { 555bdea1361Sscw /* 556bdea1361Sscw * The PHY's are only accessible from one MAC (it appears) 557bdea1361Sscw * so for other MAC's setup an additional mapping for 558bdea1361Sscw * frobbing the PHY registers. 559bdea1361Sscw */ 560bdea1361Sscw if (bus_space_map(sc->sc_iot, npeconfig[unit].miibase, 561bdea1361Sscw npeconfig[unit].miisize, 0, &sc->sc_miih)) { 562e20bd029Smatt aprint_error_dev(sc->sc_dev, 563e20bd029Smatt "Cannot map MII registers 0x%x:0x%x\n", 564e20bd029Smatt npeconfig[unit].miibase, npeconfig[unit].miisize); 565bdea1361Sscw return ENOMEM; 566bdea1361Sscw } 567bdea1361Sscw } else 568bdea1361Sscw sc->sc_miih = sc->sc_ioh; 569bdea1361Sscw error = npe_dma_setup(sc, &sc->txdma, "tx", NPE_TXBUF, NPE_MAXSEG); 570bdea1361Sscw if (error != 0) 571bdea1361Sscw return error; 572bdea1361Sscw error = npe_dma_setup(sc, &sc->rxdma, "rx", NPE_RXBUF, 1); 573bdea1361Sscw if (error != 0) 574bdea1361Sscw return error; 575bdea1361Sscw 576bdea1361Sscw /* setup statistics block */ 577bdea1361Sscw error = bus_dmamem_alloc(sc->sc_dt, sizeof(struct npestats), 578bdea1361Sscw sizeof(uint32_t), 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 579bdea1361Sscw if (error) { 580e20bd029Smatt aprint_error_dev(sc->sc_dev, 581e20bd029Smatt "unable to %s for %s, error %u\n", 582e20bd029Smatt "allocate memory", "stats block", error); 583bdea1361Sscw return error; 584bdea1361Sscw } 585bdea1361Sscw 586bdea1361Sscw error = bus_dmamem_map(sc->sc_dt, &seg, 1, sizeof(struct npestats), 587bdea1361Sscw &statbuf, BUS_DMA_NOWAIT); 588bdea1361Sscw if (error) { 589e20bd029Smatt aprint_error_dev(sc->sc_dev, 590e20bd029Smatt "unable to %s for %s, error %u\n", 591e20bd029Smatt "map memory", "stats block", error); 592bdea1361Sscw return error; 593bdea1361Sscw } 594bdea1361Sscw sc->sc_stats = (void *)statbuf; 595bdea1361Sscw 596bdea1361Sscw error = bus_dmamap_create(sc->sc_dt, sizeof(struct npestats), 1, 597bdea1361Sscw sizeof(struct npestats), 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 598bdea1361Sscw &sc->sc_stats_map); 599bdea1361Sscw if (error) { 600e20bd029Smatt aprint_error_dev(sc->sc_dev, 601e20bd029Smatt "unable to %s for %s, error %u\n", 602e20bd029Smatt "create map", "stats block", error); 603bdea1361Sscw return error; 604bdea1361Sscw } 605bdea1361Sscw 60646710031Smaxv error = bus_dmamap_load(sc->sc_dt, sc->sc_stats_map, sc->sc_stats, 60746710031Smaxv sizeof(struct npestats), NULL, BUS_DMA_NOWAIT); 60846710031Smaxv if (error) { 609e20bd029Smatt aprint_error_dev(sc->sc_dev, 610e20bd029Smatt "unable to %s for %s, error %u\n", 611e20bd029Smatt "load map", "stats block", error); 612bdea1361Sscw return error; 613bdea1361Sscw } 614bdea1361Sscw sc->sc_stats_phys = sc->sc_stats_map->dm_segs[0].ds_addr; 615bdea1361Sscw 616bdea1361Sscw /* XXX disable half-bridge LEARNING+FILTERING feature */ 617bdea1361Sscw 618bdea1361Sscw /* 619bdea1361Sscw * Setup h/w rx/tx queues. There are four q's: 620bdea1361Sscw * rx inbound q of rx'd frames 621bdea1361Sscw * rx_free pool of ixpbuf's for receiving frames 622bdea1361Sscw * tx outbound q of frames to send 623bdea1361Sscw * tx_done q of tx frames that have been processed 624bdea1361Sscw * 625bdea1361Sscw * The NPE handles the actual tx/rx process and the q manager 626bdea1361Sscw * handles the queues. The driver just writes entries to the 627bdea1361Sscw * q manager mailbox's and gets callbacks when there are rx'd 628bdea1361Sscw * frames to process or tx'd frames to reap. These callbacks 629bdea1361Sscw * are controlled by the q configurations; e.g. we get a 630bdea1361Sscw * callback when tx_done has 2 or more frames to process and 631bdea1361Sscw * when the rx q has at least one frame. These setings can 632bdea1361Sscw * changed at the time the q is configured. 633bdea1361Sscw */ 634bdea1361Sscw sc->rx_qid = npeconfig[unit].rx_qid; 635bdea1361Sscw ixpqmgr_qconfig(sc->rx_qid, NPE_RXBUF, 0, 1, 636bdea1361Sscw IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc); 637bdea1361Sscw sc->rx_freeqid = npeconfig[unit].rx_freeqid; 638bdea1361Sscw ixpqmgr_qconfig(sc->rx_freeqid, NPE_RXBUF, 0, NPE_RXBUF/2, 0, NULL, sc); 639bdea1361Sscw /* tell the NPE to direct all traffic to rx_qid */ 640bdea1361Sscw #if 0 641bdea1361Sscw for (i = 0; i < 8; i++) 642bdea1361Sscw #else 643e20bd029Smatt printf("%s: remember to fix rx q setup\n", device_xname(sc->sc_dev)); 644bdea1361Sscw for (i = 0; i < 4; i++) 645bdea1361Sscw #endif 646bdea1361Sscw npe_setrxqosentry(sc, i, 0, sc->rx_qid); 647bdea1361Sscw 648bdea1361Sscw sc->tx_qid = npeconfig[unit].tx_qid; 649bdea1361Sscw sc->tx_doneqid = npeconfig[unit].tx_doneqid; 650bdea1361Sscw ixpqmgr_qconfig(sc->tx_qid, NPE_TXBUF, 0, NPE_TXBUF, 0, NULL, sc); 651bdea1361Sscw if (tx_doneqid == -1) { 652bdea1361Sscw ixpqmgr_qconfig(sc->tx_doneqid, NPE_TXBUF, 0, 2, 653bdea1361Sscw IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 654bdea1361Sscw tx_doneqid = sc->tx_doneqid; 655bdea1361Sscw } 656bdea1361Sscw 657bdea1361Sscw KASSERT(npes[npeconfig[unit].npeid] == NULL); 658bdea1361Sscw npes[npeconfig[unit].npeid] = sc; 659bdea1361Sscw 660bdea1361Sscw return 0; 661bdea1361Sscw } 662bdea1361Sscw 663bdea1361Sscw #if 0 664bdea1361Sscw static void 665bdea1361Sscw npe_deactivate(struct npe_softc *sc); 666bdea1361Sscw { 667bdea1361Sscw int unit = sc->sc_unit; 668bdea1361Sscw 669bdea1361Sscw npes[npeconfig[unit].npeid] = NULL; 670bdea1361Sscw 671bdea1361Sscw /* XXX disable q's */ 672bdea1361Sscw if (sc->sc_npe != NULL) 673bdea1361Sscw ixpnpe_stop(sc->sc_npe); 674bdea1361Sscw if (sc->sc_stats != NULL) { 675bdea1361Sscw bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 676bdea1361Sscw bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 677bdea1361Sscw sc->sc_stats_map); 678bdea1361Sscw bus_dmamap_destroy(sc->sc_stats_tag, sc->sc_stats_map); 679bdea1361Sscw } 680bdea1361Sscw if (sc->sc_stats_tag != NULL) 681bdea1361Sscw bus_dma_tag_destroy(sc->sc_stats_tag); 682bdea1361Sscw npe_dma_destroy(sc, &sc->txdma); 683bdea1361Sscw npe_dma_destroy(sc, &sc->rxdma); 684bdea1361Sscw bus_generic_detach(sc->sc_dev); 685bdea1361Sscw if (sc->sc_mii) 686bdea1361Sscw device_delete_child(sc->sc_dev, sc->sc_mii); 687bdea1361Sscw #if 0 688bdea1361Sscw /* XXX sc_ioh and sc_miih */ 689bdea1361Sscw if (sc->mem_res) 690bdea1361Sscw bus_release_resource(dev, SYS_RES_IOPORT, 691bdea1361Sscw rman_get_rid(sc->mem_res), sc->mem_res); 692bdea1361Sscw sc->mem_res = 0; 693bdea1361Sscw #endif 694bdea1361Sscw } 695bdea1361Sscw #endif 696bdea1361Sscw 697bdea1361Sscw /* 698bdea1361Sscw * Notify the world which media we're using. 699bdea1361Sscw */ 700bdea1361Sscw static void 701bdea1361Sscw npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 702bdea1361Sscw { 703bdea1361Sscw struct npe_softc *sc = ifp->if_softc; 704bdea1361Sscw 705bdea1361Sscw mii_pollstat(&sc->sc_mii); 706bdea1361Sscw 707bdea1361Sscw ifmr->ifm_active = sc->sc_mii.mii_media_active; 708bdea1361Sscw ifmr->ifm_status = sc->sc_mii.mii_media_status; 709bdea1361Sscw } 710bdea1361Sscw 711bdea1361Sscw static void 712bdea1361Sscw npe_addstats(struct npe_softc *sc) 713bdea1361Sscw { 714bdea1361Sscw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 715bdea1361Sscw struct npestats *ns = sc->sc_stats; 716bdea1361Sscw 717bdea1361Sscw ifp->if_oerrors += 718bdea1361Sscw be32toh(ns->dot3StatsInternalMacTransmitErrors) 719bdea1361Sscw + be32toh(ns->dot3StatsCarrierSenseErrors) 720bdea1361Sscw + be32toh(ns->TxVLANIdFilterDiscards) 721bdea1361Sscw ; 722bdea1361Sscw ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 723bdea1361Sscw + be32toh(ns->dot3StatsInternalMacReceiveErrors) 724bdea1361Sscw + be32toh(ns->RxOverrunDiscards) 725bdea1361Sscw + be32toh(ns->RxUnderflowEntryDiscards) 726bdea1361Sscw ; 727bdea1361Sscw ifp->if_collisions += 728bdea1361Sscw be32toh(ns->dot3StatsSingleCollisionFrames) 729bdea1361Sscw + be32toh(ns->dot3StatsMultipleCollisionFrames) 730bdea1361Sscw ; 731bdea1361Sscw } 732bdea1361Sscw 733bdea1361Sscw static void 734bdea1361Sscw npe_tick(void *xsc) 735bdea1361Sscw { 736bdea1361Sscw #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 737bdea1361Sscw struct npe_softc *sc = xsc; 738bdea1361Sscw uint32_t msg[2]; 739bdea1361Sscw 740bdea1361Sscw /* 741bdea1361Sscw * NB: to avoid sleeping with the softc lock held we 742bdea1361Sscw * split the NPE msg processing into two parts. The 743bdea1361Sscw * request for statistics is sent w/o waiting for a 744bdea1361Sscw * reply and then on the next tick we retrieve the 745bdea1361Sscw * results. This works because npe_tick is the only 746bdea1361Sscw * code that talks via the mailbox's (except at setup). 747bdea1361Sscw * This likely can be handled better. 748bdea1361Sscw */ 749bdea1361Sscw if (ixpnpe_recvmsg(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 750bdea1361Sscw bus_dmamap_sync(sc->sc_dt, sc->sc_stats_map, 0, 751bdea1361Sscw sizeof(struct npestats), BUS_DMASYNC_POSTREAD); 752bdea1361Sscw npe_addstats(sc); 753bdea1361Sscw } 754bdea1361Sscw npe_updatestats(sc); 755bdea1361Sscw mii_tick(&sc->sc_mii); 756bdea1361Sscw 757bdea1361Sscw /* schedule next poll */ 758bdea1361Sscw callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 759bdea1361Sscw #undef ACK 760bdea1361Sscw } 761bdea1361Sscw 762bdea1361Sscw static void 7636bc0c582Smatt npe_setmac(struct npe_softc *sc, const u_char *eaddr) 764bdea1361Sscw { 7653589a8fdSmsaitoh 766bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 767bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 768bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 769bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 770bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 771bdea1361Sscw WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 772bdea1361Sscw } 773bdea1361Sscw 774bdea1361Sscw static void 7753589a8fdSmsaitoh npe_getmac(struct npe_softc *sc) 776bdea1361Sscw { 7773589a8fdSmsaitoh uint8_t *eaddr = sc->sc_enaddr; 7783589a8fdSmsaitoh 7793589a8fdSmsaitoh if (npe_getmac_md != NULL) { 780e20bd029Smatt (*npe_getmac_md)(device_unit(sc->sc_dev), eaddr); 7813589a8fdSmsaitoh } else { 7823589a8fdSmsaitoh /* 7833589a8fdSmsaitoh * Some system's unicast address appears to be loaded from 7843589a8fdSmsaitoh * EEPROM on reset 7853589a8fdSmsaitoh */ 786bdea1361Sscw eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 787bdea1361Sscw eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 788bdea1361Sscw eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 789bdea1361Sscw eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 790bdea1361Sscw eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 791bdea1361Sscw eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 792bdea1361Sscw } 7933589a8fdSmsaitoh } 794bdea1361Sscw 795bdea1361Sscw struct txdone { 796bdea1361Sscw struct npebuf *head; 797bdea1361Sscw struct npebuf **tail; 798bdea1361Sscw int count; 799bdea1361Sscw }; 800bdea1361Sscw 801bdea1361Sscw static __inline void 802bdea1361Sscw npe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 803bdea1361Sscw { 804bdea1361Sscw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 805bdea1361Sscw 806bdea1361Sscw *td->tail = sc->tx_free; 807bdea1361Sscw sc->tx_free = td->head; 808bdea1361Sscw /* 809bdea1361Sscw * We're no longer busy, so clear the busy flag and call the 810bdea1361Sscw * start routine to xmit more packets. 811bdea1361Sscw */ 812bdea1361Sscw ifp->if_opackets += td->count; 813bdea1361Sscw ifp->if_flags &= ~IFF_OACTIVE; 814bdea1361Sscw ifp->if_timer = 0; 815e3a04365Snonaka if_schedule_deferred_start(ifp); 816bdea1361Sscw } 817bdea1361Sscw 818bdea1361Sscw /* 819bdea1361Sscw * Q manager callback on tx done queue. Reap mbufs 820bdea1361Sscw * and return tx buffers to the free list. Finally 821bdea1361Sscw * restart output. Note the microcode has only one 822bdea1361Sscw * txdone q wired into it so we must use the NPE ID 823bdea1361Sscw * returned with each npehwbuf to decide where to 824bdea1361Sscw * send buffers. 825bdea1361Sscw */ 826bdea1361Sscw static void 827bdea1361Sscw npe_txdone(int qid, void *arg) 828bdea1361Sscw { 829bdea1361Sscw #define P2V(a, dma) \ 830bdea1361Sscw &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 831bdea1361Sscw struct npe_softc *sc; 832bdea1361Sscw struct npebuf *npe; 833bdea1361Sscw struct txdone *td, q[NPE_MAX]; 834bdea1361Sscw uint32_t entry; 835bdea1361Sscw 836bdea1361Sscw /* XXX no NPE-A support */ 837bdea1361Sscw q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 838bdea1361Sscw q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 839bdea1361Sscw /* XXX max # at a time? */ 840bdea1361Sscw while (ixpqmgr_qread(qid, &entry) == 0) { 841bdea1361Sscw sc = npes[NPE_QM_Q_NPE(entry)]; 842bdea1361Sscw DPRINTF(sc, "%s: entry 0x%x NPE %u port %u\n", 843bdea1361Sscw __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 844507aaf9eSmsaitoh rnd_add_uint32(&sc->rnd_source, entry); 845bdea1361Sscw 846bdea1361Sscw npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 847bdea1361Sscw m_freem(npe->ix_m); 848bdea1361Sscw npe->ix_m = NULL; 849bdea1361Sscw 850bdea1361Sscw td = &q[NPE_QM_Q_NPE(entry)]; 851bdea1361Sscw *td->tail = npe; 852bdea1361Sscw td->tail = &npe->ix_next; 853bdea1361Sscw td->count++; 854bdea1361Sscw } 855bdea1361Sscw 856bdea1361Sscw if (q[NPE_B].count) 857bdea1361Sscw npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 858bdea1361Sscw if (q[NPE_C].count) 859bdea1361Sscw npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 860bdea1361Sscw #undef P2V 861bdea1361Sscw } 862bdea1361Sscw 863bdea1361Sscw static __inline struct mbuf * 864bdea1361Sscw npe_getcl(void) 865bdea1361Sscw { 866bdea1361Sscw struct mbuf *m; 867bdea1361Sscw 868bdea1361Sscw MGETHDR(m, M_DONTWAIT, MT_DATA); 869bdea1361Sscw if (m != NULL) { 870bdea1361Sscw MCLGET(m, M_DONTWAIT); 871bdea1361Sscw if ((m->m_flags & M_EXT) == 0) { 872bdea1361Sscw m_freem(m); 873bdea1361Sscw m = NULL; 874bdea1361Sscw } 875bdea1361Sscw } 876bdea1361Sscw return (m); 877bdea1361Sscw } 878bdea1361Sscw 879bdea1361Sscw static int 880bdea1361Sscw npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 881bdea1361Sscw { 882bdea1361Sscw struct npehwbuf *hw; 883bdea1361Sscw int error; 884bdea1361Sscw 885bdea1361Sscw if (m == NULL) { 886bdea1361Sscw m = npe_getcl(); 887bdea1361Sscw if (m == NULL) 888bdea1361Sscw return ENOBUFS; 889bdea1361Sscw } 8903589a8fdSmsaitoh KASSERT(m->m_ext.ext_size >= (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 8913589a8fdSmsaitoh m->m_pkthdr.len = m->m_len = NPE_FRAME_SIZE_DEFAULT; 892bdea1361Sscw /* backload payload and align ip hdr */ 8933589a8fdSmsaitoh m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size 8943589a8fdSmsaitoh - (NPE_FRAME_SIZE_DEFAULT + ETHER_ALIGN)); 895bdea1361Sscw error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 896bdea1361Sscw BUS_DMA_READ|BUS_DMA_NOWAIT); 897bdea1361Sscw if (error != 0) { 898bdea1361Sscw m_freem(m); 899bdea1361Sscw return error; 900bdea1361Sscw } 901bdea1361Sscw hw = npe->ix_hw; 902bdea1361Sscw hw->ix_ne[0].data = htobe32(npe->ix_map->dm_segs[0].ds_addr); 903bdea1361Sscw /* NB: NPE requires length be a multiple of 64 */ 904bdea1361Sscw /* NB: buffer length is shifted in word */ 905bdea1361Sscw hw->ix_ne[0].len = htobe32(npe->ix_map->dm_segs[0].ds_len << 16); 906bdea1361Sscw hw->ix_ne[0].next = 0; 907bdea1361Sscw npe->ix_m = m; 908bdea1361Sscw /* Flush the memory in the mbuf */ 909bdea1361Sscw bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, npe->ix_map->dm_mapsize, 910bdea1361Sscw BUS_DMASYNC_PREREAD); 911bdea1361Sscw return 0; 912bdea1361Sscw } 913bdea1361Sscw 914bdea1361Sscw /* 915bdea1361Sscw * RX q processing for a specific NPE. Claim entries 916bdea1361Sscw * from the hardware queue and pass the frames up the 917bdea1361Sscw * stack. Pass the rx buffers to the free list. 918bdea1361Sscw */ 919bdea1361Sscw static void 920bdea1361Sscw npe_rxdone(int qid, void *arg) 921bdea1361Sscw { 922bdea1361Sscw #define P2V(a, dma) \ 923bdea1361Sscw &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 924bdea1361Sscw struct npe_softc *sc = arg; 925bdea1361Sscw struct npedma *dma = &sc->rxdma; 926bdea1361Sscw uint32_t entry; 927bdea1361Sscw 928bdea1361Sscw while (ixpqmgr_qread(qid, &entry) == 0) { 929bdea1361Sscw struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 930bdea1361Sscw struct mbuf *m; 931bdea1361Sscw 932bdea1361Sscw DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 933bdea1361Sscw __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 934507aaf9eSmsaitoh rnd_add_uint32(&sc->rnd_source, entry); 935bdea1361Sscw /* 936bdea1361Sscw * Allocate a new mbuf to replenish the rx buffer. 937bdea1361Sscw * If doing so fails we drop the rx'd frame so we 938bdea1361Sscw * can reuse the previous mbuf. When we're able to 939bdea1361Sscw * allocate a new mbuf dispatch the mbuf w/ rx'd 940bdea1361Sscw * data up the stack and replace it with the newly 941bdea1361Sscw * allocated one. 942bdea1361Sscw */ 943bdea1361Sscw m = npe_getcl(); 944bdea1361Sscw if (m != NULL) { 945bdea1361Sscw struct mbuf *mrx = npe->ix_m; 946bdea1361Sscw struct npehwbuf *hw = npe->ix_hw; 947bdea1361Sscw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 948bdea1361Sscw 949bdea1361Sscw /* Flush mbuf memory for rx'd data */ 950bdea1361Sscw bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 951bdea1361Sscw npe->ix_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 952bdea1361Sscw 953bdea1361Sscw /* XXX flush hw buffer; works now 'cuz coherent */ 954bdea1361Sscw /* set m_len etc. per rx frame size */ 955bdea1361Sscw mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 956bdea1361Sscw mrx->m_pkthdr.len = mrx->m_len; 957758ba73eSozaki-r m_set_rcvif(mrx, ifp); 9583589a8fdSmsaitoh /* Don't add M_HASFCS. See below */ 9593589a8fdSmsaitoh 9603589a8fdSmsaitoh #if 1 9613589a8fdSmsaitoh if (mrx->m_pkthdr.len < sizeof(struct ether_header)) { 9623589a8fdSmsaitoh log(LOG_INFO, "%s: too short frame (len=%d)\n", 963e20bd029Smatt device_xname(sc->sc_dev), mrx->m_pkthdr.len); 9643589a8fdSmsaitoh /* Back out "newly allocated" mbuf. */ 9653589a8fdSmsaitoh m_freem(m); 9663589a8fdSmsaitoh ifp->if_ierrors++; 9673589a8fdSmsaitoh goto fail; 9683589a8fdSmsaitoh } 9693589a8fdSmsaitoh if ((ifp->if_flags & IFF_PROMISC) == 0) { 9703589a8fdSmsaitoh struct ether_header *eh; 9713589a8fdSmsaitoh 9723589a8fdSmsaitoh /* 9733589a8fdSmsaitoh * Workaround for "Non-Intel XScale Technology 9743589a8fdSmsaitoh * Eratta" No. 29. AA:BB:CC:DD:EE:xF's packet 9753589a8fdSmsaitoh * matches the filter (both unicast and 9763589a8fdSmsaitoh * multicast). 9773589a8fdSmsaitoh */ 9783589a8fdSmsaitoh eh = mtod(mrx, struct ether_header *); 9793589a8fdSmsaitoh if (ETHER_IS_MULTICAST(eh->ether_dhost) == 0) { 9803589a8fdSmsaitoh /* unicast */ 9813589a8fdSmsaitoh 9823589a8fdSmsaitoh if (sc->sc_enaddr[5] != eh->ether_dhost[5]) { 9833589a8fdSmsaitoh /* discard it */ 9843589a8fdSmsaitoh #if 0 9853589a8fdSmsaitoh printf("discard it\n"); 9863589a8fdSmsaitoh #endif 9873589a8fdSmsaitoh /* 9883589a8fdSmsaitoh * Back out "newly allocated" 9893589a8fdSmsaitoh * mbuf. 9903589a8fdSmsaitoh */ 9913589a8fdSmsaitoh m_freem(m); 9923589a8fdSmsaitoh goto fail; 9933589a8fdSmsaitoh } 9943589a8fdSmsaitoh } else if (memcmp(eh->ether_dhost, 9953589a8fdSmsaitoh etherbroadcastaddr, 6) == 0) { 9963589a8fdSmsaitoh /* Always accept broadcast packet*/ 9973589a8fdSmsaitoh } else { 9983589a8fdSmsaitoh struct ethercom *ec = &sc->sc_ethercom; 9993589a8fdSmsaitoh struct ether_multi *enm; 10003589a8fdSmsaitoh struct ether_multistep step; 10013589a8fdSmsaitoh int match = 0; 10023589a8fdSmsaitoh 10033589a8fdSmsaitoh /* multicast */ 10043589a8fdSmsaitoh 10053589a8fdSmsaitoh ETHER_FIRST_MULTI(step, ec, enm); 10063589a8fdSmsaitoh while (enm != NULL) { 10073589a8fdSmsaitoh uint64_t lowint, highint, dest; 10083589a8fdSmsaitoh 10093589a8fdSmsaitoh lowint = MAC2UINT64(enm->enm_addrlo); 10103589a8fdSmsaitoh highint = MAC2UINT64(enm->enm_addrhi); 10113589a8fdSmsaitoh dest = MAC2UINT64(eh->ether_dhost); 10123589a8fdSmsaitoh #if 0 10133589a8fdSmsaitoh printf("%llx\n", lowint); 10143589a8fdSmsaitoh printf("%llx\n", dest); 10153589a8fdSmsaitoh printf("%llx\n", highint); 10163589a8fdSmsaitoh #endif 10173589a8fdSmsaitoh if ((lowint <= dest) && (dest <= highint)) { 10183589a8fdSmsaitoh match = 1; 10193589a8fdSmsaitoh break; 10203589a8fdSmsaitoh } 10213589a8fdSmsaitoh ETHER_NEXT_MULTI(step, enm); 10223589a8fdSmsaitoh } 10233589a8fdSmsaitoh if (match == 0) { 10243589a8fdSmsaitoh /* discard it */ 10253589a8fdSmsaitoh #if 0 10263589a8fdSmsaitoh printf("discard it(M)\n"); 10273589a8fdSmsaitoh #endif 10283589a8fdSmsaitoh /* 10293589a8fdSmsaitoh * Back out "newly allocated" 10303589a8fdSmsaitoh * mbuf. 10313589a8fdSmsaitoh */ 10323589a8fdSmsaitoh m_freem(m); 10333589a8fdSmsaitoh goto fail; 10343589a8fdSmsaitoh } 10353589a8fdSmsaitoh } 10363589a8fdSmsaitoh } 10373589a8fdSmsaitoh if (mrx->m_pkthdr.len > NPE_FRAME_SIZE_DEFAULT) { 10383589a8fdSmsaitoh log(LOG_INFO, "%s: oversized frame (len=%d)\n", 1039e20bd029Smatt device_xname(sc->sc_dev), mrx->m_pkthdr.len); 10403589a8fdSmsaitoh /* Back out "newly allocated" mbuf. */ 10413589a8fdSmsaitoh m_freem(m); 10423589a8fdSmsaitoh ifp->if_ierrors++; 10433589a8fdSmsaitoh goto fail; 10443589a8fdSmsaitoh } 10453589a8fdSmsaitoh #endif 10463589a8fdSmsaitoh 10473589a8fdSmsaitoh /* 10483589a8fdSmsaitoh * Trim FCS! 10493589a8fdSmsaitoh * NPE always adds the FCS by this driver's setting, 10503589a8fdSmsaitoh * so we always trim it here and not add M_HASFCS. 10513589a8fdSmsaitoh */ 10523589a8fdSmsaitoh m_adj(mrx, -ETHER_CRC_LEN); 1053bdea1361Sscw 10548586a845Smsaitoh /* 10558586a845Smsaitoh * Tap off here if there is a bpf listener. 10568586a845Smsaitoh */ 10575a3149d8Sozaki-r 1058b8256fd8Sozaki-r if_percpuq_enqueue(ifp->if_percpuq, mrx); 1059bdea1361Sscw } else { 10603589a8fdSmsaitoh fail: 1061bdea1361Sscw /* discard frame and re-use mbuf */ 1062bdea1361Sscw m = npe->ix_m; 1063bdea1361Sscw } 1064bdea1361Sscw if (npe_rxbuf_init(sc, npe, m) == 0) { 1065bdea1361Sscw /* return npe buf to rx free list */ 1066bdea1361Sscw ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1067bdea1361Sscw } else { 1068bdea1361Sscw /* XXX should not happen */ 1069bdea1361Sscw } 1070bdea1361Sscw } 1071bdea1361Sscw #undef P2V 1072bdea1361Sscw } 1073bdea1361Sscw 1074bdea1361Sscw static void 1075bdea1361Sscw npe_startxmit(struct npe_softc *sc) 1076bdea1361Sscw { 1077bdea1361Sscw struct npedma *dma = &sc->txdma; 1078bdea1361Sscw int i; 1079bdea1361Sscw 1080bdea1361Sscw sc->tx_free = NULL; 1081bdea1361Sscw for (i = 0; i < dma->nbuf; i++) { 1082bdea1361Sscw struct npebuf *npe = &dma->buf[i]; 1083bdea1361Sscw if (npe->ix_m != NULL) { 1084bdea1361Sscw /* NB: should not happen */ 1085bdea1361Sscw printf("%s: %s: free mbuf at entry %u\n", 1086e20bd029Smatt device_xname(sc->sc_dev), __func__, i); 1087bdea1361Sscw m_freem(npe->ix_m); 1088bdea1361Sscw } 1089bdea1361Sscw npe->ix_m = NULL; 1090bdea1361Sscw npe->ix_next = sc->tx_free; 1091bdea1361Sscw sc->tx_free = npe; 1092bdea1361Sscw } 1093bdea1361Sscw } 1094bdea1361Sscw 1095bdea1361Sscw static void 1096bdea1361Sscw npe_startrecv(struct npe_softc *sc) 1097bdea1361Sscw { 1098bdea1361Sscw struct npedma *dma = &sc->rxdma; 1099bdea1361Sscw struct npebuf *npe; 1100bdea1361Sscw int i; 1101bdea1361Sscw 1102bdea1361Sscw for (i = 0; i < dma->nbuf; i++) { 1103bdea1361Sscw npe = &dma->buf[i]; 1104bdea1361Sscw npe_rxbuf_init(sc, npe, npe->ix_m); 1105bdea1361Sscw /* set npe buf on rx free list */ 1106bdea1361Sscw ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1107bdea1361Sscw } 1108bdea1361Sscw } 1109bdea1361Sscw 1110bdea1361Sscw static void 1111816cf5b8Smsaitoh npeinit_macreg(struct npe_softc *sc) 1112bdea1361Sscw { 1113bdea1361Sscw 1114bdea1361Sscw /* 1115bdea1361Sscw * Reset MAC core. 1116bdea1361Sscw */ 1117bdea1361Sscw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1118bdea1361Sscw DELAY(NPE_MAC_RESET_DELAY); 1119bdea1361Sscw /* configure MAC to generate MDC clock */ 1120bdea1361Sscw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1121bdea1361Sscw 1122bdea1361Sscw /* disable transmitter and reciver in the MAC */ 1123bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL1, 1124bdea1361Sscw RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1125bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL1, 1126bdea1361Sscw RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1127bdea1361Sscw 1128bdea1361Sscw /* 1129bdea1361Sscw * Set the MAC core registers. 1130bdea1361Sscw */ 1131bdea1361Sscw WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1132bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1133bdea1361Sscw WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1134bdea1361Sscw /* thresholds determined by NPE firmware FS */ 1135bdea1361Sscw WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1136bdea1361Sscw WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1137a69b43feSmsaitoh WR4(sc, NPE_MAC_BUF_SIZE_TX, NPE_MAC_BUF_SIZE_TX_DEFAULT); 1138a69b43feSmsaitoh /* tx fifo threshold (bytes) */ 1139bdea1361Sscw WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1140bdea1361Sscw WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1141bdea1361Sscw WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1142bdea1361Sscw WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1143a69b43feSmsaitoh WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT); 1144a69b43feSmsaitoh /* assumes MII mode */ 1145bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL1, 1146bdea1361Sscw NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1147bdea1361Sscw | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1148bdea1361Sscw | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1149bdea1361Sscw | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1150bdea1361Sscw /* XXX pad strip? */ 1151bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL1, 1152bdea1361Sscw NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */ 1153bdea1361Sscw | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */ 1154bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1155816cf5b8Smsaitoh } 1156bdea1361Sscw 1157227ae4c9Smsaitoh static void 1158227ae4c9Smsaitoh npeinit_resetcb(void *xsc) 1159227ae4c9Smsaitoh { 1160227ae4c9Smsaitoh struct npe_softc *sc = xsc; 1161227ae4c9Smsaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1162227ae4c9Smsaitoh uint32_t msg[2]; 1163227ae4c9Smsaitoh 1164227ae4c9Smsaitoh ifp->if_oerrors++; 1165227ae4c9Smsaitoh npeinit_locked(sc); 1166227ae4c9Smsaitoh 1167227ae4c9Smsaitoh msg[0] = NPE_NOTIFYMACRECOVERYDONE << NPE_MAC_MSGID_SHL 1168227ae4c9Smsaitoh | (npeconfig[sc->sc_unit].macport << NPE_MAC_PORTID_SHL); 1169227ae4c9Smsaitoh msg[1] = 0; 1170227ae4c9Smsaitoh ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1171227ae4c9Smsaitoh } 1172227ae4c9Smsaitoh 1173816cf5b8Smsaitoh /* 1174816cf5b8Smsaitoh * Reset and initialize the chip 1175816cf5b8Smsaitoh */ 1176816cf5b8Smsaitoh static void 1177816cf5b8Smsaitoh npeinit_locked(void *xsc) 1178816cf5b8Smsaitoh { 1179816cf5b8Smsaitoh struct npe_softc *sc = xsc; 1180816cf5b8Smsaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1181816cf5b8Smsaitoh 1182816cf5b8Smsaitoh /* Cancel any pending I/O. */ 1183816cf5b8Smsaitoh npestop(ifp, 0); 1184816cf5b8Smsaitoh 1185816cf5b8Smsaitoh /* Reset the chip to a known state. */ 1186816cf5b8Smsaitoh npeinit_macreg(sc); 11876bc0c582Smatt npe_setmac(sc, CLLADDR(ifp->if_sadl)); 1188273cfb27Smsaitoh ether_mediachange(ifp); 1189bdea1361Sscw npe_setmcast(sc); 1190bdea1361Sscw 1191bdea1361Sscw npe_startxmit(sc); 1192bdea1361Sscw npe_startrecv(sc); 1193bdea1361Sscw 1194bdea1361Sscw ifp->if_flags |= IFF_RUNNING; 1195bdea1361Sscw ifp->if_flags &= ~IFF_OACTIVE; 1196bdea1361Sscw ifp->if_timer = 0; /* just in case */ 1197bdea1361Sscw 1198bdea1361Sscw /* enable transmitter and reciver in the MAC */ 1199bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL1, 1200bdea1361Sscw RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1201bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL1, 1202bdea1361Sscw RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1203bdea1361Sscw 1204bdea1361Sscw callout_reset(&sc->sc_tick_ch, hz, npe_tick, sc); 1205bdea1361Sscw } 1206bdea1361Sscw 1207bdea1361Sscw static int 1208bdea1361Sscw npeinit(struct ifnet *ifp) 1209bdea1361Sscw { 1210bdea1361Sscw struct npe_softc *sc = ifp->if_softc; 1211bdea1361Sscw int s; 1212bdea1361Sscw 1213bdea1361Sscw s = splnet(); 1214bdea1361Sscw npeinit_locked(sc); 1215bdea1361Sscw splx(s); 1216bdea1361Sscw 1217bdea1361Sscw return (0); 1218bdea1361Sscw } 1219bdea1361Sscw 1220bdea1361Sscw /* 1221bdea1361Sscw * Defragment an mbuf chain, returning at most maxfrags separate 1222bdea1361Sscw * mbufs+clusters. If this is not possible NULL is returned and 12237d1220acSsnj * the original mbuf chain is left in its present (potentially 1224bdea1361Sscw * modified) state. We use two techniques: collapsing consecutive 1225bdea1361Sscw * mbufs and replacing consecutive mbufs by a cluster. 1226bdea1361Sscw */ 1227bdea1361Sscw static __inline struct mbuf * 1228bdea1361Sscw npe_defrag(struct mbuf *m0) 1229bdea1361Sscw { 1230bdea1361Sscw struct mbuf *m; 1231bdea1361Sscw 1232bdea1361Sscw MGETHDR(m, M_DONTWAIT, MT_DATA); 1233bdea1361Sscw if (m == NULL) 1234bdea1361Sscw return (NULL); 12354f37cd5cSmaxv m_copy_pkthdr(m, m0); 1236bdea1361Sscw 1237bdea1361Sscw if ((m->m_len = m0->m_pkthdr.len) > MHLEN) { 1238bdea1361Sscw MCLGET(m, M_DONTWAIT); 1239bdea1361Sscw if ((m->m_flags & M_EXT) == 0) { 1240bdea1361Sscw m_freem(m); 1241bdea1361Sscw return (NULL); 1242bdea1361Sscw } 1243bdea1361Sscw } 1244bdea1361Sscw 124553524e44Schristos m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1246bdea1361Sscw m_freem(m0); 1247bdea1361Sscw 1248bdea1361Sscw return (m); 1249bdea1361Sscw } 1250bdea1361Sscw 1251bdea1361Sscw /* 1252bdea1361Sscw * Dequeue packets and place on the h/w transmit queue. 1253bdea1361Sscw */ 1254bdea1361Sscw static void 1255bdea1361Sscw npestart(struct ifnet *ifp) 1256bdea1361Sscw { 1257bdea1361Sscw struct npe_softc *sc = ifp->if_softc; 1258bdea1361Sscw struct npebuf *npe; 1259bdea1361Sscw struct npehwbuf *hw; 1260bdea1361Sscw struct mbuf *m, *n; 1261bdea1361Sscw bus_dma_segment_t *segs; 1262bdea1361Sscw int nseg, len, error, i; 1263bdea1361Sscw uint32_t next; 1264bdea1361Sscw 1265816cf5b8Smsaitoh if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1266bdea1361Sscw return; 1267bdea1361Sscw 1268bdea1361Sscw while (sc->tx_free != NULL) { 1269bdea1361Sscw IFQ_DEQUEUE(&ifp->if_snd, m); 1270816cf5b8Smsaitoh if (m == NULL) 1271816cf5b8Smsaitoh break; 1272bdea1361Sscw npe = sc->tx_free; 1273bdea1361Sscw error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, m, 1274bdea1361Sscw BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1275bdea1361Sscw if (error == EFBIG) { 1276bdea1361Sscw n = npe_defrag(m); 1277bdea1361Sscw if (n == NULL) { 1278bdea1361Sscw printf("%s: %s: too many fragments\n", 1279e20bd029Smatt device_xname(sc->sc_dev), __func__); 1280bdea1361Sscw m_freem(m); 1281bdea1361Sscw return; /* XXX? */ 1282bdea1361Sscw } 1283bdea1361Sscw m = n; 1284bdea1361Sscw error = bus_dmamap_load_mbuf(sc->sc_dt, npe->ix_map, 1285bdea1361Sscw m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1286bdea1361Sscw } 1287bdea1361Sscw if (error != 0) { 1288bdea1361Sscw printf("%s: %s: error %u\n", 1289e20bd029Smatt device_xname(sc->sc_dev), __func__, error); 1290bdea1361Sscw m_freem(m); 1291bdea1361Sscw return; /* XXX? */ 1292bdea1361Sscw } 1293bdea1361Sscw sc->tx_free = npe->ix_next; 1294bdea1361Sscw 1295bdea1361Sscw /* 1296bdea1361Sscw * Tap off here if there is a bpf listener. 1297bdea1361Sscw */ 12988517c9d1Smsaitoh bpf_mtap(ifp, m, BPF_D_OUT); 1299bdea1361Sscw 1300bdea1361Sscw bus_dmamap_sync(sc->sc_dt, npe->ix_map, 0, 1301bdea1361Sscw npe->ix_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1302bdea1361Sscw 1303bdea1361Sscw npe->ix_m = m; 1304bdea1361Sscw hw = npe->ix_hw; 1305bdea1361Sscw len = m->m_pkthdr.len; 1306bdea1361Sscw nseg = npe->ix_map->dm_nsegs; 1307bdea1361Sscw segs = npe->ix_map->dm_segs; 1308bdea1361Sscw next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1309bdea1361Sscw for (i = 0; i < nseg; i++) { 1310bdea1361Sscw hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1311bdea1361Sscw hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1312bdea1361Sscw hw->ix_ne[i].next = htobe32(next); 1313bdea1361Sscw 1314bdea1361Sscw len = 0; /* zero for segments > 1 */ 1315bdea1361Sscw next += sizeof(hw->ix_ne[0]); 1316bdea1361Sscw } 1317bdea1361Sscw hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1318bdea1361Sscw /* XXX flush descriptor instead of using uncached memory */ 1319bdea1361Sscw 1320bdea1361Sscw DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1321bdea1361Sscw __func__, sc->tx_qid, npe->ix_neaddr, 1322bdea1361Sscw hw->ix_ne[0].data, hw->ix_ne[0].len); 1323bdea1361Sscw /* stick it on the tx q */ 1324bdea1361Sscw /* XXX add vlan priority */ 1325bdea1361Sscw ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1326bdea1361Sscw 1327bdea1361Sscw ifp->if_timer = 5; 1328bdea1361Sscw } 1329bdea1361Sscw if (sc->tx_free == NULL) 1330bdea1361Sscw ifp->if_flags |= IFF_OACTIVE; 1331bdea1361Sscw } 1332bdea1361Sscw 1333bdea1361Sscw static void 1334bdea1361Sscw npe_stopxmit(struct npe_softc *sc) 1335bdea1361Sscw { 1336bdea1361Sscw struct npedma *dma = &sc->txdma; 1337bdea1361Sscw int i; 1338bdea1361Sscw 1339bdea1361Sscw /* XXX qmgr */ 1340bdea1361Sscw for (i = 0; i < dma->nbuf; i++) { 1341bdea1361Sscw struct npebuf *npe = &dma->buf[i]; 1342bdea1361Sscw 1343bdea1361Sscw if (npe->ix_m != NULL) { 1344bdea1361Sscw bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1345bdea1361Sscw m_freem(npe->ix_m); 1346bdea1361Sscw npe->ix_m = NULL; 1347bdea1361Sscw } 1348bdea1361Sscw } 1349bdea1361Sscw } 1350bdea1361Sscw 1351bdea1361Sscw static void 1352bdea1361Sscw npe_stoprecv(struct npe_softc *sc) 1353bdea1361Sscw { 1354bdea1361Sscw struct npedma *dma = &sc->rxdma; 1355bdea1361Sscw int i; 1356bdea1361Sscw 1357bdea1361Sscw /* XXX qmgr */ 1358bdea1361Sscw for (i = 0; i < dma->nbuf; i++) { 1359bdea1361Sscw struct npebuf *npe = &dma->buf[i]; 1360bdea1361Sscw 1361bdea1361Sscw if (npe->ix_m != NULL) { 1362bdea1361Sscw bus_dmamap_unload(sc->sc_dt, npe->ix_map); 1363bdea1361Sscw m_freem(npe->ix_m); 1364bdea1361Sscw npe->ix_m = NULL; 1365bdea1361Sscw } 1366bdea1361Sscw } 1367bdea1361Sscw } 1368bdea1361Sscw 1369bdea1361Sscw /* 1370bdea1361Sscw * Turn off interrupts, and stop the nic. 1371bdea1361Sscw */ 1372bdea1361Sscw void 1373bdea1361Sscw npestop(struct ifnet *ifp, int disable) 1374bdea1361Sscw { 1375bdea1361Sscw struct npe_softc *sc = ifp->if_softc; 1376bdea1361Sscw 1377bdea1361Sscw /* disable transmitter and reciver in the MAC */ 1378bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL1, 1379bdea1361Sscw RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1380bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL1, 1381bdea1361Sscw RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1382bdea1361Sscw 1383bdea1361Sscw callout_stop(&sc->sc_tick_ch); 1384bdea1361Sscw 1385bdea1361Sscw npe_stopxmit(sc); 1386bdea1361Sscw npe_stoprecv(sc); 1387bdea1361Sscw /* XXX go into loopback & drain q's? */ 1388bdea1361Sscw /* XXX but beware of disabling tx above */ 1389bdea1361Sscw 1390bdea1361Sscw /* 1391bdea1361Sscw * The MAC core rx/tx disable may leave the MAC hardware in an 1392bdea1361Sscw * unpredictable state. A hw reset is executed before resetting 1393bdea1361Sscw * all the MAC parameters to a known value. 1394bdea1361Sscw */ 1395bdea1361Sscw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1396bdea1361Sscw DELAY(NPE_MAC_RESET_DELAY); 1397bdea1361Sscw WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1398bdea1361Sscw WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1399816cf5b8Smsaitoh 1400816cf5b8Smsaitoh ifp->if_timer = 0; 1401816cf5b8Smsaitoh ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1402bdea1361Sscw } 1403bdea1361Sscw 1404bdea1361Sscw void 1405bdea1361Sscw npewatchdog(struct ifnet *ifp) 1406bdea1361Sscw { 1407bdea1361Sscw struct npe_softc *sc = ifp->if_softc; 1408bdea1361Sscw int s; 1409bdea1361Sscw 1410e20bd029Smatt aprint_error_dev(sc->sc_dev, "device timeout\n"); 1411bdea1361Sscw s = splnet(); 1412bdea1361Sscw ifp->if_oerrors++; 1413bdea1361Sscw npeinit_locked(sc); 1414bdea1361Sscw splx(s); 1415bdea1361Sscw } 1416bdea1361Sscw 1417bdea1361Sscw static int 141853524e44Schristos npeioctl(struct ifnet *ifp, u_long cmd, void *data) 1419bdea1361Sscw { 1420bdea1361Sscw struct npe_softc *sc = ifp->if_softc; 1421816cf5b8Smsaitoh struct ifreq *ifr = (struct ifreq *) data; 1422bdea1361Sscw int s, error = 0; 1423bdea1361Sscw 1424bdea1361Sscw s = splnet(); 1425bdea1361Sscw 1426816cf5b8Smsaitoh switch (cmd) { 1427816cf5b8Smsaitoh case SIOCSIFMEDIA: 1428816cf5b8Smsaitoh case SIOCGIFMEDIA: 1429816cf5b8Smsaitoh #if 0 /* not yet */ 1430816cf5b8Smsaitoh /* Flow control requires full-duplex mode. */ 1431816cf5b8Smsaitoh if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1432816cf5b8Smsaitoh (ifr->ifr_media & IFM_FDX) == 0) 1433816cf5b8Smsaitoh ifr->ifr_media &= ~IFM_ETH_FMASK; 1434816cf5b8Smsaitoh if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1435816cf5b8Smsaitoh if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1436816cf5b8Smsaitoh /* We can do both TXPAUSE and RXPAUSE. */ 1437816cf5b8Smsaitoh ifr->ifr_media |= 1438816cf5b8Smsaitoh IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1439816cf5b8Smsaitoh } 1440816cf5b8Smsaitoh sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1441816cf5b8Smsaitoh } 1442816cf5b8Smsaitoh #endif 1443816cf5b8Smsaitoh error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1444816cf5b8Smsaitoh break; 1445816cf5b8Smsaitoh case SIOCSIFFLAGS: 1446816cf5b8Smsaitoh if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == IFF_RUNNING) { 1447816cf5b8Smsaitoh /* 1448816cf5b8Smsaitoh * If interface is marked down and it is running, 1449816cf5b8Smsaitoh * then stop and disable it. 1450816cf5b8Smsaitoh */ 1451816cf5b8Smsaitoh (*ifp->if_stop)(ifp, 1); 1452816cf5b8Smsaitoh } else if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == IFF_UP) { 1453816cf5b8Smsaitoh /* 1454816cf5b8Smsaitoh * If interface is marked up and it is stopped, then 1455816cf5b8Smsaitoh * start it. 1456816cf5b8Smsaitoh */ 1457816cf5b8Smsaitoh error = (*ifp->if_init)(ifp); 1458816cf5b8Smsaitoh } else if ((ifp->if_flags & IFF_UP) != 0) { 1459816cf5b8Smsaitoh int diff; 1460816cf5b8Smsaitoh 1461816cf5b8Smsaitoh /* Up (AND RUNNING). */ 1462816cf5b8Smsaitoh 1463816cf5b8Smsaitoh diff = (ifp->if_flags ^ sc->sc_if_flags) 1464816cf5b8Smsaitoh & (IFF_PROMISC|IFF_ALLMULTI); 1465816cf5b8Smsaitoh if ((diff & (IFF_PROMISC|IFF_ALLMULTI)) != 0) { 1466816cf5b8Smsaitoh /* 1467816cf5b8Smsaitoh * If the difference bettween last flag and 1468816cf5b8Smsaitoh * new flag only IFF_PROMISC or IFF_ALLMULTI, 1469816cf5b8Smsaitoh * set multicast filter only (don't reset to 1470816cf5b8Smsaitoh * prevent link down). 1471816cf5b8Smsaitoh */ 1472816cf5b8Smsaitoh npe_setmcast(sc); 1473816cf5b8Smsaitoh } else { 1474816cf5b8Smsaitoh /* 1475816cf5b8Smsaitoh * Reset the interface to pick up changes in 1476816cf5b8Smsaitoh * any other flags that affect the hardware 1477816cf5b8Smsaitoh * state. 1478816cf5b8Smsaitoh */ 1479816cf5b8Smsaitoh error = (*ifp->if_init)(ifp); 1480816cf5b8Smsaitoh } 1481816cf5b8Smsaitoh } 1482816cf5b8Smsaitoh sc->sc_if_flags = ifp->if_flags; 1483816cf5b8Smsaitoh break; 1484816cf5b8Smsaitoh default: 1485bdea1361Sscw error = ether_ioctl(ifp, cmd, data); 1486bdea1361Sscw if (error == ENETRESET) { 1487816cf5b8Smsaitoh /* 1488816cf5b8Smsaitoh * Multicast list has changed; set the hardware filter 1489816cf5b8Smsaitoh * accordingly. 1490816cf5b8Smsaitoh */ 1491816cf5b8Smsaitoh npe_setmcast(sc); 1492bdea1361Sscw error = 0; 1493bdea1361Sscw } 1494816cf5b8Smsaitoh } 1495bdea1361Sscw 1496bdea1361Sscw npestart(ifp); 1497bdea1361Sscw 1498bdea1361Sscw splx(s); 1499bdea1361Sscw return error; 1500bdea1361Sscw } 1501bdea1361Sscw 1502bdea1361Sscw /* 1503bdea1361Sscw * Setup a traffic class -> rx queue mapping. 1504bdea1361Sscw */ 1505bdea1361Sscw static int 1506bdea1361Sscw npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1507bdea1361Sscw { 1508bdea1361Sscw int npeid = npeconfig[sc->sc_unit].npeid; 1509bdea1361Sscw uint32_t msg[2]; 1510bdea1361Sscw 1511273cfb27Smsaitoh msg[0] = (NPE_SETRXQOSENTRY << NPE_MAC_MSGID_SHL) | (npeid << 20) 1512273cfb27Smsaitoh | classix; 1513bdea1361Sscw msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1514bdea1361Sscw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1515bdea1361Sscw } 1516bdea1361Sscw 1517bdea1361Sscw /* 1518bdea1361Sscw * Update and reset the statistics in the NPE. 1519bdea1361Sscw */ 1520bdea1361Sscw static int 1521bdea1361Sscw npe_updatestats(struct npe_softc *sc) 1522bdea1361Sscw { 1523bdea1361Sscw uint32_t msg[2]; 1524bdea1361Sscw 1525bdea1361Sscw msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1526bdea1361Sscw msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1527bdea1361Sscw return ixpnpe_sendmsg(sc->sc_npe, msg); /* NB: no recv */ 1528bdea1361Sscw } 1529bdea1361Sscw 1530bdea1361Sscw #if 0 1531bdea1361Sscw /* 1532bdea1361Sscw * Get the current statistics block. 1533bdea1361Sscw */ 1534bdea1361Sscw static int 1535bdea1361Sscw npe_getstats(struct npe_softc *sc) 1536bdea1361Sscw { 1537bdea1361Sscw uint32_t msg[2]; 1538bdea1361Sscw 1539bdea1361Sscw msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1540bdea1361Sscw msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1541bdea1361Sscw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1542bdea1361Sscw } 1543bdea1361Sscw 1544bdea1361Sscw /* 1545bdea1361Sscw * Query the image id of the loaded firmware. 1546bdea1361Sscw */ 1547bdea1361Sscw static uint32_t 1548bdea1361Sscw npe_getimageid(struct npe_softc *sc) 1549bdea1361Sscw { 1550bdea1361Sscw uint32_t msg[2]; 1551bdea1361Sscw 1552bdea1361Sscw msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1553bdea1361Sscw msg[1] = 0; 1554bdea1361Sscw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1555bdea1361Sscw } 1556bdea1361Sscw 1557bdea1361Sscw /* 1558bdea1361Sscw * Enable/disable loopback. 1559bdea1361Sscw */ 1560bdea1361Sscw static int 1561bdea1361Sscw npe_setloopback(struct npe_softc *sc, int ena) 1562bdea1361Sscw { 1563bdea1361Sscw uint32_t msg[2]; 1564bdea1361Sscw 1565bdea1361Sscw msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1566bdea1361Sscw msg[1] = 0; 1567bdea1361Sscw return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1568bdea1361Sscw } 1569bdea1361Sscw #endif 1570bdea1361Sscw 1571bdea1361Sscw /* 1572bdea1361Sscw * MII bus support routines. 1573bdea1361Sscw * 1574bdea1361Sscw * NB: ixp425 has one PHY per NPE 1575bdea1361Sscw */ 1576bdea1361Sscw static uint32_t 1577bdea1361Sscw npe_mii_mdio_read(struct npe_softc *sc, int reg) 1578bdea1361Sscw { 1579bdea1361Sscw #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1580bdea1361Sscw uint32_t v; 1581bdea1361Sscw 1582bdea1361Sscw /* NB: registers are known to be sequential */ 1583bdea1361Sscw v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1584bdea1361Sscw v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1585bdea1361Sscw v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1586bdea1361Sscw v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1587bdea1361Sscw return v; 1588bdea1361Sscw #undef MII_RD4 1589bdea1361Sscw } 1590bdea1361Sscw 1591bdea1361Sscw static void 1592bdea1361Sscw npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1593bdea1361Sscw { 1594bdea1361Sscw #define MII_WR4(sc, reg, v) \ 1595bdea1361Sscw bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1596bdea1361Sscw 1597bdea1361Sscw /* NB: registers are known to be sequential */ 1598bdea1361Sscw MII_WR4(sc, reg+0, cmd & 0xff); 1599bdea1361Sscw MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1600bdea1361Sscw MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1601bdea1361Sscw MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1602bdea1361Sscw #undef MII_WR4 1603bdea1361Sscw } 1604bdea1361Sscw 1605bdea1361Sscw static int 1606bdea1361Sscw npe_mii_mdio_wait(struct npe_softc *sc) 1607bdea1361Sscw { 1608bdea1361Sscw #define MAXTRIES 100 /* XXX */ 1609bdea1361Sscw uint32_t v; 1610bdea1361Sscw int i; 1611bdea1361Sscw 1612bdea1361Sscw for (i = 0; i < MAXTRIES; i++) { 1613bdea1361Sscw v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1614bdea1361Sscw if ((v & NPE_MII_GO) == 0) 1615*e746222fSmsaitoh return 0; 1616bdea1361Sscw } 1617*e746222fSmsaitoh return ETIMEDOUT; 1618bdea1361Sscw #undef MAXTRIES 1619bdea1361Sscw } 1620bdea1361Sscw 1621bdea1361Sscw static int 1622*e746222fSmsaitoh npe_miibus_readreg(device_t self, int phy, int reg, uint16_t *val) 1623bdea1361Sscw { 1624e20bd029Smatt struct npe_softc *sc = device_private(self); 1625bdea1361Sscw uint32_t v; 1626bdea1361Sscw 1627bdea1361Sscw if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1628*e746222fSmsaitoh return -1; 1629bdea1361Sscw v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1630bdea1361Sscw | NPE_MII_GO; 1631bdea1361Sscw npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1632*e746222fSmsaitoh if (npe_mii_mdio_wait(sc) == 0) 1633bdea1361Sscw v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1634bdea1361Sscw else 1635bdea1361Sscw v = 0xffff | NPE_MII_READ_FAIL; 1636*e746222fSmsaitoh 1637*e746222fSmsaitoh if ((v & NPE_MII_READ_FAIL) != 0) 1638*e746222fSmsaitoh return -1; 1639*e746222fSmsaitoh 1640*e746222fSmsaitoh *val = v & 0xffff; 1641*e746222fSmsaitoh return 0; 1642bdea1361Sscw #undef MAXTRIES 1643bdea1361Sscw } 1644bdea1361Sscw 1645*e746222fSmsaitoh static int 1646*e746222fSmsaitoh npe_miibus_writereg(device_t self, int phy, int reg, uint16_t val) 1647bdea1361Sscw { 1648e20bd029Smatt struct npe_softc *sc = device_private(self); 1649bdea1361Sscw uint32_t v; 1650bdea1361Sscw 1651bdea1361Sscw if (sc->sc_phy > IXPNPECF_PHY_DEFAULT && phy != sc->sc_phy) 1652*e746222fSmsaitoh return -1; 1653bdea1361Sscw v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1654*e746222fSmsaitoh | val | NPE_MII_WRITE 1655bdea1361Sscw | NPE_MII_GO; 1656bdea1361Sscw npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1657*e746222fSmsaitoh 1658*e746222fSmsaitoh return npe_mii_mdio_wait(sc); 1659bdea1361Sscw } 1660bdea1361Sscw 1661bdea1361Sscw static void 1662e20bd029Smatt npe_miibus_statchg(struct ifnet *ifp) 1663bdea1361Sscw { 1664e20bd029Smatt struct npe_softc *sc = ifp->if_softc; 1665bdea1361Sscw uint32_t tx1, rx1; 1666227ae4c9Smsaitoh uint32_t randoff; 1667bdea1361Sscw 1668bdea1361Sscw /* sync MAC duplex state */ 1669bdea1361Sscw tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1670bdea1361Sscw rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1671bdea1361Sscw if (sc->sc_mii.mii_media_active & IFM_FDX) { 1672227ae4c9Smsaitoh WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT); 1673bdea1361Sscw tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1674bdea1361Sscw rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1675bdea1361Sscw } else { 1676227ae4c9Smsaitoh struct timeval now; 1677227ae4c9Smsaitoh getmicrotime(&now); 1678227ae4c9Smsaitoh randoff = (RD4(sc, NPE_MAC_UNI_ADDR_6) ^ now.tv_usec) 1679227ae4c9Smsaitoh & 0x7f; 1680227ae4c9Smsaitoh WR4(sc, NPE_MAC_SLOT_TIME, NPE_MAC_SLOT_TIME_MII_DEFAULT 1681227ae4c9Smsaitoh + randoff); 1682bdea1361Sscw tx1 |= NPE_TX_CNTRL1_DUPLEX; 1683bdea1361Sscw rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1684bdea1361Sscw } 1685bdea1361Sscw WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1686bdea1361Sscw WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1687bdea1361Sscw } 1688