1 /* $NetBSD: pxa2x0reg.h,v 1.1 2002/10/19 19:31:40 bsh Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Genetec Corporation. 19 * 4. The name of Genetec Corporation may not be used to endorse or 20 * promote products derived from this software without specific prior 21 * written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 37 /* 38 * Intel PXA2[15]0 processor is XScale based integrated CPU 39 * 40 * Reference: 41 * Intel(r) PXA250 and PXA210 Application Processors 42 * Developer's Manual 43 * (278522-001.pdf) 44 */ 45 #ifndef _ARM_XSCALE_PXA2X0REG_H_ 46 #define _ARM_XSCALE_PXA2X0REG_H_ 47 48 /* Borrow some register definitions from sa11x0 */ 49 #include <arm/sa11x0/sa11x0_reg.h> 50 51 #ifndef _LOCORE 52 #include <sys/types.h> /* for uint32_t */ 53 #endif 54 55 /* 56 * Chip select domains 57 */ 58 #define PXA2X0_CS0_START 0x00000000 59 #define PXA2X0_CS1_START 0x04000000 60 #define PXA2X0_CS2_START 0x08000000 61 #define PXA2X0_CS3_START 0x0c000000 62 #define PXA2X0_CS4_START 0x10000000 63 #define PXA2X0_CS5_START 0x14000000 64 65 #define PXA2X0_PCMCIA_SLOT0 0x20000000 66 #define PXA2X0_PCMCIA_SLOT1 0x30000000 67 68 #define PXA2X0_PERIPH_START 0x40000000 69 /* #define PXA2X0_MEMCTL_START 0x48000000 */ 70 #define PXA2X0_PERIPH_END 0x480fffff 71 72 #define PXA2X0_SDRAM0_START 0xa0000000 73 #define PXA2X0_SDRAM1_START 0xa4000000 74 #define PXA2X0_SDRAM2_START 0xa8000000 75 #define PXA2X0_SDRAM3_START 0xac000000 76 77 /* 78 * Physical address of integrated peripherals 79 */ 80 81 #define PXA2X0_DMAC_BASE 0x40000000 82 #define PXA2X0_DMAC_SIZE 0x300 83 #define PXA2X0_FFUART_BASE 0x40100000 /* Full Function UART */ 84 #define PXA2X0_BTUART_BASE 0x40200000 /* Bluetooth UART */ 85 #define PXA2X0_I2C_BASE 0x40300000 86 #define PXA2X0_I2C_SIZE 0x000016a4 87 #define PXA2X0_I2S_BASE 0x40400000 88 #define PXA2X0_AC97_BASE 0x40500000 89 #define PXA2X0_UDC_BASE 0x40600000 /* USB Client */ 90 #define PXA2X0_STUART_BASE 0x40700000 /* Standard UART */ 91 #define PXA2X0_ICP_BASE 0x40800000 92 #define PXA2X0_RTC_BASE 0x40900000 93 #define PXA2X0_RTC_SIZE 0x10 94 #define PXA2X0_OST_BASE 0x40a00000 /* OS Timer */ 95 #define PXA2X0_PWM0_BASE 0x40b00000 96 #define PXA2X0_PWM1_BASE 0x40c00000 97 #define PXA2X0_INTCTL_BASE 0x40d00000 /* Interrupt controller */ 98 #define PXA2X0_INTCTL_SIZE 0x20 99 #define PXA2X0_GPIO_BASE 0x40e00000 100 #define PXA2X0_GPIO_SIZE 0x70 101 #define PXA2X0_POWMAN_BASE 0x40f00000 /* Power management */ 102 #define PXA2X0_SSP_BASE 0x41000000 103 #define PXA2X0_MMC_BASE 0x41100000 /* MultiMediaCard */ 104 #define PXA2X0_CLKMAN_BASE 0x41300000 /* Clock Manager */ 105 #define PXA2X0_CLKMAN_SIZE 12 106 #define PXA2X0_LCDC_BASE 0x44000000 /* LCD Controller */ 107 #define PXA2X0_LCDC_SIZE 0x220 108 #define PXA2X0_MEMCTL_BASE 0x48000000 /* Memory Controller */ 109 #define PXA2X0_MEMCTL_SIZE 0x48 110 111 /* width of interrupt controller */ 112 #define ICU_LEN 32 /* but [0..7,15,16] is not used */ 113 #define ICU_INT_HWMASK 0xffffff00 114 #define PXA2X0_IRQ_MIN 8 /* 0..7 are not used by integrated 115 peripherals */ 116 117 /* UART */ 118 #define PXA2X0_COM_FREQ 14745600L 119 120 /* I2C */ 121 #define I2C_IBMR 0x1680 /* Bus monitor register */ 122 #define I2C_IDBR 0x1688 /* Data buffer */ 123 #define I2C_ICR 0x1690 /* Control register */ 124 #define ICR_START (1<<0) 125 #define ICR_STOP (1<<1) 126 #define ICR_ACKNAK (1<<2) 127 #define ICR_TB (1<<3) 128 #define ICR_MA (1<<4) 129 #define I2C_ISR 0x1698 /* Status register */ 130 #define I2C_ISAR 0x16a0 /* Slave address */ 131 132 /* Clock Manager */ 133 #define CLKMAN_CCCR 0x00 /* Core Clock Configuration */ 134 #define CCCR_TURBO_X1 (2<<7) 135 #define CCCR_TURBO_X15 (3<<7) /* x 1.5 */ 136 #define CCCR_TURBO_X2 (4<<7) 137 #define CCCR_TURBO_X25 (5<<7) /* x 2.5 */ 138 #define CCCR_TURBO_X3 (6<<7) /* x 3.0 */ 139 #define CCCR_RUN_X1 (1<<5) 140 #define CCCR_RUN_X2 (2<<5) 141 #define CCCR_RUN_X4 (3<<5) 142 #define CCCR_MEM_X27 (1<<0) /* x27, 99.53MHz */ 143 #define CCCR_MEM_X32 (2<<0) /* x32, 117,96MHz */ 144 #define CCCR_MEM_X36 (3<<0) /* x26, 132.71MHz */ 145 #define CCCR_MEM_X40 (4<<0) /* x27, 99.53MHz */ 146 #define CCCR_MEM_X45 (5<<0) /* x27, 99.53MHz */ 147 #define CCCR_MEM_X9 (0x1f<<0) /* x9, 33.2MHz */ 148 149 #define CLKMAN_CKEN 0x04 /* Clock Enable Register */ 150 #define CLKMAN_OSCC 0x08 /* Osillcator Configuration Register */ 151 152 #define CCCR_N_SHIFT 7 153 #define CCCR_N_MASK (0x07<<CCCR_N_SHIFT) 154 #define CCCR_M_SHIFT 5 155 #define CCCR_M_MASK (0x03<<CCCR_M_SHIFT) 156 #define CCCR_L_MASK 0x1f 157 158 #define CKEN_PWM0 (1<<0) 159 #define CKEN_PWM1 (1<<1) 160 #define CKEN_AC97 (1<<2) 161 #define CKEN_SSP (1<<3) 162 #define CKEN_STUART (1<<5) 163 #define CKEN_FFUART (1<<6) 164 #define CKEN_BTUART (1<<7) 165 #define CKEN_I2S (1<<8) 166 #define CKEN_USB (1<<11) 167 #define CKEN_MMC (1<<12) 168 #define CKEN_FICP (1<<13) 169 #define CKEN_I2C (1<<14) 170 #define CKEN_LCD (1<<16) 171 172 #define OSCC_OOK (1<<0) /* 32.768KHz oscillator status */ 173 #define OSCC_OON (1<<1) /* 32.768KHz oscillator */ 174 175 /* 176 * RTC 177 */ 178 #define RTC_RCNR 0x0000 /* count register */ 179 #define RTC_RTAR 0x0004 /* alarm register */ 180 #define RTC_RTSR 0x0008 /* status register */ 181 #define RTC_RTTR 0x000c /* trim register */ 182 /* 183 * GPIO 184 */ 185 #define GPIO_GPLR0 0x00 /* Level reg [31:0] */ 186 #define GPIO_GPLR1 0x04 /* Level reg [63:32] */ 187 #define GPIO_GPLR2 0x08 /* Level reg [80:64] */ 188 189 #define GPIO_GPDR0 0x0c /* dir reg [31:0] */ 190 #define GPIO_GPDR1 0x10 /* dir reg [63:32] */ 191 #define GPIO_GPDR2 0x14 /* dir reg [80:64] */ 192 193 #define GPIO_GPSR0 0x18 /* set reg [31:0] */ 194 #define GPIO_GPSR1 0x1c /* set reg [63:32] */ 195 #define GPIO_GPSR2 0x20 /* set reg [80:64] */ 196 197 #define GPIO_GPCR0 0x24 /* clear reg [31:0] */ 198 #define GPIO_GPCR1 0x28 /* clear reg [63:32] */ 199 #define GPIO_GPCR2 0x2c /* clear reg [80:64] */ 200 201 #define GPIO_GPER0 0x30 /* rising edge [31:0] */ 202 #define GPIO_GPER1 0x34 /* rising edge [63:32] */ 203 #define GPIO_GPER2 0x38 /* rising edge [80:64] */ 204 205 #define GPIO_GRER0 0x30 /* rising edge [31:0] */ 206 #define GPIO_GRER1 0x34 /* rising edge [63:32] */ 207 #define GPIO_GRER2 0x38 /* rising edge [80:64] */ 208 209 #define GPIO_GFER0 0x3c /* falling edge [31:0] */ 210 #define GPIO_GFER1 0x40 /* falling edge [63:32] */ 211 #define GPIO_GFER2 0x44 /* falling edge [80:64] */ 212 213 #define GPIO_GEDR0 0x48 /* edge detect [31:0] */ 214 #define GPIO_GEDR1 0x4c /* edge detect [63:32] */ 215 #define GPIO_GEDR2 0x50 /* edge detect [80:64] */ 216 217 #define GPIO_GAFR0_L 0x54 /* alternate function [15:0] */ 218 #define GPIO_GAFR0_U 0x58 /* alternate function [31:16] */ 219 #define GPIO_GAFR1_L 0x5c /* alternate function [47:32] */ 220 #define GPIO_GAFR1_U 0x60 /* alternate function [63:48] */ 221 #define GPIO_GAFR2_L 0x64 /* alternate function [79:64] */ 222 #define GPIO_GAFR2_U 0x68 /* alternate function [80] */ 223 224 /* 225 * memory controller 226 */ 227 228 #define MEMCTL_MDCNFG 0x0000 229 #define MDCNFG_DE0 (1<<0) 230 #define MDCNFG_DE1 (1<<1) 231 #define MDCNFG_DE2 (1<<16) 232 #define MDCNFG_DE3 (1<<17) 233 234 #define MEMCTL_MDREFR 0x04 /* refresh control register */ 235 #define MDREFR_DRI 0xfff 236 #define MDREFR_E0PIN (1<<12) 237 #define MDREFR_K0RUN (1<<13) /* SDCLK0 enable */ 238 #define MDREFR_K0DB2 (1<<14) /* SDCLK0 1/2 freq */ 239 #define MDREFR_E1PIN (1<<15) 240 #define MDREFR_K1RUN (1<<16) /* SDCLK1 enable */ 241 #define MDREFR_K1DB2 (1<<17) /* SDCLK1 1/2 freq */ 242 #define MDREFR_K2RUN (1<<18) /* SDCLK2 enable */ 243 #define MDREFR_K2DB2 (1<<19) /* SDCLK2 1/2 freq */ 244 #define MDREFR_APD (1<<20) /* Auto Power Down */ 245 #define MDREFR_SLFRSH (1<<22) /* Self Refresh */ 246 #define MDREFR_K0FREE (1<<23) /* SDCLK0 free run */ 247 #define MDREFR_K1FREE (1<<24) /* SDCLK1 free run */ 248 #define MDREFR_K2FREE (1<<25) /* SDCLK2 free run */ 249 250 #define MEMCTL_MSC0 0x08 /* Asychronous Statis memory Control CS[01] */ 251 #define MEMCTL_MSC1 0x0c /* Asychronous Statis memory Control CS[23] */ 252 #define MEMCTL_MSC2 0x10 /* Asychronous Statis memory Control CS[45] */ 253 #define MSC2_RBUFF_SHIFT 15 /* return data buffer */ 254 #define MSC2_RBUFF (1<<MSC2_RBUFF_SHIFT) 255 #define MSC2_RRR_SHIFT 12 /* recovery time */ 256 #define MSC2_RRR (7<<MSC2_RRR_SHIFT) 257 #define MSC2_RDN_SHIFT 8 /* ROM delay next access */ 258 #define MSC2_RDN (0x0f<<MSC2_RDN_SHIFT) 259 #define MSC2_RDF_SHIFT 4 /* ROM delay first access*/ 260 #define MSC2_RDF (0x0f<<MSC2_RDF_SHIFT) 261 #define MSC2_RBW_SHIFT 3 /* 32/16 bit bus */ 262 #define MSC2_RBW (1<<MSC2_RBW_SHIFT) 263 #define MSC2_RT_SHIFT 0 /* type */ 264 #define MSC2_RT (7<<MSC2_RT_SHIFT) 265 #define MSC2_RT_NONBURST 0 266 #define MSC2_RT_SRAM 1 267 #define MSC2_RT_BURST4 2 268 #define MSC2_RT_BURST8 3 269 #define MSC2_RT_VLIO 4 270 271 #define MEMCTL_MCMEM0 0x28 /* expansion memory timing configuration */ 272 #define MEMCTL_MCMEM1 0x2c /* expansion memory timing configuration */ 273 #define MEMCTL_MCATT0 0x30 274 #define MEMCTL_MCATT1 0x34 275 #define MEMCTL_MCIO0 0x38 276 #define MEMCTL_MCIO1 0x3c 277 278 #define MEMCTL_MECR 0x14 /* Expansion memory configuration */ 279 #define MECR_NOS (1<<0) /* Number of sockets */ 280 #define MECR_CIT (1<<1) /* Card-is-there */ 281 282 #define MEMCTL_MDMRS 0x0040 283 284 /* 285 * LCD Controller 286 */ 287 #define LCDC_LCCR0 0x000 /* Controller Control Register 0 */ 288 #define LCCR0_ENB (1U<<0) /* LCD Controller Enable */ 289 #define LCCR0_CMS (1U<<1) /* Color/Mono select */ 290 #define LCCR0_SDS (1U<<2) /* Single/Dual -panel */ 291 #define LCCR0_LDM (1U<<3) /* LCD Disable Done Mask */ 292 #define LCCR0_SFM (1U<<4) /* Start of Frame Mask */ 293 #define LCCR0_IUM (1U<<5) /* Input FIFO Underrun Mask */ 294 #define LCCR0_EFM (1U<<6) /* End of Frame Mask */ 295 #define LCCR0_PAS (1U<<7) /* Passive/Active Display select */ 296 #define LCCR0_DPD (1U<<9) /* Double-Pixel Data pin mode */ 297 #define LCCR0_DIS (1U<<10) /* LCD Disable */ 298 #define LCCR0_QDM (1U<<11) /* LCD Quick Disable Mask */ 299 #define LCCR0_BM (1U<<20) /* Branch Mask */ 300 #define LCCR0_OUM (1U<<21) /* Output FIFO Underrun Mask */ 301 302 #define LCCR0_IMASK (LCCR0_LDM|LCCR0_SFM|LCCR0_IUM|LCCR0_EFM|LCCR0_QDM|LCCR0_BM|LCCR0_OUM) 303 304 305 #define LCDC_LCCR1 0x004 /* Controller Control Register 1 */ 306 #define LCDC_LCCR2 0x008 /* Controller Control Register 2 */ 307 #define LCDC_LCCR3 0x00c /* Controller Control Register 2 */ 308 #define LCCR3_BPP_SHIFT 24 /* Bits per pixel */ 309 #define LCCR3_BPP (0x07<<LCCR3_BPP_SHIFT) 310 #define LCDC_FBR0 0x020 /* DMA ch0 frame branch register */ 311 #define LCDC_FBR1 0x024 /* DMA ch1 frame branch register */ 312 #define LCDC_LCSR 0x038 /* controller status register */ 313 #define LCSR_LDD (1U<<0) /* LCD disable done */ 314 #define LCSR_SOF (1U<<1) /* Start of frame */ 315 #define LCDC_LIIDR 0x03c /* controller interrupt ID Register */ 316 #define LCDC_TRGBR 0x040 /* TMED RGB Speed Register */ 317 #define LCDC_TCR 0x044 /* TMED Control Register */ 318 #define LCDC_FDADR0 0x200 /* DMA ch0 frame descriptor address */ 319 #define LCDC_FSADR0 0x204 /* DMA ch0 frame source address */ 320 #define LCDC_FIDR0 0x208 /* DMA ch0 frame ID register */ 321 #define LCDC_LDCMD0 0x20c /* DMA ch0 command register */ 322 #define LCDC_FDADR1 0x210 /* DMA ch1 frame descriptor address */ 323 #define LCDC_FSADR1 0x214 /* DMA ch1 frame source address */ 324 #define LCDC_FIDR1 0x218 /* DMA ch1 frame ID register */ 325 #define LCDC_LDCMD1 0x21c /* DMA ch1 command register */ 326 327 #endif /* _ARM_XSCALE_PXA2X0REG_H_ */ 328