1 /* $NetBSD: xscalereg.h,v 1.1 2002/03/26 19:29:46 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _ARM_XSCALE_XSCALEREG_H_ 39 #define _ARM_XSCALE_XSCALEREG_H_ 40 41 /* 42 * Register definitions for the Intel XScale processor core. 43 */ 44 45 /* 46 * Performance Monitoring Unit (CP14) 47 * 48 * CP14.0 Performance Monitor Control Register 49 * CP14.1 Clock Counter 50 * CP14.2 Performance Counter Register 0 51 * CP14.3 Performance Counter Register 1 52 */ 53 54 #define PMNC_E 0x00000001 /* enable counters */ 55 #define PMNC_P 0x00000002 /* reset both PMNs to 0 */ 56 #define PMNC_C 0x00000004 /* clock counter reset */ 57 #define PMNC_D 0x00000008 /* clock counter / 64 */ 58 #define PMNC_PMN0_IE 0x00000010 /* enable PMN0 interrupt */ 59 #define PMNC_PMN1_IE 0x00000020 /* enable PMN1 interrupt */ 60 #define PMNC_CC_IE 0x00000040 /* enable clock counter interrupt */ 61 #define PMNC_PMN0_IF 0x00000100 /* PMN0 overflow/interrupt */ 62 #define PMNC_PMN1_IF 0x00000200 /* PMN1 overflow/interrupt */ 63 #define PMNC_CC_IF 0x00000400 /* clock counter overflow/interrupt */ 64 #define PMNC_EVCNT0_MASK 0x000ff000 /* event to count for PMN0 */ 65 #define PMNC_EVCNT0_SHIFT 12 66 #define PMNC_EVCNT1_MASK 0x0ff00000 /* event to count for PMN1 */ 67 #define PMNC_EVCNT1_SHIFT 20 68 69 #endif /* _ARM_XSCALE_XSCALEREG_H_ */ 70