1 /* $NetBSD: fdreg.h,v 1.2 1995/04/22 22:18:21 leo Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Leo Weppelman. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Leo Weppelman. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _FDREG_H 34 #define _FDREG_H 35 /* 36 * Atari TT hardware: 37 * Western Digital 1772 Floppy Disk Controller. 38 */ 39 40 /* 41 * Accessing the FDC registers is indirect through ST-specific 42 * DMA circuitry. See also dma.h. 43 */ 44 #define FDC_CS (DMA_FDC ) /* command/status */ 45 #define FDC_TR (DMA_FDC| DMA_A0) /* track register */ 46 #define FDC_SR (DMA_FDC|DMA_A1 ) /* sector register */ 47 #define FDC_DR (DMA_FDC|DMA_A1|DMA_A0) /* data register */ 48 49 /* 50 * commands (relevant bits/fields indicated) 51 */ 52 #define RESTORE 0x00 /* ( HVRR) seek to track 0 */ 53 #define SEEK 0x10 /* ( HVRR) seek to track */ 54 #define STEP 0x20 /* (UHVRR) step in same direction */ 55 #define STEPI 0x40 /* (UHVRR) step in */ 56 #define STEPO 0x60 /* (UHVRR) step out */ 57 #define F_READ 0x80 /* (MHE00) read sector */ 58 #define F_WRITE 0xA0 /* (MHEPA) write sector */ 59 #define READID 0xC0 /* ( HE00) read sector ID */ 60 #define READTR 0xE0 /* ( HE00) read track */ 61 #define WRITETR 0xF0 /* ( HEP0) write track */ 62 #define IRUPT 0xD0 /* ( IIII) force interrupt */ 63 64 /* 65 * other bits/fields in command register 66 */ 67 #define RATE6 0x00 /* not 2, but 6 msec steprate */ 68 #define RATE12 0x01 /* not 3, but 12 msec steprate */ 69 #define RATE2 0x02 /* not 5, but 2 msec steprate */ 70 #define RATE3 0x03 /* not 6, but 3 msec steprate */ 71 #define VBIT 0x04 /* verify sector ID */ 72 #define HBIT 0x08 /* suppress motor on sequence */ 73 #define UBIT 0x10 /* update track register */ 74 #define EBIT 0x04 /* wait 30 msec to settle */ 75 #define MBIT 0x10 /* multi-sector */ 76 #define PBIT 0x02 /* write precompensate */ 77 #define A0BIT 0x01 /* suppress (?) data address mark */ 78 #define IINDEX 0x04 /* interrupt on each index pulse */ 79 #define IFORCE 0x08 /* force interrupt */ 80 81 /* 82 * status register 83 */ 84 #define BUSY 0x01 /* set if command under execution */ 85 #define DRQ 0x02 /* Data Register status (pin c1) */ 86 #define LD_T00 0x04 /* lost data; track 00 */ 87 #define CRCERR 0x08 /* CRC error */ 88 #define RNF 0x10 /* Record Not Found */ 89 #define RT_SU 0x20 /* Record Type; Spin Up completed */ 90 #define WRI_PRO 0x40 /* Write Protected */ 91 #define MOTORON 0x80 /* Motor On */ 92 93 #endif /* _FDREG_H */ 94