1 /* $NetBSD: grf_etreg.h,v 1.1 1996/10/04 07:27:53 leo Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Tobias Abt 5 * Copyright (c) 1995 Ezra Story 6 * Copyright (c) 1995 Kari Mettinen 7 * Copyright (c) 1994 Markus Wild 8 * Copyright (c) 1994 Lutz Vieweg 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Lutz Vieweg. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef _GRF_ETREG_H 38 #define _GRF_ETREG_H 39 40 /* 41 * Written & Copyright by Kari Mettinen, Ezra Story. 42 * 43 * This is derived from Cirrus driver source 44 */ 45 46 /* 47 * read/write VGA registers 48 */ 49 #define vgar(ba, reg) (*(((volatile u_char *)ba)+reg)) 50 #define vgaw(ba, reg, val) *(((volatile u_char *)ba)+reg) = ((u_char)val) 51 52 /* 53 * defines for the used register addresses (mw) 54 * 55 * NOTE: there are some registers that have different addresses when 56 * in mono or color mode. We only support color mode, and thus 57 * some addresses won't work in mono-mode! 58 * 59 * General and VGA-registers taken from retina driver. Fixed a few 60 * bugs in it. (SR and GR read address is Port + 1, NOT Port) 61 * 62 */ 63 64 /* General Registers: */ 65 #define GREG_STATUS0_R 0x03C2 66 #define GREG_STATUS1_R 0x03DA 67 #define GREG_MISC_OUTPUT_R 0x03CC 68 #define GREG_MISC_OUTPUT_W 0x03C2 69 #define GREG_FEATURE_CONTROL_R 0x03CA 70 #define GREG_FEATURE_CONTROL_W 0x03DA 71 #define GREG_POS 0x0102 72 #define GREG_HERCULESCOMPAT 0x03BF 73 #define GREG_VIDEOSYSENABLE 0x03C3 74 #define GREG_DISPMODECONTROL 0x03D8 75 #define GREG_COLORSELECT 0x03D9 76 #define GREG_ATNTMODECONTROL 0x03DE 77 #define GREG_SEGMENTSELECT 0x03CD 78 79 /* Attribute Controller: */ 80 #define ACT_ADDRESS 0x03C0 81 #define ACT_ADDRESS_R 0x03C1 82 #define ACT_ADDRESS_W 0x03C0 83 #define ACT_ADDRESS_RESET 0x03DA 84 #define ACT_ID_PALETTE0 0x00 85 #define ACT_ID_PALETTE1 0x01 86 #define ACT_ID_PALETTE2 0x02 87 #define ACT_ID_PALETTE3 0x03 88 #define ACT_ID_PALETTE4 0x04 89 #define ACT_ID_PALETTE5 0x05 90 #define ACT_ID_PALETTE6 0x06 91 #define ACT_ID_PALETTE7 0x07 92 #define ACT_ID_PALETTE8 0x08 93 #define ACT_ID_PALETTE9 0x09 94 #define ACT_ID_PALETTE10 0x0A 95 #define ACT_ID_PALETTE11 0x0B 96 #define ACT_ID_PALETTE12 0x0C 97 #define ACT_ID_PALETTE13 0x0D 98 #define ACT_ID_PALETTE14 0x0E 99 #define ACT_ID_PALETTE15 0x0F 100 #define ACT_ID_ATTR_MODE_CNTL 0x10 101 #define ACT_ID_OVERSCAN_COLOR 0x11 102 #define ACT_ID_COLOR_PLANE_ENA 0x12 103 #define ACT_ID_HOR_PEL_PANNING 0x13 104 #define ACT_ID_COLOR_SELECT 0x14 105 #define ACT_ID_MISCELLANEOUS 0x16 106 107 /* Graphics Controller: */ 108 #define GCT_ADDRESS 0x03CE 109 #define GCT_ADDRESS_R 0x03CF 110 #define GCT_ADDRESS_W 0x03CF 111 #define GCT_ID_SET_RESET 0x00 112 #define GCT_ID_ENABLE_SET_RESET 0x01 113 #define GCT_ID_COLOR_COMPARE 0x02 114 #define GCT_ID_DATA_ROTATE 0x03 115 #define GCT_ID_READ_MAP_SELECT 0x04 116 #define GCT_ID_GRAPHICS_MODE 0x05 117 #define GCT_ID_MISC 0x06 118 #define GCT_ID_COLOR_XCARE 0x07 119 #define GCT_ID_BITMASK 0x08 120 121 /* Sequencer: */ 122 #define SEQ_ADDRESS 0x03C4 123 #define SEQ_ADDRESS_R 0x03C5 124 #define SEQ_ADDRESS_W 0x03C5 125 #define SEQ_ID_RESET 0x00 126 #define SEQ_ID_CLOCKING_MODE 0x01 127 #define SEQ_ID_MAP_MASK 0x02 128 #define SEQ_ID_CHAR_MAP_SELECT 0x03 129 #define SEQ_ID_MEMORY_MODE 0x04 130 #define SEQ_ID_STATE_CONTROL 0x06 131 #define SEQ_ID_AUXILIARY_MODE 0x07 132 133 /* CRT Controller: */ 134 #define CRT_ADDRESS 0x03D4 135 #define CRT_ADDRESS_R 0x03D5 136 #define CRT_ADDRESS_W 0x03D5 137 #define CRT_ID_HOR_TOTAL 0x00 138 #define CRT_ID_HOR_DISP_ENA_END 0x01 139 #define CRT_ID_START_HOR_BLANK 0x02 140 #define CRT_ID_END_HOR_BLANK 0x03 141 #define CRT_ID_START_HOR_RETR 0x04 142 #define CRT_ID_END_HOR_RETR 0x05 143 #define CRT_ID_VER_TOTAL 0x06 144 #define CRT_ID_OVERFLOW 0x07 145 #define CRT_ID_PRESET_ROW_SCAN 0x08 146 #define CRT_ID_MAX_ROW_ADDRESS 0x09 147 #define CRT_ID_CURSOR_START 0x0A 148 #define CRT_ID_CURSOR_END 0x0B 149 #define CRT_ID_START_ADDR_HIGH 0x0C 150 #define CRT_ID_START_ADDR_LOW 0x0D 151 #define CRT_ID_CURSOR_LOC_HIGH 0x0E 152 #define CRT_ID_CURSOR_LOC_LOW 0x0F 153 #define CRT_ID_START_VER_RETR 0x10 154 #define CRT_ID_END_VER_RETR 0x11 155 #define CRT_ID_VER_DISP_ENA_END 0x12 156 #define CRT_ID_OFFSET 0x13 157 #define CRT_ID_UNDERLINE_LOC 0x14 158 #define CRT_ID_START_VER_BLANK 0x15 159 #define CRT_ID_END_VER_BLANK 0x16 160 #define CRT_ID_MODE_CONTROL 0x17 161 #define CRT_ID_LINE_COMPARE 0x18 162 163 #define CRT_ID_SEGMENT_COMP 0x30 164 #define CRT_ID_GENERAL_PURPOSE 0x31 165 #define CRT_ID_RASCAS_CONFIG 0x32 166 #define CTR_ID_EXT_START 0x33 167 #define CRT_ID_6845_COMPAT 0x34 168 #define CRT_ID_OVERFLOW_HIGH 0x35 169 #define CRT_ID_VIDEO_CONFIG1 0x36 170 #define CRT_ID_VIDEO_CONFIG2 0x37 171 #define CRT_ID_HOR_OVERFLOW 0x3f 172 173 /* Video DAC */ 174 #define VDAC_ADDRESS 0x03c8 175 #define VDAC_ADDRESS_W 0x03c8 176 #define VDAC_ADDRESS_R 0x03c7 177 #define VDAC_STATE 0x03c7 178 #define VDAC_DATA 0x03c9 179 #define VDAC_MASK 0x03c6 180 #define HDR 0x03c6 /* Hidden DAC regs, 4 reads to access */ 181 182 #define VDAC_COMMAND 0x03c6 183 #define VDAC_XINDEX 0x03c7 184 #define VDAC_XDATA 0x03c8 185 186 #define WGfx(ba, idx, val) \ 187 do { \ 188 vgaw(ba, GCT_ADDRESS, idx); \ 189 vgaw(ba, GCT_ADDRESS_W , val); \ 190 } while (0) 191 192 #define WSeq(ba, idx, val) \ 193 do { \ 194 vgaw(ba, SEQ_ADDRESS, idx); \ 195 vgaw(ba, SEQ_ADDRESS_W , val); \ 196 } while (0) 197 198 #define WCrt(ba, idx, val) \ 199 do { \ 200 vgaw(ba, CRT_ADDRESS, idx); \ 201 vgaw(ba, CRT_ADDRESS_W , val); \ 202 } while (0) 203 204 #define WIma(ba, idx, val) \ 205 do { \ 206 vgaw(ba, IMA_ADDRESS, idx); \ 207 vgaw(ba, IMA_ADDRESS_W , val); \ 208 } while (0) 209 210 #define WAttr(ba, idx, val) \ 211 do { \ 212 if(vgar(ba, GREG_STATUS1_R)) \ 213 ; \ 214 vgaw(ba, ACT_ADDRESS_W, idx); \ 215 vgaw(ba, ACT_ADDRESS_W, val); \ 216 } while (0) 217 218 static inline u_char RAttr(volatile void * ba, short idx) { 219 if(vgar(ba, GREG_STATUS1_R)) 220 ; 221 vgaw(ba, ACT_ADDRESS_W, idx); 222 return vgar(ba, ACT_ADDRESS_R); 223 } 224 225 static inline u_char RSeq(volatile void * ba, short idx) { 226 vgaw(ba, SEQ_ADDRESS, idx); 227 return vgar(ba, SEQ_ADDRESS_R); 228 } 229 230 static inline u_char RCrt(volatile void * ba, short idx) { 231 vgaw(ba, CRT_ADDRESS, idx); 232 return vgar(ba, CRT_ADDRESS_R); 233 } 234 235 static inline u_char RGfx(volatile void * ba, short idx) { 236 vgaw(ba, GCT_ADDRESS, idx); 237 return vgar(ba, GCT_ADDRESS_R); 238 } 239 240 #endif /* _GRF_ETREG_H */ 241