1 /* $NetBSD: zs.c,v 1.39 2002/10/23 09:10:54 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1995 L. Weppelman (Atari modifications) 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. All advertising materials mentioning features or use of this software 27 * must display the following acknowledgement: 28 * This product includes software developed by the University of 29 * California, Berkeley and its contributors. 30 * 4. Neither the name of the University nor the names of its contributors 31 * may be used to endorse or promote products derived from this software 32 * without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 37 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 40 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 41 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 42 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 43 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 44 * SUCH DAMAGE. 45 * 46 * @(#)zs.c 8.1 (Berkeley) 7/19/93 47 */ 48 49 /* 50 * Zilog Z8530 (ZSCC) driver. 51 * 52 * Runs two tty ports (modem2 and serial2) on zs0. 53 * 54 * This driver knows far too much about chip to usage mappings. 55 */ 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/proc.h> 59 #include <sys/device.h> 60 #include <sys/conf.h> 61 #include <sys/file.h> 62 #include <sys/ioctl.h> 63 #include <sys/malloc.h> 64 #include <sys/tty.h> 65 #include <sys/time.h> 66 #include <sys/kernel.h> 67 #include <sys/syslog.h> 68 69 #include <machine/cpu.h> 70 #include <machine/iomap.h> 71 #include <machine/scu.h> 72 #include <machine/mfp.h> 73 #include <atari/dev/ym2149reg.h> 74 75 #include <dev/ic/z8530reg.h> 76 #include <atari/dev/zsvar.h> 77 #include "zs.h" 78 #if NZS > 1 79 #error "This driver supports only 1 85C30!" 80 #endif 81 82 #if NZS > 0 83 84 #define PCLK (8053976) /* PCLK pin input clock rate */ 85 #define PCLK_HD (9600 * 1536) /* PCLK on Hades pin input clock rate */ 86 87 #define splzs spl5 88 89 /* 90 * Software state per found chip. 91 */ 92 struct zs_softc { 93 struct device zi_dev; /* base device */ 94 volatile struct zsdevice *zi_zs; /* chip registers */ 95 struct zs_chanstate zi_cs[2]; /* chan A and B software state */ 96 }; 97 98 static u_char cb_scheduled = 0; /* Already asked for callback? */ 99 /* 100 * Define the registers for a closed port 101 */ 102 static u_char zs_init_regs[16] = { 103 /* 0 */ 0, 104 /* 1 */ 0, 105 /* 2 */ 0x60, 106 /* 3 */ 0, 107 /* 4 */ 0, 108 /* 5 */ 0, 109 /* 6 */ 0, 110 /* 7 */ 0, 111 /* 8 */ 0, 112 /* 9 */ ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 113 /* 10 */ ZSWR10_NRZ, 114 /* 11 */ ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 115 /* 12 */ 0, 116 /* 13 */ 0, 117 /* 14 */ ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA, 118 /* 15 */ 0 119 }; 120 121 /* 122 * Define the machine dependant clock frequencies 123 * If BRgen feeds sender/receiver we always use a 124 * divisor 16, therefor the division by 16 can as 125 * well be done here. 126 */ 127 static u_long zs_freqs_tt[] = { 128 /* 129 * Atari TT, RTxCB is generated by TT-MFP timer C, 130 * which is set to 307.2KHz during initialisation 131 * and never changed afterwards. 132 */ 133 PCLK/16, /* BRgen, PCLK, divisor 16 */ 134 229500, /* BRgen, RTxCA, divisor 16 */ 135 3672000, /* RTxCA, from PCLK4 */ 136 0, /* TRxCA, external */ 137 138 PCLK/16, /* BRgen, PCLK, divisor 16 */ 139 19200, /* BRgen, RTxCB, divisor 16 */ 140 307200, /* RTxCB, from TT-MFP TCO */ 141 2457600 /* TRxCB, from BCLK */ 142 }; 143 144 static u_long zs_freqs_falcon[] = { 145 /* 146 * Atari Falcon, XXX no specs available, this might be wrong 147 */ 148 PCLK/16, /* BRgen, PCLK, divisor 16 */ 149 229500, /* BRgen, RTxCA, divisor 16 */ 150 3672000, /* RTxCA, ??? */ 151 0, /* TRxCA, external */ 152 153 PCLK/16, /* BRgen, PCLK, divisor 16 */ 154 229500, /* BRgen, RTxCB, divisor 16 */ 155 3672000, /* RTxCB, ??? */ 156 2457600 /* TRxCB, ??? */ 157 }; 158 159 static u_long zs_freqs_hades[] = { 160 /* 161 * XXX: Channel-A unchecked!!!!! 162 */ 163 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 164 229500, /* BRgen, RTxCA, divisor 16 */ 165 3672000, /* RTxCA, from PCLK4 */ 166 0, /* TRxCA, external */ 167 168 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 169 235550, /* BRgen, RTxCB, divisor 16 */ 170 3768800, /* RTxCB, 3.7688MHz */ 171 3768800 /* TRxCB, 3.7688MHz */ 172 }; 173 174 static u_long zs_freqs_generic[] = { 175 /* 176 * other machines, assume only PCLK is available 177 */ 178 PCLK/16, /* BRgen, PCLK, divisor 16 */ 179 0, /* BRgen, RTxCA, divisor 16 */ 180 0, /* RTxCA, unknown */ 181 0, /* TRxCA, unknown */ 182 183 PCLK/16, /* BRgen, PCLK, divisor 16 */ 184 0, /* BRgen, RTxCB, divisor 16 */ 185 0, /* RTxCB, unknown */ 186 0 /* TRxCB, unknown */ 187 }; 188 static u_long *zs_frequencies; 189 190 /* Definition of the driver for autoconfig. */ 191 static int zsmatch __P((struct device *, struct cfdata *, void *)); 192 static void zsattach __P((struct device *, struct device *, void *)); 193 194 CFATTACH_DECL(zs, sizeof(struct zs_softc), 195 zsmatch, zsattach, NULL, NULL); 196 197 extern struct cfdriver zs_cd; 198 199 /* {b,c}devsw[] function prototypes */ 200 dev_type_open(zsopen); 201 dev_type_close(zsclose); 202 dev_type_read(zsread); 203 dev_type_write(zswrite); 204 dev_type_ioctl(zsioctl); 205 dev_type_stop(zsstop); 206 dev_type_tty(zstty); 207 dev_type_poll(zspoll); 208 209 const struct cdevsw zs_cdevsw = { 210 zsopen, zsclose, zsread, zswrite, zsioctl, 211 zsstop, zstty, zspoll, nommap, ttykqfilter, D_TTY 212 }; 213 214 /* Interrupt handlers. */ 215 int zshard __P((long)); 216 static int zssoft __P((long)); 217 static int zsrint __P((struct zs_chanstate *, volatile struct zschan *)); 218 static int zsxint __P((struct zs_chanstate *, volatile struct zschan *)); 219 static int zssint __P((struct zs_chanstate *, volatile struct zschan *)); 220 221 static struct zs_chanstate *zslist; 222 223 /* Routines called from other code. */ 224 static void zsstart __P((struct tty *)); 225 226 /* Routines purely local to this driver. */ 227 static void zsoverrun __P((int, long *, char *)); 228 static int zsparam __P((struct tty *, struct termios *)); 229 static int zsbaudrate __P((int, int, int *, int *, int *, int *)); 230 static int zs_modem __P((struct zs_chanstate *, int, int)); 231 static void zs_loadchannelregs __P((volatile struct zschan *, u_char *)); 232 static void zs_shutdown __P((struct zs_chanstate *)); 233 234 static int zsshortcuts; /* number of "shortcut" software interrupts */ 235 236 static int 237 zsmatch(pdp, cfp, auxp) 238 struct device *pdp; 239 struct cfdata *cfp; 240 void *auxp; 241 { 242 static int zs_matched = 0; 243 244 if(strcmp("zs", auxp) || zs_matched) 245 return(0); 246 zs_matched = 1; 247 return(1); 248 } 249 250 /* 251 * Attach a found zs. 252 */ 253 static void 254 zsattach(parent, dev, aux) 255 struct device *parent; 256 struct device *dev; 257 void *aux; 258 { 259 register struct zs_softc *zi; 260 register struct zs_chanstate *cs; 261 register volatile struct zsdevice *addr; 262 char tmp; 263 264 addr = (struct zsdevice *)AD_SCC; 265 zi = (struct zs_softc *)dev; 266 zi->zi_zs = addr; 267 cs = zi->zi_cs; 268 269 /* 270 * Get the command register into a known state. 271 */ 272 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 273 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 274 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 275 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 276 277 /* 278 * Do a hardware reset. 279 */ 280 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, ZSWR9_HARD_RESET); 281 delay(50000); /*enough ? */ 282 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, 0); 283 284 /* 285 * Initialize both channels 286 */ 287 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_A], zs_init_regs); 288 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_B], zs_init_regs); 289 290 if(machineid & ATARI_TT) { 291 /* 292 * ininitialise TT-MFP timer C: 307200Hz 293 * timer C and D share one control register: 294 * bits 0-2 control timer D 295 * bits 4-6 control timer C 296 */ 297 int cr = MFP2->mf_tcdcr & 7; 298 MFP2->mf_tcdcr = cr; /* stop timer C */ 299 MFP2->mf_tcdr = 1; /* counter 1 */ 300 cr |= T_Q004 << 4; /* divisor 4 */ 301 MFP2->mf_tcdcr = cr; /* start timer C */ 302 /* 303 * enable scc related interrupts 304 */ 305 SCU->vme_mask |= SCU_SCC; 306 307 zs_frequencies = zs_freqs_tt; 308 } else if (machineid & ATARI_FALCON) { 309 zs_frequencies = zs_freqs_falcon; 310 } else if (machineid & ATARI_HADES) { 311 zs_frequencies = zs_freqs_hades; 312 } else { 313 zs_frequencies = zs_freqs_generic; 314 } 315 316 /* link into interrupt list with order (A,B) (B=A+1) */ 317 cs[0].cs_next = &cs[1]; 318 cs[1].cs_next = zslist; 319 zslist = cs; 320 321 cs->cs_unit = 0; 322 cs->cs_zc = &addr->zs_chan[ZS_CHAN_A]; 323 cs++; 324 cs->cs_unit = 1; 325 cs->cs_zc = &addr->zs_chan[ZS_CHAN_B]; 326 327 printf(": serial2 on channel a and modem2 on channel b\n"); 328 } 329 330 /* 331 * Open a zs serial port. 332 */ 333 int 334 zsopen(dev, flags, mode, p) 335 dev_t dev; 336 int flags; 337 int mode; 338 struct proc *p; 339 { 340 register struct tty *tp; 341 register struct zs_chanstate *cs; 342 struct zs_softc *zi; 343 int unit = ZS_UNIT(dev); 344 int zs = unit >> 1; 345 int error, s; 346 347 if(zs >= zs_cd.cd_ndevs || (zi = zs_cd.cd_devs[zs]) == NULL) 348 return (ENXIO); 349 cs = &zi->zi_cs[unit & 1]; 350 351 /* 352 * When port A (ser02) is selected on the TT, make sure 353 * the port is enabled. 354 */ 355 if((machineid & ATARI_TT) && !(unit & 1)) 356 ym2149_ser2(1); 357 358 if (cs->cs_rbuf == NULL) { 359 cs->cs_rbuf = malloc(ZLRB_RING_SIZE * sizeof(int), M_DEVBUF, 360 M_WAITOK); 361 } 362 363 tp = cs->cs_ttyp; 364 if(tp == NULL) { 365 cs->cs_ttyp = tp = ttymalloc(); 366 tty_attach(tp); 367 tp->t_dev = dev; 368 tp->t_oproc = zsstart; 369 tp->t_param = zsparam; 370 } 371 372 if ((tp->t_state & TS_ISOPEN) && 373 (tp->t_state & TS_XCLUDE) && 374 p->p_ucred->cr_uid != 0) 375 return (EBUSY); 376 377 s = spltty(); 378 379 /* 380 * Do the following iff this is a first open. 381 */ 382 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 383 if(tp->t_ispeed == 0) { 384 tp->t_iflag = TTYDEF_IFLAG; 385 tp->t_oflag = TTYDEF_OFLAG; 386 tp->t_cflag = TTYDEF_CFLAG; 387 tp->t_lflag = TTYDEF_LFLAG; 388 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 389 } 390 ttychars(tp); 391 ttsetwater(tp); 392 393 (void)zsparam(tp, &tp->t_termios); 394 395 /* 396 * Turn on DTR. We must always do this, even if carrier is not 397 * present, because otherwise we'd have to use TIOCSDTR 398 * immediately after setting CLOCAL, which applications do not 399 * expect. We always assert DTR while the device is open 400 * unless explicitly requested to deassert it. 401 */ 402 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, DMSET); 403 /* May never get a status intr. if DCD already on. -gwr */ 404 if((cs->cs_rr0 = cs->cs_zc->zc_csr) & ZSRR0_DCD) 405 tp->t_state |= TS_CARR_ON; 406 if(cs->cs_softcar) 407 tp->t_state |= TS_CARR_ON; 408 } 409 410 splx(s); 411 412 error = ttyopen(tp, ZS_DIALOUT(dev), (flags & O_NONBLOCK)); 413 if (error) 414 goto bad; 415 416 error = tp->t_linesw->l_open(dev, tp); 417 if(error) 418 goto bad; 419 return (0); 420 421 bad: 422 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 423 /* 424 * We failed to open the device, and nobody else had it opened. 425 * Clean up the state as appropriate. 426 */ 427 zs_shutdown(cs); 428 } 429 return(error); 430 } 431 432 /* 433 * Close a zs serial port. 434 */ 435 int 436 zsclose(dev, flags, mode, p) 437 dev_t dev; 438 int flags; 439 int mode; 440 struct proc *p; 441 { 442 register struct zs_chanstate *cs; 443 register struct tty *tp; 444 struct zs_softc *zi; 445 int unit = ZS_UNIT(dev); 446 447 zi = zs_cd.cd_devs[unit >> 1]; 448 cs = &zi->zi_cs[unit & 1]; 449 tp = cs->cs_ttyp; 450 451 tp->t_linesw->l_close(tp, flags); 452 ttyclose(tp); 453 454 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 455 /* 456 * Although we got a last close, the device may still be in 457 * use; e.g. if this was the dialout node, and there are still 458 * processes waiting for carrier on the non-dialout node. 459 */ 460 zs_shutdown(cs); 461 } 462 return (0); 463 } 464 465 /* 466 * Read/write zs serial port. 467 */ 468 int 469 zsread(dev, uio, flags) 470 dev_t dev; 471 struct uio *uio; 472 int flags; 473 { 474 register struct zs_chanstate *cs; 475 register struct zs_softc *zi; 476 register struct tty *tp; 477 int unit; 478 479 unit = ZS_UNIT(dev); 480 zi = zs_cd.cd_devs[unit >> 1]; 481 cs = &zi->zi_cs[unit & 1]; 482 tp = cs->cs_ttyp; 483 484 return(tp->t_linesw->l_read(tp, uio, flags)); 485 } 486 487 int 488 zswrite(dev, uio, flags) 489 dev_t dev; 490 struct uio *uio; 491 int flags; 492 { 493 register struct zs_chanstate *cs; 494 register struct zs_softc *zi; 495 register struct tty *tp; 496 int unit; 497 498 unit = ZS_UNIT(dev); 499 zi = zs_cd.cd_devs[unit >> 1]; 500 cs = &zi->zi_cs[unit & 1]; 501 tp = cs->cs_ttyp; 502 503 return(tp->t_linesw->l_write(tp, uio, flags)); 504 } 505 506 int 507 zspoll(dev, events, p) 508 dev_t dev; 509 int events; 510 struct proc *p; 511 { 512 register struct zs_chanstate *cs; 513 register struct zs_softc *zi; 514 register struct tty *tp; 515 int unit; 516 517 unit = ZS_UNIT(dev); 518 zi = zs_cd.cd_devs[unit >> 1]; 519 cs = &zi->zi_cs[unit & 1]; 520 tp = cs->cs_ttyp; 521 522 return ((*tp->t_linesw->l_poll)(tp, events, p)); 523 } 524 525 struct tty * 526 zstty(dev) 527 dev_t dev; 528 { 529 register struct zs_chanstate *cs; 530 register struct zs_softc *zi; 531 int unit; 532 533 unit = ZS_UNIT(dev); 534 zi = zs_cd.cd_devs[unit >> 1]; 535 cs = &zi->zi_cs[unit & 1]; 536 return(cs->cs_ttyp); 537 } 538 539 /* 540 * ZS hardware interrupt. Scan all ZS channels. NB: we know here that 541 * channels are kept in (A,B) pairs. 542 * 543 * Do just a little, then get out; set a software interrupt if more 544 * work is needed. 545 * 546 * We deliberately ignore the vectoring Zilog gives us, and match up 547 * only the number of `reset interrupt under service' operations, not 548 * the order. 549 */ 550 551 int 552 zshard(sr) 553 long sr; 554 { 555 register struct zs_chanstate *a; 556 #define b (a + 1) 557 register volatile struct zschan *zc; 558 register int rr3, intflags = 0, v, i; 559 560 do { 561 intflags &= ~4; 562 for(a = zslist; a != NULL; a = b->cs_next) { 563 rr3 = ZS_READ(a->cs_zc, 3); 564 if(rr3 & (ZSRR3_IP_A_RX|ZSRR3_IP_A_TX|ZSRR3_IP_A_STAT)) { 565 intflags |= 4|2; 566 zc = a->cs_zc; 567 i = a->cs_rbput; 568 if(rr3 & ZSRR3_IP_A_RX && (v = zsrint(a, zc)) != 0) { 569 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 570 intflags |= 1; 571 } 572 if(rr3 & ZSRR3_IP_A_TX && (v = zsxint(a, zc)) != 0) { 573 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 574 intflags |= 1; 575 } 576 if(rr3 & ZSRR3_IP_A_STAT && (v = zssint(a, zc)) != 0) { 577 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 578 intflags |= 1; 579 } 580 a->cs_rbput = i; 581 } 582 if(rr3 & (ZSRR3_IP_B_RX|ZSRR3_IP_B_TX|ZSRR3_IP_B_STAT)) { 583 intflags |= 4|2; 584 zc = b->cs_zc; 585 i = b->cs_rbput; 586 if(rr3 & ZSRR3_IP_B_RX && (v = zsrint(b, zc)) != 0) { 587 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 588 intflags |= 1; 589 } 590 if(rr3 & ZSRR3_IP_B_TX && (v = zsxint(b, zc)) != 0) { 591 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 592 intflags |= 1; 593 } 594 if(rr3 & ZSRR3_IP_B_STAT && (v = zssint(b, zc)) != 0) { 595 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 596 intflags |= 1; 597 } 598 b->cs_rbput = i; 599 } 600 } 601 } while(intflags & 4); 602 #undef b 603 604 if(intflags & 1) { 605 if(BASEPRI(sr)) { 606 spl1(); 607 zsshortcuts++; 608 return(zssoft(sr)); 609 } 610 else if(!cb_scheduled) { 611 cb_scheduled++; 612 add_sicallback((si_farg)zssoft, 0, 0); 613 } 614 } 615 return(intflags & 2); 616 } 617 618 static int 619 zsrint(cs, zc) 620 register struct zs_chanstate *cs; 621 register volatile struct zschan *zc; 622 { 623 register int c; 624 625 /* 626 * First read the status, because read of the received char 627 * destroy the status of this char. 628 */ 629 c = ZS_READ(zc, 1); 630 c |= (zc->zc_data << 8); 631 632 /* clear receive error & interrupt condition */ 633 zc->zc_csr = ZSWR0_RESET_ERRORS; 634 zc->zc_csr = ZSWR0_CLR_INTR; 635 636 return(ZRING_MAKE(ZRING_RINT, c)); 637 } 638 639 static int 640 zsxint(cs, zc) 641 register struct zs_chanstate *cs; 642 register volatile struct zschan *zc; 643 { 644 register int i = cs->cs_tbc; 645 646 if(i == 0) { 647 zc->zc_csr = ZSWR0_RESET_TXINT; 648 zc->zc_csr = ZSWR0_CLR_INTR; 649 return(ZRING_MAKE(ZRING_XINT, 0)); 650 } 651 cs->cs_tbc = i - 1; 652 zc->zc_data = *cs->cs_tba++; 653 zc->zc_csr = ZSWR0_CLR_INTR; 654 return (0); 655 } 656 657 static int 658 zssint(cs, zc) 659 register struct zs_chanstate *cs; 660 register volatile struct zschan *zc; 661 { 662 register int rr0; 663 664 rr0 = zc->zc_csr; 665 zc->zc_csr = ZSWR0_RESET_STATUS; 666 zc->zc_csr = ZSWR0_CLR_INTR; 667 /* 668 * The chip's hardware flow control is, as noted in zsreg.h, 669 * busted---if the DCD line goes low the chip shuts off the 670 * receiver (!). If we want hardware CTS flow control but do 671 * not have it, and carrier is now on, turn HFC on; if we have 672 * HFC now but carrier has gone low, turn it off. 673 */ 674 if(rr0 & ZSRR0_DCD) { 675 if(cs->cs_ttyp->t_cflag & CCTS_OFLOW && 676 (cs->cs_creg[3] & ZSWR3_HFC) == 0) { 677 cs->cs_creg[3] |= ZSWR3_HFC; 678 ZS_WRITE(zc, 3, cs->cs_creg[3]); 679 } 680 } 681 else { 682 if (cs->cs_creg[3] & ZSWR3_HFC) { 683 cs->cs_creg[3] &= ~ZSWR3_HFC; 684 ZS_WRITE(zc, 3, cs->cs_creg[3]); 685 } 686 } 687 return(ZRING_MAKE(ZRING_SINT, rr0)); 688 } 689 690 /* 691 * Print out a ring or fifo overrun error message. 692 */ 693 static void 694 zsoverrun(unit, ptime, what) 695 int unit; 696 long *ptime; 697 char *what; 698 { 699 700 if(*ptime != time.tv_sec) { 701 *ptime = time.tv_sec; 702 log(LOG_WARNING, "zs%d%c: %s overrun\n", unit >> 1, 703 (unit & 1) + 'a', what); 704 } 705 } 706 707 /* 708 * ZS software interrupt. Scan all channels for deferred interrupts. 709 */ 710 int 711 zssoft(sr) 712 long sr; 713 { 714 register struct zs_chanstate *cs; 715 register volatile struct zschan *zc; 716 register struct linesw *line; 717 register struct tty *tp; 718 register int get, n, c, cc, unit, s; 719 int retval = 0; 720 721 cb_scheduled = 0; 722 s = spltty(); 723 for(cs = zslist; cs != NULL; cs = cs->cs_next) { 724 get = cs->cs_rbget; 725 again: 726 n = cs->cs_rbput; /* atomic */ 727 if(get == n) /* nothing more on this line */ 728 continue; 729 retval = 1; 730 unit = cs->cs_unit; /* set up to handle interrupts */ 731 zc = cs->cs_zc; 732 tp = cs->cs_ttyp; 733 line = tp->t_linesw; 734 /* 735 * Compute the number of interrupts in the receive ring. 736 * If the count is overlarge, we lost some events, and 737 * must advance to the first valid one. It may get 738 * overwritten if more data are arriving, but this is 739 * too expensive to check and gains nothing (we already 740 * lost out; all we can do at this point is trade one 741 * kind of loss for another). 742 */ 743 n -= get; 744 if(n > ZLRB_RING_SIZE) { 745 zsoverrun(unit, &cs->cs_rotime, "ring"); 746 get += n - ZLRB_RING_SIZE; 747 n = ZLRB_RING_SIZE; 748 } 749 while(--n >= 0) { 750 /* race to keep ahead of incoming interrupts */ 751 c = cs->cs_rbuf[get++ & ZLRB_RING_MASK]; 752 switch (ZRING_TYPE(c)) { 753 754 case ZRING_RINT: 755 c = ZRING_VALUE(c); 756 if(c & ZSRR1_DO) 757 zsoverrun(unit, &cs->cs_fotime, "fifo"); 758 cc = c >> 8; 759 if(c & ZSRR1_FE) 760 cc |= TTY_FE; 761 if(c & ZSRR1_PE) 762 cc |= TTY_PE; 763 line->l_rint(cc, tp); 764 break; 765 766 case ZRING_XINT: 767 /* 768 * Transmit done: change registers and resume, 769 * or clear BUSY. 770 */ 771 if(cs->cs_heldchange) { 772 int sps; 773 774 sps = splzs(); 775 c = zc->zc_csr; 776 if((c & ZSRR0_DCD) == 0) 777 cs->cs_preg[3] &= ~ZSWR3_HFC; 778 bcopy((caddr_t)cs->cs_preg, 779 (caddr_t)cs->cs_creg, 16); 780 zs_loadchannelregs(zc, cs->cs_creg); 781 splx(sps); 782 cs->cs_heldchange = 0; 783 if(cs->cs_heldtbc 784 && (tp->t_state & TS_TTSTOP) == 0) { 785 cs->cs_tbc = cs->cs_heldtbc - 1; 786 zc->zc_data = *cs->cs_tba++; 787 goto again; 788 } 789 } 790 tp->t_state &= ~TS_BUSY; 791 if(tp->t_state & TS_FLUSH) 792 tp->t_state &= ~TS_FLUSH; 793 else ndflush(&tp->t_outq,cs->cs_tba 794 - (caddr_t)tp->t_outq.c_cf); 795 line->l_start(tp); 796 break; 797 798 case ZRING_SINT: 799 /* 800 * Status line change. HFC bit is run in 801 * hardware interrupt, to avoid locking 802 * at splzs here. 803 */ 804 c = ZRING_VALUE(c); 805 if((c ^ cs->cs_rr0) & ZSRR0_DCD) { 806 cc = (c & ZSRR0_DCD) != 0; 807 if(line->l_modem(tp, cc) == 0) 808 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, 809 cc ? DMBIS : DMBIC); 810 } 811 cs->cs_rr0 = c; 812 break; 813 814 default: 815 log(LOG_ERR, "zs%d%c: bad ZRING_TYPE (%x)\n", 816 unit >> 1, (unit & 1) + 'a', c); 817 break; 818 } 819 } 820 cs->cs_rbget = get; 821 goto again; 822 } 823 splx(s); 824 return (retval); 825 } 826 827 int 828 zsioctl(dev, cmd, data, flag, p) 829 dev_t dev; 830 u_long cmd; 831 caddr_t data; 832 int flag; 833 struct proc *p; 834 { 835 int unit = ZS_UNIT(dev); 836 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 837 register struct tty *tp = zi->zi_cs[unit & 1].cs_ttyp; 838 register int error, s; 839 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 840 841 error = tp->t_linesw->l_ioctl(tp, cmd, data, flag, p); 842 if(error != EPASSTHROUGH) 843 return(error); 844 845 error = ttioctl(tp, cmd, data, flag, p); 846 if(error !=EPASSTHROUGH) 847 return (error); 848 849 switch (cmd) { 850 case TIOCSBRK: 851 s = splzs(); 852 cs->cs_preg[5] |= ZSWR5_BREAK; 853 cs->cs_creg[5] |= ZSWR5_BREAK; 854 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 855 splx(s); 856 break; 857 case TIOCCBRK: 858 s = splzs(); 859 cs->cs_preg[5] &= ~ZSWR5_BREAK; 860 cs->cs_creg[5] &= ~ZSWR5_BREAK; 861 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 862 splx(s); 863 break; 864 case TIOCGFLAGS: { 865 int bits = 0; 866 867 if(cs->cs_softcar) 868 bits |= TIOCFLAG_SOFTCAR; 869 if(cs->cs_creg[15] & ZSWR15_DCD_IE) 870 bits |= TIOCFLAG_CLOCAL; 871 if(cs->cs_creg[3] & ZSWR3_HFC) 872 bits |= TIOCFLAG_CRTSCTS; 873 *(int *)data = bits; 874 break; 875 } 876 case TIOCSFLAGS: { 877 int userbits = 0; 878 879 error = suser(p->p_ucred, &p->p_acflag); 880 if(error != 0) 881 return (EPERM); 882 883 userbits = *(int *)data; 884 885 /* 886 * can have `local' or `softcar', and `rtscts' or `mdmbuf' 887 # defaulting to software flow control. 888 */ 889 if(userbits & TIOCFLAG_SOFTCAR && userbits & TIOCFLAG_CLOCAL) 890 return(EINVAL); 891 if(userbits & TIOCFLAG_MDMBUF) /* don't support this (yet?) */ 892 return(ENODEV); 893 894 s = splzs(); 895 if((userbits & TIOCFLAG_SOFTCAR)) { 896 cs->cs_softcar = 1; /* turn on softcar */ 897 cs->cs_preg[15] &= ~ZSWR15_DCD_IE; /* turn off dcd */ 898 cs->cs_creg[15] &= ~ZSWR15_DCD_IE; 899 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 900 } 901 else if(userbits & TIOCFLAG_CLOCAL) { 902 cs->cs_softcar = 0; /* turn off softcar */ 903 cs->cs_preg[15] |= ZSWR15_DCD_IE; /* turn on dcd */ 904 cs->cs_creg[15] |= ZSWR15_DCD_IE; 905 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 906 tp->t_termios.c_cflag |= CLOCAL; 907 } 908 if(userbits & TIOCFLAG_CRTSCTS) { 909 cs->cs_preg[15] |= ZSWR15_CTS_IE; 910 cs->cs_creg[15] |= ZSWR15_CTS_IE; 911 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 912 cs->cs_preg[3] |= ZSWR3_HFC; 913 cs->cs_creg[3] |= ZSWR3_HFC; 914 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 915 tp->t_termios.c_cflag |= CRTSCTS; 916 } 917 else { 918 /* no mdmbuf, so we must want software flow control */ 919 cs->cs_preg[15] &= ~ZSWR15_CTS_IE; 920 cs->cs_creg[15] &= ~ZSWR15_CTS_IE; 921 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 922 cs->cs_preg[3] &= ~ZSWR3_HFC; 923 cs->cs_creg[3] &= ~ZSWR3_HFC; 924 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 925 tp->t_termios.c_cflag &= ~CRTSCTS; 926 } 927 splx(s); 928 break; 929 } 930 case TIOCSDTR: 931 zs_modem(cs, ZSWR5_DTR, DMBIS); 932 break; 933 case TIOCCDTR: 934 zs_modem(cs, ZSWR5_DTR, DMBIC); 935 break; 936 case TIOCMGET: 937 zs_modem(cs, 0, DMGET); 938 break; 939 case TIOCMSET: 940 case TIOCMBIS: 941 case TIOCMBIC: 942 default: 943 return (EPASSTHROUGH); 944 } 945 return (0); 946 } 947 948 /* 949 * Start or restart transmission. 950 */ 951 static void 952 zsstart(tp) 953 register struct tty *tp; 954 { 955 register struct zs_chanstate *cs; 956 register int s, nch; 957 int unit = ZS_UNIT(tp->t_dev); 958 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 959 960 cs = &zi->zi_cs[unit & 1]; 961 s = spltty(); 962 963 /* 964 * If currently active or delaying, no need to do anything. 965 */ 966 if(tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) 967 goto out; 968 969 /* 970 * If there are sleepers, and output has drained below low 971 * water mark, awaken. 972 */ 973 if(tp->t_outq.c_cc <= tp->t_lowat) { 974 if(tp->t_state & TS_ASLEEP) { 975 tp->t_state &= ~TS_ASLEEP; 976 wakeup((caddr_t)&tp->t_outq); 977 } 978 selwakeup(&tp->t_wsel); 979 } 980 981 nch = ndqb(&tp->t_outq, 0); /* XXX */ 982 if(nch) { 983 register char *p = tp->t_outq.c_cf; 984 985 /* mark busy, enable tx done interrupts, & send first byte */ 986 tp->t_state |= TS_BUSY; 987 (void) splzs(); 988 cs->cs_preg[1] |= ZSWR1_TIE; 989 cs->cs_creg[1] |= ZSWR1_TIE; 990 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 991 cs->cs_zc->zc_data = *p; 992 cs->cs_tba = p + 1; 993 cs->cs_tbc = nch - 1; 994 } else { 995 /* 996 * Nothing to send, turn off transmit done interrupts. 997 * This is useful if something is doing polled output. 998 */ 999 (void) splzs(); 1000 cs->cs_preg[1] &= ~ZSWR1_TIE; 1001 cs->cs_creg[1] &= ~ZSWR1_TIE; 1002 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 1003 } 1004 out: 1005 splx(s); 1006 } 1007 1008 /* 1009 * Stop output, e.g., for ^S or output flush. 1010 */ 1011 void 1012 zsstop(tp, flag) 1013 register struct tty *tp; 1014 int flag; 1015 { 1016 register struct zs_chanstate *cs; 1017 register int s, unit = ZS_UNIT(tp->t_dev); 1018 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 1019 1020 cs = &zi->zi_cs[unit & 1]; 1021 s = splzs(); 1022 if(tp->t_state & TS_BUSY) { 1023 /* 1024 * Device is transmitting; must stop it. 1025 */ 1026 cs->cs_tbc = 0; 1027 if ((tp->t_state & TS_TTSTOP) == 0) 1028 tp->t_state |= TS_FLUSH; 1029 } 1030 splx(s); 1031 } 1032 1033 static void 1034 zs_shutdown(cs) 1035 struct zs_chanstate *cs; 1036 { 1037 struct tty *tp = cs->cs_ttyp; 1038 int s; 1039 1040 s = splzs(); 1041 1042 /* 1043 * Hang up if necessary. Wait a bit, so the other side has time to 1044 * notice even if we immediately open the port again. 1045 */ 1046 if(tp->t_cflag & HUPCL) { 1047 zs_modem(cs, 0, DMSET); 1048 (void)tsleep((caddr_t)cs, TTIPRI, ttclos, hz); 1049 } 1050 1051 /* Clear any break condition set with TIOCSBRK. */ 1052 if(cs->cs_creg[5] & ZSWR5_BREAK) { 1053 cs->cs_preg[5] &= ~ZSWR5_BREAK; 1054 cs->cs_creg[5] &= ~ZSWR5_BREAK; 1055 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1056 } 1057 1058 /* 1059 * Drop all lines and cancel interrupts 1060 */ 1061 zs_loadchannelregs(cs->cs_zc, zs_init_regs); 1062 splx(s); 1063 } 1064 1065 /* 1066 * Set ZS tty parameters from termios. 1067 * 1068 * This routine makes use of the fact that only registers 1069 * 1, 3, 4, 5, 9, 10, 11, 12, 13, 14, and 15 are written. 1070 */ 1071 static int 1072 zsparam(tp, t) 1073 register struct tty *tp; 1074 register struct termios *t; 1075 { 1076 int unit = ZS_UNIT(tp->t_dev); 1077 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 1078 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 1079 int cdiv, clkm, brgm, tcon; 1080 register int tmp, tmp5, cflag, s; 1081 1082 tmp = t->c_ospeed; 1083 tmp5 = t->c_ispeed; 1084 if(tmp < 0 || (tmp5 && tmp5 != tmp)) 1085 return(EINVAL); 1086 if(tmp == 0) { 1087 /* stty 0 => drop DTR and RTS */ 1088 zs_modem(cs, 0, DMSET); 1089 return(0); 1090 } 1091 tmp = zsbaudrate(unit, tmp, &cdiv, &clkm, &brgm, &tcon); 1092 if (tmp < 0) 1093 return(EINVAL); 1094 tp->t_ispeed = tp->t_ospeed = tmp; 1095 1096 cflag = tp->t_cflag = t->c_cflag; 1097 if (cflag & CSTOPB) 1098 cdiv |= ZSWR4_TWOSB; 1099 else 1100 cdiv |= ZSWR4_ONESB; 1101 if (!(cflag & PARODD)) 1102 cdiv |= ZSWR4_EVENP; 1103 if (cflag & PARENB) 1104 cdiv |= ZSWR4_PARENB; 1105 1106 switch(cflag & CSIZE) { 1107 case CS5: 1108 tmp = ZSWR3_RX_5; 1109 tmp5 = ZSWR5_TX_5; 1110 break; 1111 case CS6: 1112 tmp = ZSWR3_RX_6; 1113 tmp5 = ZSWR5_TX_6; 1114 break; 1115 case CS7: 1116 tmp = ZSWR3_RX_7; 1117 tmp5 = ZSWR5_TX_7; 1118 break; 1119 case CS8: 1120 default: 1121 tmp = ZSWR3_RX_8; 1122 tmp5 = ZSWR5_TX_8; 1123 break; 1124 } 1125 tmp |= ZSWR3_RX_ENABLE; 1126 tmp5 |= ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS; 1127 1128 /* 1129 * Block interrupts so that state will not 1130 * be altered until we are done setting it up. 1131 */ 1132 s = splzs(); 1133 cs->cs_preg[4] = cdiv; 1134 cs->cs_preg[11] = clkm; 1135 cs->cs_preg[12] = tcon; 1136 cs->cs_preg[13] = tcon >> 8; 1137 cs->cs_preg[14] = brgm; 1138 cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE; 1139 cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT; 1140 cs->cs_preg[10] = ZSWR10_NRZ; 1141 cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE; 1142 1143 /* 1144 * Output hardware flow control on the chip is horrendous: if 1145 * carrier detect drops, the receiver is disabled. Hence we 1146 * can only do this when the carrier is on. 1147 */ 1148 if(cflag & CCTS_OFLOW && cs->cs_zc->zc_csr & ZSRR0_DCD) 1149 tmp |= ZSWR3_HFC; 1150 cs->cs_preg[3] = tmp; 1151 cs->cs_preg[5] = tmp5; 1152 1153 /* 1154 * If nothing is being transmitted, set up new current values, 1155 * else mark them as pending. 1156 */ 1157 if(cs->cs_heldchange == 0) { 1158 if (cs->cs_ttyp->t_state & TS_BUSY) { 1159 cs->cs_heldtbc = cs->cs_tbc; 1160 cs->cs_tbc = 0; 1161 cs->cs_heldchange = 1; 1162 } else { 1163 bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16); 1164 zs_loadchannelregs(cs->cs_zc, cs->cs_creg); 1165 } 1166 } 1167 splx(s); 1168 return (0); 1169 } 1170 1171 /* 1172 * search for the best matching baudrate 1173 */ 1174 static int 1175 zsbaudrate(unit, wanted, divisor, clockmode, brgenmode, timeconst) 1176 int unit, wanted, *divisor, *clockmode, *brgenmode, *timeconst; 1177 { 1178 int bestdiff, bestbps, source; 1179 1180 bestdiff = bestbps = 0; 1181 unit = (unit & 1) << 2; 1182 for (source = 0; source < 4; ++source) { 1183 long freq = zs_frequencies[unit + source]; 1184 int diff, bps, div, clkm, brgm, tcon; 1185 1186 bps = div = clkm = brgm = tcon = 0; 1187 switch (source) { 1188 case 0: /* BRgen, PCLK */ 1189 brgm = ZSWR14_BAUD_ENA|ZSWR14_BAUD_FROM_PCLK; 1190 break; 1191 case 1: /* BRgen, RTxC */ 1192 brgm = ZSWR14_BAUD_ENA; 1193 break; 1194 case 2: /* RTxC */ 1195 clkm = ZSWR11_RXCLK_RTXC|ZSWR11_TXCLK_RTXC; 1196 break; 1197 case 3: /* TRxC */ 1198 clkm = ZSWR11_RXCLK_TRXC|ZSWR11_TXCLK_TRXC; 1199 break; 1200 } 1201 switch (source) { 1202 case 0: 1203 case 1: 1204 div = ZSWR4_CLK_X16; 1205 clkm = ZSWR11_RXCLK_BAUD|ZSWR11_TXCLK_BAUD; 1206 tcon = BPS_TO_TCONST(freq, wanted); 1207 if (tcon < 0) 1208 tcon = 0; 1209 bps = TCONST_TO_BPS(freq, tcon); 1210 break; 1211 case 2: 1212 case 3: 1213 { int b1 = freq / 16, d1 = abs(b1 - wanted); 1214 int b2 = freq / 32, d2 = abs(b2 - wanted); 1215 int b3 = freq / 64, d3 = abs(b3 - wanted); 1216 1217 if (d1 < d2 && d1 < d3) { 1218 div = ZSWR4_CLK_X16; 1219 bps = b1; 1220 } else if (d2 < d3 && d2 < d1) { 1221 div = ZSWR4_CLK_X32; 1222 bps = b2; 1223 } else { 1224 div = ZSWR4_CLK_X64; 1225 bps = b3; 1226 } 1227 brgm = tcon = 0; 1228 break; 1229 } 1230 } 1231 diff = abs(bps - wanted); 1232 if (!source || diff < bestdiff) { 1233 *divisor = div; 1234 *clockmode = clkm; 1235 *brgenmode = brgm; 1236 *timeconst = tcon; 1237 bestbps = bps; 1238 bestdiff = diff; 1239 if (diff == 0) 1240 break; 1241 } 1242 } 1243 /* Allow deviations upto 5% */ 1244 if (20 * bestdiff > wanted) 1245 return -1; 1246 return bestbps; 1247 } 1248 1249 /* 1250 * Raise or lower modem control (DTR/RTS) signals. If a character is 1251 * in transmission, the change is deferred. 1252 */ 1253 static int 1254 zs_modem(cs, bits, how) 1255 struct zs_chanstate *cs; 1256 int bits, how; 1257 { 1258 int s, mbits; 1259 1260 bits &= ZSWR5_DTR | ZSWR5_RTS; 1261 1262 s = splzs(); 1263 mbits = cs->cs_preg[5] & (ZSWR5_DTR | ZSWR5_RTS); 1264 1265 switch(how) { 1266 case DMSET: 1267 mbits = bits; 1268 break; 1269 case DMBIS: 1270 mbits |= bits; 1271 break; 1272 case DMBIC: 1273 mbits &= ~bits; 1274 break; 1275 case DMGET: 1276 splx(s); 1277 return(mbits); 1278 } 1279 1280 cs->cs_preg[5] = (cs->cs_preg[5] & ~(ZSWR5_DTR | ZSWR5_RTS)) | mbits; 1281 if(cs->cs_heldchange == 0) { 1282 if(cs->cs_ttyp->t_state & TS_BUSY) { 1283 cs->cs_heldtbc = cs->cs_tbc; 1284 cs->cs_tbc = 0; 1285 cs->cs_heldchange = 1; 1286 } 1287 else { 1288 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1289 } 1290 } 1291 splx(s); 1292 return(0); 1293 } 1294 1295 /* 1296 * Write the given register set to the given zs channel in the proper order. 1297 * The channel must not be transmitting at the time. The receiver will 1298 * be disabled for the time it takes to write all the registers. 1299 */ 1300 static void 1301 zs_loadchannelregs(zc, reg) 1302 volatile struct zschan *zc; 1303 u_char *reg; 1304 { 1305 int i; 1306 1307 zc->zc_csr = ZSM_RESET_ERR; /* reset error condition */ 1308 i = zc->zc_data; /* drain fifo */ 1309 i = zc->zc_data; 1310 i = zc->zc_data; 1311 ZS_WRITE(zc, 4, reg[4]); 1312 ZS_WRITE(zc, 10, reg[10]); 1313 ZS_WRITE(zc, 3, reg[3] & ~ZSWR3_RX_ENABLE); 1314 ZS_WRITE(zc, 5, reg[5] & ~ZSWR5_TX_ENABLE); 1315 ZS_WRITE(zc, 1, reg[1]); 1316 ZS_WRITE(zc, 9, reg[9]); 1317 ZS_WRITE(zc, 11, reg[11]); 1318 ZS_WRITE(zc, 12, reg[12]); 1319 ZS_WRITE(zc, 13, reg[13]); 1320 ZS_WRITE(zc, 14, reg[14]); 1321 ZS_WRITE(zc, 15, reg[15]); 1322 ZS_WRITE(zc, 3, reg[3]); 1323 ZS_WRITE(zc, 5, reg[5]); 1324 } 1325 #endif /* NZS > 1 */ 1326