1 /* $NetBSD: pci_machdep.c,v 1.35 2002/05/16 01:01:34 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Leo Weppelman. All rights reserved. 5 * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include "opt_mbtype.h" 35 #include <sys/types.h> 36 #include <sys/param.h> 37 #include <sys/time.h> 38 #include <sys/systm.h> 39 #include <sys/errno.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 43 #define _ATARI_BUS_DMA_PRIVATE 44 #include <machine/bus.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <machine/cpu.h> 52 #include <machine/iomap.h> 53 #include <machine/mfp.h> 54 55 #include <atari/atari/device.h> 56 #include <atari/pci/pci_vga.h> 57 58 /* 59 * Sizes of pci memory and I/O area. 60 */ 61 #define PCI_MEM_END 0x10000000 /* 256 MByte */ 62 #define PCI_IO_END 0x10000000 /* 256 MByte */ 63 64 /* 65 * We preserve some space at the begin of the pci area for 32BIT_1M 66 * devices and standard vga. 67 */ 68 #define PCI_MEM_START 0x00100000 /* 1 MByte */ 69 #define PCI_IO_START 0x00004000 /* 16 kByte (some PCI cards allow only 70 I/O addresses up to 0xffff) */ 71 72 /* 73 * PCI memory and IO should be aligned acording to this masks 74 */ 75 #define PCI_MACHDEP_IO_ALIGN_MASK 0xffffff00 76 #define PCI_MACHDEP_MEM_ALIGN_MASK 0xfffff000 77 78 /* 79 * Convert a PCI 'device' number to a slot number. 80 */ 81 #define DEV2SLOT(dev) (3 - dev) 82 83 /* 84 * Struct to hold the memory and I/O datas of the pci devices 85 */ 86 struct pci_memreg { 87 LIST_ENTRY(pci_memreg) link; 88 int dev; 89 pcitag_t tag; 90 pcireg_t reg, address, mask; 91 u_int32_t size; 92 u_int32_t csr; 93 }; 94 95 typedef LIST_HEAD(pci_memreg_head, pci_memreg) PCI_MEMREG; 96 97 /* 98 * Entry points for PCI DMA. Use only the 'standard' functions. 99 */ 100 int _bus_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, bus_size_t, 101 bus_size_t, int, bus_dmamap_t *)); 102 struct atari_bus_dma_tag pci_bus_dma_tag = { 103 0, 104 #if defined(_ATARIHW_) 105 0x80000000, /* On the Hades, CPU memory starts here PCI-wise */ 106 #else 107 0, 108 #endif 109 _bus_dmamap_create, 110 _bus_dmamap_destroy, 111 _bus_dmamap_load, 112 _bus_dmamap_load_mbuf, 113 _bus_dmamap_load_uio, 114 _bus_dmamap_load_raw, 115 _bus_dmamap_unload, 116 _bus_dmamap_sync, 117 }; 118 119 int pcibusprint __P((void *auxp, const char *)); 120 int pcibusmatch __P((struct device *, struct cfdata *, void *)); 121 void pcibusattach __P((struct device *, struct device *, void *)); 122 123 static void enable_pci_devices __P((void)); 124 static void insert_into_list __P((PCI_MEMREG *head, struct pci_memreg *elem)); 125 static int overlap_pci_areas __P((struct pci_memreg *p, 126 struct pci_memreg *self, u_int addr, u_int size, u_int what)); 127 128 struct cfattach pcibus_ca = { 129 sizeof(struct device), pcibusmatch, pcibusattach 130 }; 131 132 /* 133 * We need some static storage to probe pci-busses for VGA cards during 134 * early console init. 135 */ 136 static struct atari_bus_space bs_storage[2]; /* 1 iot, 1 memt */ 137 138 int 139 pcibusmatch(pdp, cfp, auxp) 140 struct device *pdp; 141 struct cfdata *cfp; 142 void *auxp; 143 { 144 static int nmatched = 0; 145 146 if (strcmp((char *)auxp, "pcibus")) 147 return (0); /* Wrong number... */ 148 149 if(atari_realconfig == 0) 150 return (1); 151 152 if (machineid & (ATARI_HADES|ATARI_MILAN)) { 153 /* 154 * Both Hades and Milan have only one pci bus 155 */ 156 if (nmatched) 157 return (0); 158 nmatched++; 159 return (1); 160 } 161 return (0); 162 } 163 164 void 165 pcibusattach(pdp, dp, auxp) 166 struct device *pdp, *dp; 167 void *auxp; 168 { 169 struct pcibus_attach_args pba; 170 171 pba.pba_busname = "pci"; 172 pba.pba_pc = NULL; 173 pba.pba_bus = 0; 174 pba.pba_bridgetag = NULL; 175 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 176 pba.pba_dmat = &pci_bus_dma_tag; 177 pba.pba_iot = leb_alloc_bus_space_tag(&bs_storage[0]); 178 pba.pba_memt = leb_alloc_bus_space_tag(&bs_storage[1]); 179 if ((pba.pba_iot == NULL) || (pba.pba_memt == NULL)) { 180 printf("leb_alloc_bus_space_tag failed!\n"); 181 return; 182 } 183 pba.pba_iot->base = PCI_IO_PHYS; 184 pba.pba_memt->base = PCI_MEM_PHYS; 185 186 if (dp == NULL) { 187 /* 188 * Scan the bus for a VGA-card that we support. If we 189 * find one, try to initialize it to a 'standard' text 190 * mode (80x25). 191 */ 192 check_for_vga(pba.pba_iot, pba.pba_memt); 193 return; 194 } 195 196 enable_pci_devices(); 197 198 #if defined(_ATARIHW_) 199 MFP2->mf_aer &= ~(0x27); /* PCI interrupts: HIGH -> LOW */ 200 #endif 201 202 printf("\n"); 203 204 config_found(dp, &pba, pcibusprint); 205 } 206 207 int 208 pcibusprint(auxp, name) 209 void *auxp; 210 const char *name; 211 { 212 if(name == NULL) 213 return(UNCONF); 214 return(QUIET); 215 } 216 217 void 218 pci_attach_hook(parent, self, pba) 219 struct device *parent, *self; 220 struct pcibus_attach_args *pba; 221 { 222 } 223 224 /* 225 * Initialize the PCI-bus. The Atari-BIOS does not do this, so.... 226 * We only disable all devices here. Memory and I/O enabling is done 227 * later at pcibusattach. 228 */ 229 void 230 init_pci_bus() 231 { 232 pci_chipset_tag_t pc = NULL; /* XXX */ 233 pcitag_t tag; 234 pcireg_t csr; 235 int device, id, maxndevs; 236 237 tag = 0; 238 id = 0; 239 240 maxndevs = pci_bus_maxdevs(pc, 0); 241 242 for (device = 0; device < maxndevs; device++) { 243 244 tag = pci_make_tag(pc, 0, device, 0); 245 id = pci_conf_read(pc, tag, PCI_ID_REG); 246 if (id == 0 || id == 0xffffffff) 247 continue; 248 249 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 250 csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE); 251 csr &= ~PCI_COMMAND_MASTER_ENABLE; 252 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 253 } 254 } 255 256 /* 257 * insert a new element in an existing list that the ID's (size in struct 258 * pci_memreg) are sorted. 259 */ 260 static void 261 insert_into_list(head, elem) 262 PCI_MEMREG *head; 263 struct pci_memreg *elem; 264 { 265 struct pci_memreg *p, *q; 266 267 p = LIST_FIRST(head); 268 q = NULL; 269 270 for (; p != NULL && p->size < elem->size; q = p, p = LIST_NEXT(p, link)); 271 272 if (q == NULL) { 273 LIST_INSERT_HEAD(head, elem, link); 274 } else { 275 LIST_INSERT_AFTER(q, elem, link); 276 } 277 } 278 279 /* 280 * Test if a new selected area overlaps with an already (probably preselected) 281 * pci area. 282 */ 283 static int 284 overlap_pci_areas(p, self, addr, size, what) 285 struct pci_memreg *p, *self; 286 u_int addr, size, what; 287 { 288 struct pci_memreg *q; 289 290 if (p == NULL) 291 return 0; 292 293 q = p; 294 while (q != NULL) { 295 if ((q != self) && (q->csr & what)) { 296 if ((addr >= q->address) && (addr < (q->address + q->size))) { 297 #ifdef DEBUG_PCI_MACHDEP 298 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 299 self->dev, self->reg, q->dev, q->reg); 300 #endif 301 return 1; 302 } 303 if ((q->address >= addr) && (q->address < (addr + size))) { 304 #ifdef DEBUG_PCI_MACHDEP 305 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 306 self->dev, self->reg, q->dev, q->reg); 307 #endif 308 return 1; 309 } 310 } 311 q = LIST_NEXT(q, link); 312 } 313 return 0; 314 } 315 316 /* 317 * Enable memory and I/O on pci devices. Care about already enabled devices 318 * (probabaly by the console driver). 319 * 320 * The idea behind the following code is: 321 * We build a by sizes sorted list of the requirements of the different 322 * pci devices. After that we choose the start addresses of that areas 323 * in such a way that they are placed as closed as possible together. 324 */ 325 static void 326 enable_pci_devices() 327 { 328 PCI_MEMREG memlist; 329 PCI_MEMREG iolist; 330 struct pci_memreg *p, *q; 331 int dev, reg, id, class; 332 pcitag_t tag; 333 pcireg_t csr, address, mask; 334 pci_chipset_tag_t pc; 335 int sizecnt, membase_1m; 336 337 pc = 0; 338 csr = 0; 339 tag = 0; 340 341 LIST_INIT(&memlist); 342 LIST_INIT(&iolist); 343 344 /* 345 * first step: go through all devices and gather memory and I/O 346 * sizes 347 */ 348 for (dev = 0; dev < pci_bus_maxdevs(pc,0); dev++) { 349 350 tag = pci_make_tag(pc, 0, dev, 0); 351 id = pci_conf_read(pc, tag, PCI_ID_REG); 352 if (id == 0 || id == 0xffffffff) 353 continue; 354 355 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 356 357 /* 358 * special case: if a display card is found and memory is enabled 359 * preserve 128k at 0xa0000 as vga memory. 360 * XXX: if a display card is found without being enabled, leave 361 * it alone! You will usually only create conflicts by enabeling 362 * it. 363 */ 364 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 365 switch (PCI_CLASS(class)) { 366 case PCI_CLASS_PREHISTORIC: 367 case PCI_CLASS_DISPLAY: 368 if (csr & (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 369 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 370 M_TEMP, M_WAITOK); 371 memset(p, '\0', sizeof(struct pci_memreg)); 372 p->dev = dev; 373 p->csr = csr; 374 p->tag = tag; 375 p->reg = 0; /* there is no register about this */ 376 p->size = 0x20000; /* 128kByte */ 377 p->mask = 0xfffe0000; 378 p->address = 0xa0000; 379 380 insert_into_list(&memlist, p); 381 } 382 else continue; 383 } 384 385 for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) { 386 387 address = pci_conf_read(pc, tag, reg); 388 pci_conf_write(pc, tag, reg, 0xffffffff); 389 mask = pci_conf_read(pc, tag, reg); 390 pci_conf_write(pc, tag, reg, address); 391 if (mask == 0) 392 continue; /* Register unused */ 393 394 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 395 M_TEMP, M_WAITOK); 396 memset(p, '\0', sizeof(struct pci_memreg)); 397 p->dev = dev; 398 p->csr = csr; 399 p->tag = tag; 400 p->reg = reg; 401 p->mask = mask; 402 p->address = 0; 403 404 if (mask & PCI_MAPREG_TYPE_IO) { 405 p->size = PCI_MAPREG_IO_SIZE(mask); 406 407 /* 408 * Align IO if necessary 409 */ 410 if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_IO_ALIGN_MASK)) { 411 p->mask = PCI_MACHDEP_IO_ALIGN_MASK; 412 p->size = PCI_MAPREG_IO_SIZE(p->mask); 413 } 414 415 /* 416 * if I/O is already enabled (probably by the console driver) 417 * save the address in order to take care about it later. 418 */ 419 if (csr & PCI_COMMAND_IO_ENABLE) 420 p->address = address; 421 422 insert_into_list(&iolist, p); 423 } else { 424 p->size = PCI_MAPREG_MEM_SIZE(mask); 425 426 /* 427 * Align memory if necessary 428 */ 429 if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_MEM_ALIGN_MASK)) { 430 p->mask = PCI_MACHDEP_MEM_ALIGN_MASK; 431 p->size = PCI_MAPREG_MEM_SIZE(p->mask); 432 } 433 434 /* 435 * if memory is already enabled (probably by the console driver) 436 * save the address in order to take care about it later. 437 */ 438 if (csr & PCI_COMMAND_MEM_ENABLE) 439 p->address = address; 440 441 insert_into_list(&memlist, p); 442 443 if (PCI_MAPREG_MEM_TYPE(mask) == PCI_MAPREG_MEM_TYPE_64BIT) 444 reg++; 445 } 446 } 447 448 449 #if defined(_ATARIHW_) 450 /* 451 * Both interrupt pin & line are set to the device (== slot) 452 * number. This makes sense on the atari Hades because the 453 * individual slots are hard-wired to a specific MFP-pin. 454 */ 455 csr = (DEV2SLOT(dev) << PCI_INTERRUPT_PIN_SHIFT); 456 csr |= (DEV2SLOT(dev) << PCI_INTERRUPT_LINE_SHIFT); 457 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, csr); 458 #else 459 /* 460 * On the Milan, we accept the BIOS's choice. 461 */ 462 #endif 463 } 464 465 /* 466 * second step: calculate the memory and I/O adresses beginning from 467 * PCI_MEM_START and PCI_IO_START. Care about already mapped areas. 468 * 469 * begin with memory list 470 */ 471 472 address = PCI_MEM_START; 473 sizecnt = 0; 474 membase_1m = 0; 475 p = LIST_FIRST(&memlist); 476 while (p != NULL) { 477 if (!(p->csr & PCI_COMMAND_MEM_ENABLE)) { 478 if (PCI_MAPREG_MEM_TYPE(p->mask) == PCI_MAPREG_MEM_TYPE_32BIT_1M) { 479 if (p->size > membase_1m) 480 membase_1m = p->size; 481 do { 482 p->address = membase_1m; 483 membase_1m += p->size; 484 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 485 p->size, PCI_COMMAND_MEM_ENABLE)); 486 if (membase_1m > 0x00100000) { 487 /* 488 * Should we panic here? 489 */ 490 printf("\npcibus0: dev %d reg %d: memory not configured", 491 p->dev, p->reg); 492 p->reg = 0; 493 } 494 } else { 495 496 if (sizecnt && (p->size > sizecnt)) 497 sizecnt = ((p->size + sizecnt) & p->mask) & 498 PCI_MAPREG_MEM_ADDR_MASK; 499 if (sizecnt > address) { 500 address = sizecnt; 501 sizecnt = 0; 502 } 503 504 do { 505 p->address = address + sizecnt; 506 sizecnt += p->size; 507 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 508 p->size, PCI_COMMAND_MEM_ENABLE)); 509 510 if ((address + sizecnt) > PCI_MEM_END) { 511 /* 512 * Should we panic here? 513 */ 514 printf("\npcibus0: dev %d reg %d: memory not configured", 515 p->dev, p->reg); 516 p->reg = 0; 517 } 518 } 519 if (p->reg > 0) { 520 pci_conf_write(pc, p->tag, p->reg, p->address); 521 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 522 csr |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 523 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 524 p->csr = csr; 525 } 526 } 527 p = LIST_NEXT(p, link); 528 } 529 530 /* 531 * now the I/O list 532 */ 533 534 address = PCI_IO_START; 535 sizecnt = 0; 536 p = LIST_FIRST(&iolist); 537 while (p != NULL) { 538 if (!(p->csr & PCI_COMMAND_IO_ENABLE)) { 539 540 if (sizecnt && (p->size > sizecnt)) 541 sizecnt = ((p->size + sizecnt) & p->mask) & 542 PCI_MAPREG_IO_ADDR_MASK; 543 if (sizecnt > address) { 544 address = sizecnt; 545 sizecnt = 0; 546 } 547 548 do { 549 p->address = address + sizecnt; 550 sizecnt += p->size; 551 } while (overlap_pci_areas(LIST_FIRST(&iolist), p, p->address, 552 p->size, PCI_COMMAND_IO_ENABLE)); 553 554 if ((address + sizecnt) > PCI_IO_END) { 555 /* 556 * Should we panic here? 557 */ 558 printf("\npcibus0: dev %d reg %d: io not configured", 559 p->dev, p->reg); 560 } else { 561 pci_conf_write(pc, p->tag, p->reg, p->address); 562 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 563 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 564 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 565 p->csr = csr; 566 } 567 } 568 p = LIST_NEXT(p, link); 569 } 570 571 #ifdef DEBUG_PCI_MACHDEP 572 printf("\nI/O List:\n"); 573 p = LIST_FIRST(&iolist); 574 575 while (p != NULL) { 576 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 577 p->reg, p->size, p->address); 578 p = LIST_NEXT(p, link); 579 } 580 printf("\nMemlist:"); 581 p = LIST_FIRST(&memlist); 582 583 while (p != NULL) { 584 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 585 p->reg, p->size, p->address); 586 p = LIST_NEXT(p, link); 587 } 588 #endif 589 590 /* 591 * Free the lists 592 */ 593 p = LIST_FIRST(&iolist); 594 while (p != NULL) { 595 q = p; 596 LIST_REMOVE(q, link); 597 free(p, M_WAITOK); 598 p = LIST_FIRST(&iolist); 599 } 600 p = LIST_FIRST(&memlist); 601 while (p != NULL) { 602 q = p; 603 LIST_REMOVE(q, link); 604 free(p, M_WAITOK); 605 p = LIST_FIRST(&memlist); 606 } 607 } 608 609 pcitag_t 610 pci_make_tag(pc, bus, device, function) 611 pci_chipset_tag_t pc; 612 int bus, device, function; 613 { 614 return ((bus << 16) | (device << 11) | (function << 8)); 615 } 616 617 void 618 pci_decompose_tag(pc, tag, bp, dp, fp) 619 pci_chipset_tag_t pc; 620 pcitag_t tag; 621 int *bp, *dp, *fp; 622 { 623 624 if (bp != NULL) 625 *bp = (tag >> 16) & 0xff; 626 if (dp != NULL) 627 *dp = (tag >> 11) & 0x1f; 628 if (fp != NULL) 629 *fp = (tag >> 8) & 0x7; 630 } 631 632 int 633 pci_intr_map(pa, ihp) 634 struct pci_attach_args *pa; 635 pci_intr_handle_t *ihp; 636 { 637 int line = pa->pa_intrline; 638 639 #if defined(_MILANHW_) 640 /* 641 * On the Hades, the 'pin' info is useless. 642 */ 643 { 644 int pin = pa->pa_intrpin; 645 646 if (pin == 0) { 647 /* No IRQ used. */ 648 goto bad; 649 } 650 if (pin > PCI_INTERRUPT_PIN_MAX) { 651 printf("pci_intr_map: bad interrupt pin %d\n", pin); 652 goto bad; 653 } 654 } 655 #endif /* _MILANHW_ */ 656 657 /* 658 * According to the PCI-spec, 255 means `unknown' or `no connection'. 659 * Interpret this as 'no interrupt assigned'. 660 */ 661 if (line == 255) 662 goto bad; 663 664 /* 665 * Values are pretty useless on the Hades since all interrupt 666 * lines for a card are tied together and hardwired to a 667 * specific TT-MFP I/O port. 668 * On the Milan, they are tied to the ICU. 669 */ 670 #if defined(_MILANHW_) 671 if (line >= 16) { 672 printf("pci_intr_map: bad interrupt line %d\n", line); 673 goto bad; 674 } 675 if (line == 2) { 676 printf("pci_intr_map: changed line 2 to line 9\n"); 677 line = 9; 678 } 679 /* Assume line == 0 means unassigned */ 680 if (line == 0) 681 goto bad; 682 #endif 683 *ihp = line; 684 return 0; 685 686 bad: 687 *ihp = -1; 688 return 1; 689 } 690 691 const char * 692 pci_intr_string(pc, ih) 693 pci_chipset_tag_t pc; 694 pci_intr_handle_t ih; 695 { 696 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 697 698 if (ih == -1) 699 panic("pci_intr_string: bogus handle 0x%x\n", ih); 700 701 sprintf(irqstr, "irq %d", ih); 702 return (irqstr); 703 704 } 705 706 const struct evcnt * 707 pci_intr_evcnt(pc, ih) 708 pci_chipset_tag_t pc; 709 pci_intr_handle_t ih; 710 { 711 712 /* XXX for now, no evcnt parent reported */ 713 return NULL; 714 } 715