1 /* $NetBSD: aicavar.h,v 1.3 2005/12/11 12:17:06 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2003 SHIMIZU Ryo <ryo@misakimix.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef _AICAVAR_H_ 32 #define _AICAVAR_H_ 33 34 typedef struct { 35 uint32_t serial; 36 uint32_t command; 37 uint32_t blocksize; 38 uint32_t channel; 39 uint32_t rate; 40 uint32_t precision; 41 uint32_t l_param; /* volume,etc... for left */ 42 uint32_t r_param; /* volume,etc... for right */ 43 } aica_cmd_t; 44 45 #define AICA_COMMAND_NOP 0 46 #define AICA_COMMAND_PLAY 1 47 #define AICA_COMMAND_STOP 2 48 #define AICA_COMMAND_INIT 3 49 #define AICA_COMMAND_MVOL 4 50 #define AICA_COMMAND_VOL 5 51 52 #define AICA_ARM_CODE 0x00000000 /* text+data+bss+stack 53 0x00000000-0x0000ff00 */ 54 #define AICA_ARM_CMD 0x0000ff00 /* SH4<->ARM work for 55 communication */ 56 #define AICA_ARM_CMDADDR(x) (AICA_ARM_CMD + offsetof(aica_cmd_t, x)) 57 #define AICA_ARM_CMD_SERIAL AICA_ARM_CMDADDR(serial) 58 #define AICA_ARM_CMD_COMMAND AICA_ARM_CMDADDR(command) 59 #define AICA_ARM_CMD_BLOCKSIZE AICA_ARM_CMDADDR(blocksize) 60 #define AICA_ARM_CMD_CHANNEL AICA_ARM_CMDADDR(channel) 61 #define AICA_ARM_CMD_RATE AICA_ARM_CMDADDR(rate) 62 #define AICA_ARM_CMD_PRECISION AICA_ARM_CMDADDR(precision) 63 #define AICA_ARM_CMD_LPARAM AICA_ARM_CMDADDR(l_param) 64 #define AICA_ARM_CMD_RPARAM AICA_ARM_CMDADDR(r_param) 65 66 #define AICA_ARM_END 0x00010000 67 68 #define AICA_DMABUF_START 0x00010000 69 #define AICA_DMABUF_LEFT 0x00010000 /* DMA buffer for PLAY 70 0x00010000-0x0001FFFF */ 71 #define AICA_DMABUF_RIGHT 0x00020000 /* DMA buffer for PLAY 72 0x00020000-0x0002FFFF */ 73 #define AICA_DMABUF_MONO AICA_DMABUF_LEFT 74 #define AICA_DMABUF_END 0x00030000 75 76 #define AICA_DMABUF_SIZE 0x0000ffc0 77 78 #define AICA_MEMORY_END 0x00200000 79 80 81 #define L256TO16(l) (((l) >> 4) & 0x0f) 82 #define L16TO256(l) ((((l) << 4) & 0xf0) + ((l) & 0x0f)) 83 84 85 enum MIXER_CLASS { 86 AICA_MASTER_VOL = 0, 87 AICA_OUTPUT_GAIN, 88 AICA_OUTPUT_CLASS, 89 90 AICA_NDEVS 91 }; 92 93 #endif /* _AICAVAR_H_ */ 94 95