1 /* $NetBSD: ifpga_intr.c,v 1.9 2010/12/20 00:25:31 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef EVBARM_SPL_NOINLINE 39 #define EVBARM_SPL_NOINLINE 40 #endif 41 42 /* 43 * Interrupt support for the Integrator FPGA. 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/bus.h> 50 #include <sys/intr.h> 51 52 #include <arm/cpufunc.h> 53 54 #include <evbarm/ifpga/ifpgareg.h> 55 #include <evbarm/ifpga/ifpgavar.h> 56 57 /* Interrupt handler queues. */ 58 struct intrq intrq[NIRQ]; 59 60 /* Interrupts to mask at each level. */ 61 int ifpga_imask[NIPL]; 62 63 /* Interrupts pending. */ 64 volatile int ifpga_ipending; 65 66 /* Software copy of the IRQs we have enabled. */ 67 volatile uint32_t intr_enabled; 68 69 /* Mask if interrupts steered to FIQs. */ 70 uint32_t intr_steer; 71 72 /* 73 * Interrupt bit names. 74 */ 75 const char * const ifpga_irqnames[] = { 76 "soft", /* 0 */ 77 "uart 0", /* 1 */ 78 "uart 1", /* 2 */ 79 "kbd", /* 3 */ 80 "mouse", /* 4 */ 81 "tmr 0", /* 5 */ 82 "tmr 1 hard", /* 6 */ 83 "tmr 2 stat", /* 7 */ 84 "rtc", /* 8 */ 85 "exp 0", /* 9 */ 86 "exp 1", /* 10 */ 87 "exp 2", /* 11 */ 88 "exp 3", /* 12 */ 89 "pci 0", /* 13 */ 90 "pci 1", /* 14 */ 91 "pci 2", /* 15 */ 92 "pci 3", /* 16 */ 93 "V3 br", /* 17 */ 94 "deg", /* 18 */ 95 "enum", /* 19 */ 96 "pci lb", /* 20 */ 97 "autoPC", /* 21 */ 98 "irq 22", /* 22 */ 99 "irq 23", /* 23 */ 100 "irq 24", /* 24 */ 101 "irq 25", /* 25 */ 102 "irq 26", /* 26 */ 103 "irq 27", /* 27 */ 104 "irq 28", /* 28 */ 105 "irq 29", /* 29 */ 106 "irq 30", /* 30 */ 107 "irq 31", /* 31 */ 108 }; 109 110 void ifpga_intr_dispatch(struct clockframe *frame); 111 112 extern struct ifpga_softc *ifpga_sc; 113 114 static inline uint32_t 115 ifpga_iintsrc_read(void) 116 { 117 return bus_space_read_4(ifpga_sc->sc_iot, ifpga_sc->sc_irq_ioh, 118 IFPGA_INTR_STATUS); 119 } 120 121 static inline void 122 ifpga_enable_irq(int irq) 123 { 124 125 intr_enabled |= (1U << irq); 126 ifpga_set_intrmask(); 127 } 128 129 static inline void 130 ifpga_disable_irq(int irq) 131 { 132 133 intr_enabled &= ~(1U << irq); 134 ifpga_set_intrmask(); 135 } 136 137 /* 138 * NOTE: This routine must be called with interrupts disabled in the CPSR. 139 */ 140 static void 141 ifpga_intr_calculate_masks(void) 142 { 143 struct intrq *iq; 144 struct intrhand *ih; 145 int irq, ipl; 146 147 /* First, figure out which IPLs each IRQ has. */ 148 for (irq = 0; irq < NIRQ; irq++) { 149 int levels = 0; 150 iq = &intrq[irq]; 151 ifpga_disable_irq(irq); 152 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 153 ih = TAILQ_NEXT(ih, ih_list)) 154 levels |= (1U << ih->ih_ipl); 155 iq->iq_levels = levels; 156 } 157 158 /* Next, figure out which IRQs are used by each IPL. */ 159 for (ipl = 0; ipl < NIPL; ipl++) { 160 int irqs = 0; 161 for (irq = 0; irq < NIRQ; irq++) { 162 if (intrq[irq].iq_levels & (1U << ipl)) 163 irqs |= (1U << irq); 164 } 165 ifpga_imask[ipl] = irqs; 166 } 167 168 KASSERT(ifpga_imask[IPL_NONE] == 0); 169 170 /* 171 * Enforce a hierarchy that gives "slow" device (or devices with 172 * limited input buffer space/"real-time" requirements) a better 173 * chance at not dropping data. 174 */ 175 ifpga_imask[IPL_VM] |= 0; 176 ifpga_imask[IPL_SCHED] |= ifpga_imask[IPL_VM]; 177 ifpga_imask[IPL_HIGH] |= ifpga_imask[IPL_SCHED]; 178 179 /* 180 * Now compute which IRQs must be blocked when servicing any 181 * given IRQ. 182 */ 183 for (irq = 0; irq < NIRQ; irq++) { 184 int irqs = (1U << irq); 185 iq = &intrq[irq]; 186 if (TAILQ_FIRST(&iq->iq_list) != NULL) 187 ifpga_enable_irq(irq); 188 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 189 ih = TAILQ_NEXT(ih, ih_list)) 190 irqs |= ifpga_imask[ih->ih_ipl]; 191 iq->iq_mask = irqs; 192 } 193 } 194 195 void 196 splx(int new) 197 { 198 199 ifpga_splx(new); 200 } 201 202 int 203 _spllower(int ipl) 204 { 205 206 return (ifpga_spllower(ipl)); 207 } 208 209 int 210 _splraise(int ipl) 211 { 212 213 return (ifpga_splraise(ipl)); 214 } 215 216 /* 217 * ifpga_intr_init: 218 * 219 * Initialize the rest of the interrupt subsystem, making it 220 * ready to handle interrupts from devices. 221 */ 222 void 223 ifpga_intr_init(void) 224 { 225 struct intrq *iq; 226 int i; 227 228 intr_enabled = 0; 229 230 for (i = 0; i < NIRQ; i++) { 231 iq = &intrq[i]; 232 TAILQ_INIT(&iq->iq_list); 233 234 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 235 NULL, "ifpga", ifpga_irqnames[i]); 236 } 237 } 238 239 void 240 ifpga_intr_postinit(void) 241 { 242 ifpga_intr_calculate_masks(); 243 244 /* Enable IRQs (don't yet use FIQs). */ 245 enable_interrupts(I32_bit); 246 } 247 248 void * 249 ifpga_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 250 { 251 struct intrq *iq; 252 struct intrhand *ih; 253 u_int oldirqstate; 254 255 if (irq < 0 || irq > NIRQ) 256 panic("ifpga_intr_establish: IRQ %d out of range", irq); 257 258 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 259 if (ih == NULL) 260 return (NULL); 261 262 ih->ih_func = func; 263 ih->ih_arg = arg; 264 ih->ih_ipl = ipl; 265 ih->ih_irq = irq; 266 267 iq = &intrq[irq]; 268 269 /* All IOP321 interrupts are level-triggered. */ 270 iq->iq_ist = IST_LEVEL; 271 272 oldirqstate = disable_interrupts(I32_bit); 273 274 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 275 276 ifpga_intr_calculate_masks(); 277 278 restore_interrupts(oldirqstate); 279 280 return (ih); 281 } 282 283 void 284 ifpga_intr_disestablish(void *cookie) 285 { 286 struct intrhand *ih = cookie; 287 struct intrq *iq = &intrq[ih->ih_irq]; 288 int oldirqstate; 289 290 oldirqstate = disable_interrupts(I32_bit); 291 292 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 293 294 ifpga_intr_calculate_masks(); 295 296 restore_interrupts(oldirqstate); 297 } 298 299 void 300 ifpga_intr_dispatch(struct clockframe *frame) 301 { 302 struct intrq *iq; 303 struct intrhand *ih; 304 int oldirqstate, pcpl, irq, ibit, hwpend; 305 struct cpu_info * const ci = curcpu(); 306 307 pcpl = ci->ci_cpl; 308 309 hwpend = ifpga_iintsrc_read(); 310 311 /* 312 * Disable all the interrupts that are pending. We will 313 * reenable them once they are processed and not masked. 314 */ 315 intr_enabled &= ~hwpend; 316 ifpga_set_intrmask(); 317 318 /* Wait for these interrupts to be suppressed. */ 319 while ((ifpga_iintsrc_read() & hwpend) != 0) 320 ; 321 322 while (hwpend != 0) { 323 irq = ffs(hwpend) - 1; 324 ibit = (1U << irq); 325 326 hwpend &= ~ibit; 327 328 if (pcpl & ibit) { 329 /* 330 * IRQ is masked; mark it as pending and check 331 * the next one. Note: the IRQ is already disabled. 332 */ 333 ifpga_ipending |= ibit; 334 continue; 335 } 336 337 ifpga_ipending &= ~ibit; 338 339 iq = &intrq[irq]; 340 iq->iq_ev.ev_count++; 341 ci->ci_data.cpu_nintr++; 342 ci->ci_cpl |= iq->iq_mask; 343 oldirqstate = enable_interrupts(I32_bit); 344 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 345 ih = TAILQ_NEXT(ih, ih_list)) { 346 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 347 } 348 restore_interrupts(oldirqstate); 349 ci->ci_cpl = pcpl; 350 351 hwpend |= (ifpga_ipending & IFPGA_INTR_HWMASK) & ~pcpl; 352 353 /* Re-enable this interrupt now that's it's cleared. */ 354 intr_enabled |= ibit; 355 ifpga_set_intrmask(); 356 } 357 358 #ifdef __HAVE_FAST_SOFTINTS 359 cpu_dosoftints(); 360 #endif 361 } 362