1 /* $NetBSD: ifpgamem.h,v 1.1 2001/10/27 16:19:09 rearnsha Exp $ */ 2 3 /* 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * Physical memory map provided by the integrator FPGA 34 */ 35 36 #define IFPGA_SDRAM_BASE 0x00000000 37 #define IFPGA_SDRAM_SIZE 0x10000000 /* 256 MB */ 38 39 #define IFPGA_SSRAM_BASE 0x00000000 /* Overlaps SDRAM */ 40 #define IFPGA_SSRAM_SIZE 0x00040000 /* 256 KB */ 41 42 #define IFPGA_IO_BASE 0x10000000 43 #define IFPGA_IO_SIZE 0x10000000 /* 256 KB */ 44 45 #define IFPGA_IO_CM_BASE 0x00000000 /* Core module regs */ 46 #define IFPGA_IO_CM_SIZE 0x00000200 47 48 #define IFPGA_IO_SC_BASE 0x01000000 /* System Ctrl regs */ 49 #define IFPGA_IO_SC_SIZE 0x00000028 50 51 #define IFPGA_IO_TMR_BASE 0x03000000 /* Countr/timr regs */ 52 #define IFPGA_IO_TMR_SIZE 0x00000210 53 54 #define IFPGA_IO_IRQ_BASE 0x04000000 /* IRQ controller */ 55 #define IFPGA_IO_IRQ_SIZE 0x00000100 56 57 #define IFPGA_TIMER0_BASE 0x00000000 58 #define IFPGA_TIMER1_BASE 0x00000100 59 #define IFPGA_TIMER2_BASE 0x00000200 60 61 #define IFPGA_TIMER0_IRQ 5 62 #define IFPGA_TIMER1_IRQ 6 63 #define IFPGA_TIMER2_IRQ 7 64 65 #define IFPGA_TIMER1_FREQ 24000000 /* 24 MHz */ 66 #define IFPGA_TIMER2_FREQ 24000000 /* 24 MHz */ 67 68 #define IFPGA_EBI_ROM_BASE 0x20000000 69 #define IFPGA_EBI_ROM_SIZE 0x04000000 /* 64MB */ 70 71 #define IFPGA_EBI_FLASH_BASE 0x24000000 72 #define IFPGA_EBI_FLASH_SIZE 0x04000000 /* 64MB */ 73 74 #define IFPGA_EBI_SSRAM_BASE 0x28000000 75 #define IFPGA_EBI_SSRAM_SIZE 0x04000000 /* 64MB */ 76 77 #define IFPGA_PCI_BASE 0x40000000 /* Base of entire PCI 78 subsystem. */ 79 80 #define IFPGA_PCI_APP0_BASE 0x40000000 81 #define IFPGA_PCI_APP0_SIZE 0x10000000 /* 256MB */ 82 83 #define IFPGA_PCI_APP1_BASE 0x50000000 84 #define IFPGA_PCI_APP1_SIZE 0x10000000 /* 256MB */ 85 86 #define IFPGA_PCI_IO_BASE 0x60000000 /* Absolute */ 87 #define IFPGA_PCI_IO_VBASE 0xfe000000 88 #define IFPGA_PCI_IO_VSIZE 0x01000000 /* 16MB */ 89 90 #define IFPGA_PCI_CONF_BASE 0x61000000 /* Absolute */ 91 #define IFPGA_PCI_CONF_VBASE 0xff000000 92 #define IFPGA_PCI_CONF_VSIZE 0x01000000 /* 16MB */ 93 94 #define IFPGA_V360_REG_BASE 0x62000000 95 #define IFPGA_V360_REG_SIZE 0x00010000 /* 64K */ 96 97 /* Core module alias memory. */ 98 #define IFPGA_CM_ALIAS_BASE 0x80000000 99 100 /* Logic module memory. */ 101 #define IFPGA_LM_BASE 0xc0000000 102 103