1 /* $NetBSD: ifpgareg.h,v 1.1 2001/10/27 16:19:09 rearnsha Exp $ */ 2 3 /* 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* System clock defaults. */ 33 34 #define IFPGA_UART_CLK 14745600 /* Uart REFCLK freq */ 35 36 /* 37 * IFPGA registers 38 */ 39 40 /* Core module */ 41 #define IFPGA_CM_ID 0x00000000 /* ID register */ 42 #define IFPGA_CM_PROC 0x00000004 /* Processor Reg */ 43 #define IFPGA_CM_OSC 0x00000008 /* Oscillator ctrl */ 44 #define IFPGA_CM_CTRL 0x0000000c /* Control Reg */ 45 #define IFPGA_CM_STAT 0x00000010 /* Status Reg */ 46 #define IFPGA_CM_LOCK 0x00000014 /* Lock */ 47 #define IFPGA_CM_SDRAM 0x00000020 /* SDRAM stat/ctrl */ 48 #define IFPGA_CM_IRQ_STAT 0x00000040 /* IRQ Status */ 49 #define IFPGA_CM_IRQ_RSTAT 0x00000044 /* IRQ Raw status */ 50 #define IFPGA_CM_IRQ_ENSET 0x00000048 /* IRQ Enable set */ 51 #define IFPGA_CM_IRQ_ENCLR 0x0000004c /* IRQ Enable clr */ 52 #define IFPGA_CM_SOFT_INTSET 0x00000050 /* S/W Int set */ 53 #define IFPGA_CM_SOFT_INTCLR 0x00000054 /* S/W Int clr */ 54 #define IFPGA_CM_FIQ_STAT 0x00000060 /* FIQ Status */ 55 #define IFPGA_CM_FIQ_RSTAT 0x00000064 /* FIQ Raw Status */ 56 #define IFPGA_CM_FIQ_ENSET 0x00000068 /* FIQ Enable set */ 57 #define IFPGA_CM_FIQ_ENCLR 0x0000006c /* FIQ Enable clr */ 58 #define IFPGA_CM_SPD 0x00000100 /* SDRAM SPD memory */ 59 60 /* CM-ARM10200 module only */ 61 #define IFPGA_CM_LMBUSCNT 0x00000018 /* LMBUS counter */ 62 #define IFPGA_CM_AUXOSC 0x0000001c /* Aux Oscillator */ 63 #define IFPGA_CM_INIT 0x00000024 /* Initialization */ 64 #define IFPGA_CM_REFCNT 0x00000028 /* 24MHz counter */ 65 #define IFPGA_CM_FLAGS 0x00000030 /* Flags reg ? */ 66 #define IFPGA_CM_FLAGSS 0x00000030 /* Flags set */ 67 #define IFPGA_CM_FLAGSC 0x00000034 /* Flags clr */ 68 #define IFPGA_CM_NVFLAGS 0x00000038 /* NVFlags reg ? */ 69 #define IFPGA_CM_NVFLAGSS 0x00000038 /* NVFlags set */ 70 #define IFPGA_CM_NVFLAGSC 0x0000003c /* NVFlags clr */ 71 72 /* CM_ID reg */ 73 #define IFPGA_CM_ID_MAN_MASK 0xff000000 /* Manufacturer ID */ 74 #define IFPGA_CM_ID_MAN_ARM 0x41000000 /* ARM Ltd */ 75 #define IFPGA_CM_ID_ARCH_MASK 0x00ff0000 /* Architecture */ 76 #define IFPGA_CM_ID_ARCH_ASBLE 0x00000000 /* ASB Little-endian */ 77 #define IFPGA_CM_ID_ARCH_AHBLE 0x00010000 /* AHB Little-endian */ 78 #define IFPGA_CM_ID_FPGA_MASK 0x0000f000 /* FPGA type */ 79 #define IFPGA_CM_ID_FPGA_XC4036 0x00000000 /* XC4036 */ 80 #define IFPGA_CM_ID_FPGA_XCV600 0x00003000 /* XCV600 */ 81 #define IFPGA_CM_ID_BUILD_MASK 0x00000ff0 /* Build number */ 82 #define IFPGA_CM_ID_BUILD_SHIFT 4 83 #define IFPGA_CM_ID_REV_MASK 0x0000000f /* Revision number */ 84 #define IFPGA_CM_ID_REV_A 0x00000000 /* Revision A */ 85 #define IFPGA_CM_ID_REV_B 0x00000001 /* Revision B */ 86 87 /* System controller */ 88 #define IFPGA_SC_ID 0x00000000 /* ID register */ 89 #define IFPGA_SC_OSC 0x00000004 /* Oscillator ctrl */ 90 #define IFPGA_SC_CTRLS 0x00000008 /* Ctrl Regs Set */ 91 #define IFPGA_SC_CTRLC 0x0000000c /* Ctrl Regs Clr */ 92 #define IFPGA_SC_DEC 0x00000010 /* Decoder status */ 93 #define IFPGA_SC_ARB 0x00000014 /* Arbiter time-out */ 94 #define IFPGA_SC_PCI 0x00000018 /* PIC Ctrl */ 95 #define IFPGA_SC_LOCK 0x0000001c /* Lock */ 96 #define IFPGA_SC_LBFADDR 0x00000020 /* PCI Lbus flt addr */ 97 #define IFPGA_SC_LBFCODE 0x00000024 /* PCI Lbus flt code */ 98 99 /* SC_ID reg */ 100 #define IFPGA_SC_ID_MAN_MASK 0xff000000 /* Manufacturer ID */ 101 #define IFPGA_SC_ID_MAN_ARM 0x41000000 /* ARM Ltd */ 102 #define IFPGA_SC_ID_ARCH_MASK 0x00ff0000 /* Architecture */ 103 #define IFPGA_SC_ID_ARCH_ASBLE 0x00000000 /* ASB Little-endian */ 104 #define IFPGA_SC_ID_ARCH_AHBLE 0x00010000 /* AHB Little-endian */ 105 #define IFPGA_SC_ID_FPGA_MASK 0x0000f000 /* FPGA type */ 106 #define IFPGA_SC_ID_FPGA_XC4062 0x00001000 /* XC4062 */ 107 #define IFPGA_SC_ID_FPGA_XC4085 0x00002000 /* XC4085 */ 108 #define IFPGA_SC_ID_BUILD_MASK 0x00000ff0 /* Build number */ 109 #define IFPGA_SC_ID_BUILD_SHIFT 4 110 #define IFPGA_SC_ID_REV_MASK 0x0000000f /* Revision number */ 111 #define IFPGA_SC_ID_REV_A 0x00000000 /* Revision A */ 112 #define IFPGA_SC_ID_REV_B 0x00000001 /* Revision B */ 113 114 /* SC_OSC reg */ 115 #define IFPGA_SC_OSC_DIV_X_Y 0x80 116 #define IFPGA_SC_OSC_S_VDW 0x7f 117 118 /* SC_CTRLS & SC_CTRLC regs */ 119 #define IFPGA_SC_CTRL_UART0RTS 0x80 /* Active low */ 120 #define IFPGA_SC_CTRL_UART0DTR 0x40 /* Active low */ 121 #define IFPGA_SC_CTRL_UART1RTS 0x20 /* Active low */ 122 #define IFPGA_SC_CTRL_UART1DTR 0x10 /* Active low */ 123 #define IFPGA_SC_CTRL_FLASHWP 0x04 /* W/P Flash */ 124 #define IFPGA_SC_CTRL_FLASHVPP 0x02 /* Flash VPP enable */ 125 #define IFPGA_SC_CTRL_SOFTRESET 0x01 /* Board reset */ 126 127 /* SC_DEC reg (read-only) */ 128 #define IFPGA_SC_DEC_EXP_MASK 0xf0 /* EXP connector */ 129 #define IFPGA_SC_DEC_EXP_SHIFT 4 130 #define IFPGA_SC_DEC_HDR_MASK 0x0f /* HDR connector */ 131 #define IFPGA_SC_DEC_HDR_SHIFT 0 132 133 /* SC_ARB reg */ 134 #define IFPGA_SC_ARB_CCOUNT_MASK 0xffffff00 /* Cycle counter */ 135 #define IFPGA_SC_ARB_CCOUNT_SHIFT 8 136 #define IFPGA_SC_ARB_TCOUNT_MASK 0xffffff00 /* Transaction cntr */ 137 #define IFPGA_SC_ARB_TCOUNT_SHIFT 0 138 139 /* SC_PCI reg */ 140 #define IFPGA_SC_PCI_PCIEN 0x02 /* PCI Enable */ 141 #define IFPGA_SC_PCI_LBINT_CLR 0x01 /* LB interrupt clr */ 142 143 /* SC_LOCK reg */ 144 #define IFPGA_SC_LOCK_LCK 0x00010000 /* Is locked */ 145 #define IFPGA_SC_LOCK_MASK 0x0000ffff /* Key */ 146 #define IFPGA_SC_LOCK_KEY 0x0000a05f /* Key */ 147 148 /* SC_LBFADDR reg */ 149 150 /* SC_LBFCODE reg */ 151 #define IFPGA_SC_LBFCODE_BEN3 0x80 /* Byte enable 3 */ 152 #define IFPGA_SC_LBFCODE_BEN2 0x40 /* Byte enable 2 */ 153 #define IFPGA_SC_LBFCODE_BEN1 0x10 /* Byte enable 1 */ 154 #define IFPGA_SC_LBFCODE_BEN1 0x10 /* Byte enable 0 */ 155 #define IFPGA_SC_LBFCODE_LBURST 0x08 /* Burst */ 156 #define IFPGA_SC_LBFCODE_LREAD 0x04 /* Read */ 157 #define IFPGA_SC_LBFCODE_MASTER 0x02 /* Master */ 158 #define IFPGA_SC_LBFCODE_RLBFINT 0x01 /* Raw LBNT */ 159 160 /* Counter/Timer registers */ 161 162 #define TIMERx_LOAD 0x00 /* Load register */ 163 #define TIMERx_VALUE 0x04 /* Current value */ 164 #define TIMERx_CTRL 0x08 /* Control */ 165 #define TIMERx_CLR 0x0c /* Clear */ 166 167 #define TIMERx_MAX 0xffff /* Max count value */ 168 169 #define TIMERx_CTRL_ENABLE 0x80 /* Timer enable */ 170 #define TIMERx_CTRL_MODE_ONCE 0x00 /* Single shot */ 171 #define TIMERx_CTRL_MODE_PERIODIC 0x40 /* Single shot */ 172 #define TIMERx_CTRL_PRESCALE_DIV1 0x00 /* CLK / 1 */ 173 #define TIMERx_CTRL_PRESCALE_DIV16 0x04 /* CLK / 16 */ 174 #define TIMERx_CTRL_PRESCALE_DIV256 0x08 /* CLK / 256 */ 175 176 /* Interrupt registers */ 177 /* Bit positions... */ 178 #define IFPGA_INTR_APCINT 0x00200000 179 #define IFPGA_INTR_PCILBINT 0x00100000 180 #define IFPGA_INTR_ENUMINT 0x00080000 181 #define IFPGA_INTR_DEGINT 0x00040000 182 #define IFPGA_INTR_LINT 0x00020000 183 #define IFPGA_INTR_PCIINT3 0x00010000 184 #define IFPGA_INTR_PCIINT2 0x00008000 185 #define IFPGA_INTR_PCIINT1 0x00004000 186 #define IFPGA_INTR_PCIINT0 0x00002000 187 #define IFPGA_INTR_EXPINT3 0x00001000 188 #define IFPGA_INTR_EXPINT2 0x00000800 189 #define IFPGA_INTR_EXPINT1 0x00000400 190 #define IFPGA_INTR_EXPINT0 0x00000200 191 #define IFPGA_INTR_RTCINT 0x00000100 192 #define IFPGA_INTR_TIMERINT2 0x00000080 193 #define IFPGA_INTR_TIMERINT1 0x00000040 194 #define IFPGA_INTR_TIMERINT0 0x00000020 195 #define IFPGA_INTR_MOUSEINT 0x00000010 196 #define IFPGA_INTR_KBDINT 0x00000008 197 #define IFPGA_INTR_UARTINT1 0x00000004 198 #define IFPGA_INTR_UARTINT0 0x00000002 199 #define IFPGA_INTR_SOFTINT 0x00000001 200 /* ... and the corresponding numbers. */ 201 #define IFPGA_INTRNUM_APCINT 21 202 #define IFPGA_INTRNUM_PCILBINT 20 203 #define IFPGA_INTRNUM_ENUMINT 19 204 #define IFPGA_INTRNUM_DEGINT 18 205 #define IFPGA_INTRNUM_LINT 17 206 #define IFPGA_INTRNUM_PCIINT3 16 207 #define IFPGA_INTRNUM_PCIINT2 15 208 #define IFPGA_INTRNUM_PCIINT1 14 209 #define IFPGA_INTRNUM_PCIINT0 13 210 #define IFPGA_INTRNUM_EXPINT3 12 211 #define IFPGA_INTRNUM_EXPINT2 11 212 #define IFPGA_INTRNUM_EXPINT1 10 213 #define IFPGA_INTRNUM_EXPINT0 9 214 #define IFPGA_INTRNUM_RTCINT 8 215 #define IFPGA_INTRNUM_TIMERINT2 7 216 #define IFPGA_INTRNUM_TIMERINT1 6 217 #define IFPGA_INTRNUM_TIMERINT0 5 218 #define IFPGA_INTRNUM_MOUSEINT 4 219 #define IFPGA_INTRNUM_KBDINT 3 220 #define IFPGA_INTRNUM_UARTINT1 2 221 #define IFPGA_INTRNUM_UARTINT0 1 222 #define IFPGA_INTRNUM_SOFTINT 0 223 224 #define IFPGA_INTR_STATUS 0x0 /* Offset to status reg */ 225 #define IFPGA_INTR_RAWSTAT 0x4 /* Offset to raw reg */ 226 #define IFPGA_INTR_ENABLESET 0x8 /* Offset to Enable-Set */ 227 #define IFPGA_INTR_ENABLECLR 0xc /* Offset to Enable-Clear */ 228 229 #define IFPGA_IRQ0 0x00 230 #define IFPGA_IRQ1 0x40 231 #define IFPGA_IRQ2 0x80 232 #define IFPGA_IRQ3 0xc0 233 #define IFPGA_FIQ0 0x20 234 #define IFPGA_FIQ1 0x60 235 #define IFPGA_FIQ2 0xa0 236 #define IFPGA_FIQ3 0xe0 237 238 /* Peripheral registers */ 239 240 /* Real time clock */ 241 242 #define IFPGA_RTC_DR 0x00 243 #define IFPGA_RTC_MR 0x04 244 #define IFPGA_RTC_STAT 0x08 245 #define IFPGA_RTC_EOI 0x08 246 #define IFPGA_RTC_LR 0x0c 247 #define IFPGA_RTC_CR 0x10 248 249 #define IFPGA_RTC_STAT_INT 1 250 251 #define IFPGA_RTC_CR_MIE 1 /* Match interrupt enable */ 252 253