1 /* $NetBSD: plcom_ifpga.c,v 1.6 2002/10/02 05:10:33 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* Interface to plcom (PL010) serial driver. */ 33 34 #include <sys/types.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 #include <sys/param.h> 38 #include <sys/malloc.h> 39 40 #include <sys/termios.h> 41 42 #include <machine/intr.h> 43 #include <evbarm/ifpga/irqhandler.h> /* XXX XXX XXX */ 44 #include <machine/bus.h> 45 46 #include <evbarm/dev/plcomreg.h> 47 #include <evbarm/dev/plcomvar.h> 48 49 #include <evbarm/ifpga/plcom_ifpgavar.h> 50 51 #include <evbarm/ifpga/ifpgareg.h> 52 #include <evbarm/ifpga/ifpgavar.h> 53 54 static int plcom_ifpga_match(struct device *, struct cfdata *, void *); 55 static void plcom_ifpga_attach(struct device *, struct device *, void *); 56 static void plcom_ifpga_set_mcr(void *, int, u_int); 57 58 CFATTACH_DECL(plcom_ifpga, sizeof(struct plcom_softc), 59 plcom_ifpga_match, plcom_ifpga_attach, NULL, NULL); 60 61 static int 62 plcom_ifpga_match(struct device *parent, struct cfdata *cf, void *aux) 63 { 64 return 1; 65 } 66 67 static void 68 plcom_ifpga_attach(struct device *parent, struct device *self, void *aux) 69 { 70 struct plcom_ifpga_softc *isc = (struct plcom_ifpga_softc *)self; 71 struct plcom_softc *sc = &isc->sc_plcom; 72 struct ifpga_attach_args *ifa = aux; 73 char *irqname; 74 75 isc->sc_iot = ifa->ifa_iot; 76 isc->sc_ioh = ifa->ifa_sc_ioh; 77 sc->sc_iounit = sc->sc_dev.dv_unit; 78 sc->sc_frequency = IFPGA_UART_CLK; 79 sc->sc_iot = ifa->ifa_iot; 80 sc->sc_hwflags = 0; 81 sc->sc_swflags = 0; 82 sc->sc_set_mcr = plcom_ifpga_set_mcr; 83 sc->sc_set_mcr_arg = (void *)isc; 84 85 if (bus_space_map(ifa->ifa_iot, ifa->ifa_addr, PLCOM_UART_SIZE, 0, 86 &sc->sc_ioh)) { 87 printf("%s: unable to map device\n", sc->sc_dev.dv_xname); 88 return; 89 } 90 91 plcom_attach_subr(sc); 92 irqname = malloc(sizeof("uart") + 2, M_DEVBUF, M_WAITOK); 93 sprintf(irqname, "uart%d", sc->sc_dev.dv_unit); 94 isc->sc_ih = intr_claim(ifa->ifa_irq, IPL_SERIAL, irqname, plcomintr, 95 sc); 96 if (isc->sc_ih == NULL) 97 panic("%s: cannot install interrupt handler", 98 sc->sc_dev.dv_xname); 99 } 100 101 static void plcom_ifpga_set_mcr(void *aux, int unit, u_int mcr) 102 { 103 struct plcom_ifpga_softc *isc = (struct plcom_ifpga_softc *)aux; 104 u_int set, clr; 105 106 set = clr = 0; 107 108 switch (unit) { 109 case 0: 110 if (mcr & MCR_RTS) 111 set |= IFPGA_SC_CTRL_UART0RTS; 112 else 113 clr |= IFPGA_SC_CTRL_UART0RTS; 114 if (mcr & MCR_DTR) 115 set |= IFPGA_SC_CTRL_UART0DTR; 116 else 117 clr |= IFPGA_SC_CTRL_UART0DTR; 118 case 1: 119 if (mcr & MCR_RTS) 120 set |= IFPGA_SC_CTRL_UART1RTS; 121 else 122 clr |= IFPGA_SC_CTRL_UART1RTS; 123 if (mcr & MCR_DTR) 124 set |= IFPGA_SC_CTRL_UART1DTR; 125 else 126 clr |= IFPGA_SC_CTRL_UART1DTR; 127 default: 128 return; 129 } 130 131 if (set) 132 bus_space_write_1(isc->sc_iot, isc->sc_ioh, IFPGA_SC_CTRLS, 133 set); 134 if (clr) 135 bus_space_write_1(isc->sc_iot, isc->sc_ioh, IFPGA_SC_CTRLC, 136 clr); 137 } 138