1 /* $NetBSD: i80312_mainbus.c,v 1.10 2002/10/03 01:35:28 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * IQ80310 front-end for the i80312 Companion I/O chip. We take care 40 * of setting up the i80312 memory map, PCI interrupt routing, etc., 41 * which are all specific to the board the i80312 is wired up to. 42 */ 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 48 #include <machine/autoconf.h> 49 #include <machine/bus.h> 50 51 #include <evbarm/iq80310/iq80310reg.h> 52 #include <evbarm/iq80310/iq80310var.h> 53 54 #include <arm/xscale/i80312reg.h> 55 #include <arm/xscale/i80312var.h> 56 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcidevs.h> 59 60 int i80312_mainbus_match(struct device *, struct cfdata *, void *); 61 void i80312_mainbus_attach(struct device *, struct device *, void *); 62 63 CFATTACH_DECL(iopxs_mainbus, sizeof(struct i80312_softc), 64 i80312_mainbus_match, i80312_mainbus_attach, NULL, NULL); 65 66 /* There can be only one. */ 67 int i80312_mainbus_found; 68 69 int 70 i80312_mainbus_match(struct device *parent, struct cfdata *cf, void *aux) 71 { 72 #if 0 73 struct mainbus_attach_args *ma = aux; 74 #endif 75 76 if (i80312_mainbus_found) 77 return (0); 78 79 #if 1 80 /* XXX Shoot arch/arm/mainbus in the head. */ 81 return (1); 82 #else 83 if (strcmp(cf->cf_name, ma->ma_name) == 0) 84 return (1); 85 86 return (0); 87 #endif 88 } 89 90 void 91 i80312_mainbus_attach(struct device *parent, struct device *self, void *aux) 92 { 93 struct i80312_softc *sc = (void *) self; 94 paddr_t memstart; 95 psize_t memsize; 96 97 i80312_mainbus_found = 1; 98 99 /* 100 * Fill in the space tag for the i80312's own devices, 101 * and hand-craft the space handle for it (the device 102 * was mapped during early bootstrap). 103 */ 104 i80312_bs_init(&i80312_bs_tag, sc); 105 sc->sc_st = &i80312_bs_tag; 106 sc->sc_sh = IQ80310_80312_VBASE; 107 108 /* 109 * Slice off a subregion for the Memory Controller -- we need it 110 * here in order read the memory size. 111 */ 112 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_MEM_BASE, 113 I80312_MEM_SIZE, &sc->sc_mem_sh)) 114 panic("%s: unable to subregion MEM registers", 115 sc->sc_dev.dv_xname); 116 117 /* 118 * We have mapped the the PCI I/O windows in the early 119 * bootstrap phase. 120 */ 121 sc->sc_piow_vaddr = IQ80310_PIOW_VBASE; 122 sc->sc_siow_vaddr = IQ80310_SIOW_VBASE; 123 124 /* Some boards are always considered "host". */ 125 #if defined(IOP310_TEAMASA_NPWR) 126 sc->sc_is_host = 1; 127 #else /* Default to stock IQ80310 */ 128 sc->sc_is_host = CPLD_READ(IQ80310_BACKPLANE_DET) & 1; 129 130 /* 131 * Set the subsystem vendor/device IDs to "Cyclone" "PCI-700", 132 * which is the board-specific identification. 133 */ 134 bus_space_write_4(sc->sc_st, sc->sc_sh, 135 I80312_ATU_BASE + PCI_SUBSYS_ID_REG, 136 PCI_ID_CODE(PCI_VENDOR_CYCLONE, PCI_PRODUCT_CYCLONE_PCI_700)); 137 #endif 138 139 printf(": i80312 Companion I/O, acting as PCI %s\n", 140 sc->sc_is_host ? "host" : "slave"); 141 142 i80312_sdram_bounds(sc->sc_st, sc->sc_mem_sh, &memstart, &memsize); 143 144 /* 145 * Set the Primary Inbound window xlate base to the start 146 * of RAM. Set the size to 4K, for now. Just for testing 147 * in a host. This obviously has to be customized for each 148 * IQ310 application. 149 * 150 * Note the first 4K of the window is reserved for the 151 * messaging unit, so no RAM is going to be accessed here. 152 * 153 * ..unless we're a host -- in which case, make it work like 154 * the Secondary Inbound window (below). 155 */ 156 if (sc->sc_is_host) { 157 sc->sc_pin_base = memstart; 158 sc->sc_pin_xlate = memstart; 159 sc->sc_pin_size = memsize; 160 } else { 161 sc->sc_pin_xlate = memstart; 162 sc->sc_pin_size = 4096; 163 } 164 165 /* 166 * Map the Secondary Inbound window 1:1 with local RAM. 167 */ 168 sc->sc_sin_base = memstart; 169 sc->sc_sin_xlate = memstart; 170 sc->sc_sin_size = memsize; 171 172 /* 173 * XXX Don't use the Primary Outbound windows, for now. 174 */ 175 sc->sc_pmemout_size = 0; 176 sc->sc_pioout_size = 0; 177 178 /* 179 * Set the Secondary Outbound Memory window to map 1:1 180 * PCI:Local. 181 */ 182 sc->sc_smemout_base = I80312_PCI_XLATE_SMW_BASE; 183 sc->sc_smemout_size = I80312_PCI_XLATE_MSIZE; 184 185 /* 186 * Set the Secondary Outbound I/O window to map 187 * to PCI address 0 for all 64K of the I/O space. 188 */ 189 sc->sc_sioout_base = 0; 190 sc->sc_sioout_size = I80312_PCI_XLATE_IOSIZE; 191 192 /* 193 * XXX For now, suppress all secondary IDSELs (thus making all 194 * devices from S_AD[11]..S_AD[25] private). 195 */ 196 sc->sc_sisr = 0x3ff; 197 198 /* 199 * XXX For now, make the entire Secondary Outbound address 200 * spaces private. 201 */ 202 sc->sc_privio_base = sc->sc_sioout_base; 203 sc->sc_privio_size = sc->sc_sioout_size; 204 sc->sc_privmem_base = sc->sc_smemout_base; 205 sc->sc_privmem_size = sc->sc_smemout_size; 206 207 /* 208 * Initialize the interrupt part of our PCI chipset tag. 209 */ 210 iq80310_pci_init(&sc->sc_pci_chipset, sc); 211 212 i80312_attach(sc); 213 } 214