1 /* $NetBSD: iq80310_intr.h,v 1.8 2009/02/14 12:44:20 he Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _IQ80310_INTR_H_ 39 #define _IQ80310_INTR_H_ 40 41 #include "opt_iop310.h" 42 43 #include <arm/cpu.h> 44 #include <arm/armreg.h> 45 #include <arm/cpufunc.h> 46 47 #include <arm/xscale/i80200reg.h> 48 #include <arm/xscale/i80200var.h> 49 50 #if defined(IOP310_TEAMASA_NPWR) 51 /* 52 * We have 5 interrupt source bits -- all in XINT3. All interrupts 53 * can be masked in the CPLD. 54 */ 55 #define IRQ_BITS 0x1f 56 #define IRQ_BITS_ALWAYS_ON 0x00 57 #else /* Default to stock IQ80310 */ 58 /* 59 * We have 8 interrupt source bits -- 5 in the XINT3 register, and 3 60 * in the XINT0 register (the upper 3). Note that the XINT0 IRQs 61 * (SPCI INTA, INTB, and INTC) are always enabled, since they can not 62 * be masked out in the CPLD (it provides only status, not masking, 63 * for those interrupts). 64 */ 65 #define IRQ_BITS 0xff 66 #define IRQ_BITS_ALWAYS_ON 0xe0 67 #define IRQ_READ_XINT0 1 /* XXX only if board rev >= F */ 68 #endif /* list of IQ80310-based designs */ 69 70 #ifdef __HAVE_FAST_SOFTINTS 71 void iq80310_do_soft(void); 72 #endif 73 74 static inline int __attribute__((__unused__)) 75 iq80310_splraise(int ipl) 76 { 77 extern int iq80310_imask[]; 78 int old; 79 80 old = curcpl(); 81 set_curcpl(old | iq80310_imask[ipl]); 82 83 /* Don't let the compiler re-order this code with subsequent code */ 84 __insn_barrier(); 85 86 return (old); 87 } 88 89 static inline void __attribute__((__unused__)) 90 iq80310_splx(int new) 91 { 92 extern volatile int iq80310_ipending; 93 int old; 94 95 /* Don't let the compiler re-order this code with preceding code */ 96 __insn_barrier(); 97 98 old = curcpl(); 99 set_curcpl(new); 100 101 #ifdef __HAVE_FAST_SOFTINTS 102 /* If there are software interrupts to process, do it. */ 103 if ((iq80310_ipending & ~IRQ_BITS) & ~new) 104 iq80310_do_soft(); 105 #endif 106 107 /* 108 * If there are pending hardware interrupts (i.e. the 109 * external interrupt is disabled in the ICU), and all 110 * hardware interrupts are being unblocked, then re-enable 111 * the external hardware interrupt. 112 * 113 * XXX We have to wait for ALL hardware interrupts to 114 * XXX be unblocked, because we currently lose if we 115 * XXX get nested interrupts, and I don't know why yet. 116 */ 117 if ((new & IRQ_BITS) == 0 && (iq80310_ipending & IRQ_BITS)) 118 i80200_intr_enable(INTCTL_IM | INTCTL_PM); 119 } 120 121 static inline int __attribute__((__unused__)) 122 iq80310_spllower(int ipl) 123 { 124 extern int iq80310_imask[]; 125 const int old = curcpl(); 126 127 iq80310_splx(iq80310_imask[ipl]); 128 return (old); 129 } 130 131 #if !defined(EVBARM_SPL_NOINLINE) 132 133 #define _splraise(ipl) iq80310_splraise(ipl) 134 #define _spllower(ipl) iq80310_spllower(ipl) 135 #define splx(spl) iq80310_splx(spl) 136 #ifdef __HAVE_FAST_SOFTINTS 137 void _setsoftintr(int); 138 #endif 139 140 #else 141 142 int _splraise(int); 143 int _spllower(int); 144 void splx(int); 145 #ifdef __HAVE_FAST_SOFTINTS 146 void _setsoftintr(int); 147 #endif 148 149 #endif /* ! EVBARM_SPL_NOINLINE */ 150 151 #endif /* _IQ80310_INTR_H_ */ 152