1 /* $NetBSD: iq80310_pci.c,v 1.7 2002/02/08 03:28:24 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * IQ80310 PCI interrupt support, using he i80312 Companion I/O chip. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <machine/autoconf.h> 47 #include <machine/bus.h> 48 49 #include <evbarm/iq80310/iq80310reg.h> 50 #include <evbarm/iq80310/iq80310var.h> 51 52 #include <arm/xscale/i80312reg.h> 53 #include <arm/xscale/i80312var.h> 54 55 #include <dev/pci/pcidevs.h> 56 #include <dev/pci/ppbreg.h> 57 58 int iq80310_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 59 const char *iq80310_pci_intr_string(void *, pci_intr_handle_t); 60 const struct evcnt *iq80310_pci_intr_evcnt(void *, pci_intr_handle_t); 61 void *iq80310_pci_intr_establish(void *, pci_intr_handle_t, 62 int, int (*func)(void *), void *); 63 void iq80310_pci_intr_disestablish(void *, void *); 64 65 void 66 iq80310_pci_init(pci_chipset_tag_t pc, void *cookie) 67 { 68 69 pc->pc_intr_v = cookie; /* the i80312 softc */ 70 pc->pc_intr_map = iq80310_pci_intr_map; 71 pc->pc_intr_string = iq80310_pci_intr_string; 72 pc->pc_intr_evcnt = iq80310_pci_intr_evcnt; 73 pc->pc_intr_establish = iq80310_pci_intr_establish; 74 pc->pc_intr_disestablish = iq80310_pci_intr_disestablish; 75 } 76 77 #if defined(IOP310_TEAMASA_NPWR) 78 int 79 iq80310_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 80 { 81 struct i80312_softc *sc = pa->pa_pc->pc_intr_v; 82 pcireg_t reg; 83 int sbus; 84 85 /* 86 * The Npwr routes #INTA of the on-board PCI devices directly 87 * through the CPLD. There is no PCI-PCI bridge and no PCI 88 * slots on the Npwr. 89 * 90 * We also expect the devices to be on the Secondary side of 91 * the i80312. 92 */ 93 94 reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO); 95 sbus = PPB_BUSINFO_SECONDARY(reg); 96 97 if (pa->pa_bus != sbus) { 98 printf("iq80310_pci_intr_map: %d/%d/%d not on Secondary bus\n", 99 pa->pa_bus, pa->pa_device, pa->pa_function); 100 return (1); 101 } 102 103 switch (pa->pa_device) { 104 case 5: /* LSI 53c1010 SCSI */ 105 *ihp = XINT3_IRQ(2); 106 break; 107 case 6: /* Intel i82544GC Gig-E #1 */ 108 *ihp = XINT3_IRQ(1); 109 break; 110 case 7: /* Intel i82544GC Gig-E #2 */ 111 *ihp = XINT3_IRQ(4); 112 break; 113 default: 114 printf("iq80310_pci_intr_map: no mapping for %d/%d/%d\n", 115 pa->pa_bus, pa->pa_device, pa->pa_function); 116 return (1); 117 } 118 119 return (0); 120 } 121 #else /* Default to stock IQ80310 */ 122 int 123 iq80310_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 124 { 125 struct i80312_softc *sc = pa->pa_pc->pc_intr_v; 126 pcitag_t tag; 127 pcireg_t reg; 128 int sbus, pbus; 129 130 /* 131 * Mapping of PCI interrupts on the IQ80310 is pretty easy; there 132 * is a single interrupt line for all PCI devices on pre-F boards, 133 * and an interrupt line for each INTx# signal on F and later boards. 134 * 135 * The only exception is the on-board Ethernet; this devices has 136 * its own dedicated interrupt line. The location of this device 137 * looks like this: 138 * 139 * 80312 Secondary -> PPB at dev #7 -> i82559 at dev #0 140 * 141 * In order to determine if we're mapping the interrupt for the 142 * on-board Ethernet, we must read the Secondary Bus # of the 143 * i80312, then use that to read the Secondary Bus # of the 144 * 21154 PPB. At that point, we know that b/d/f of the i82559, 145 * and can determine if we're looking at that device. 146 */ 147 148 reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO); 149 pbus = PPB_BUSINFO_PRIMARY(reg); 150 sbus = PPB_BUSINFO_SECONDARY(reg); 151 152 /* 153 * XXX We don't know how to map interrupts on the Primary 154 * XXX PCI bus right now. 155 */ 156 if (pa->pa_bus == pbus) { 157 printf("iq80310_pci_intr_map: can't map interrupts on " 158 "Primary bus\n"); 159 return (1); 160 } 161 162 tag = pci_make_tag(pa->pa_pc, sbus, 7, 0); 163 164 /* Make sure the PPB is there. */ 165 reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG); 166 if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID || 167 PCI_VENDOR(reg) == 0) { 168 /* 169 * That's odd... no PPB there? Oh well, issue a warning 170 * and continue on. 171 */ 172 printf("iq80310_pci_intr_map: PPB not found at %d/%d/%d ??\n", 173 sbus, 7, 0); 174 goto pinmap; 175 } 176 177 /* Make sure the device that's there is a PPB. */ 178 reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG); 179 if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE || 180 PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI) { 181 /* 182 * That's odd... the device that's there isn't a PPB. 183 * Oh well, issue a warning and continue on. 184 */ 185 printf("iq80310_pci_intr_map: %d/%d/%d isn't a PPB ??\n", 186 sbus, 7, 0); 187 goto pinmap; 188 } 189 190 /* Now read the PPB's secondary bus number. */ 191 reg = pci_conf_read(pa->pa_pc, tag, PPB_REG_BUSINFO); 192 sbus = PPB_BUSINFO_SECONDARY(reg); 193 194 if (pa->pa_bus == sbus && pa->pa_device == 0 && 195 pa->pa_function == 0) { 196 /* On-board i82559 Ethernet! */ 197 *ihp = XINT3_IRQ(XINT3_ETHERNET); 198 return (0); 199 } 200 201 pinmap: 202 if (pa->pa_intrpin == 0) { 203 /* No IRQ used. */ 204 return (1); 205 } 206 if (pa->pa_intrpin > 4) { 207 printf("iq80310_pci_intr_map: bad interrupt pin %d\n", 208 pa->pa_intrpin); 209 return (1); 210 } 211 212 /* INTD# is always in XINT3. */ 213 if (pa->pa_intrpin == 4) { 214 *ihp = XINT3_IRQ(XINT3_SINTD); 215 return (0); 216 } 217 218 /* On pre-F boards, ALL of them are on XINT3. */ 219 if (/*pre-F*/0) 220 *ihp = XINT3_IRQ(XINT3_SINTD); 221 else 222 *ihp = XINT0_IRQ(pa->pa_intrpin - 1); 223 224 return (0); 225 } 226 #endif /* list of IQ80310-based designs */ 227 228 const char * 229 iq80310_pci_intr_string(void *v, pci_intr_handle_t ih) 230 { 231 static char irqstr[IRQNAMESIZE]; 232 233 sprintf(irqstr, "iq80310 irq %ld", ih); 234 return (irqstr); 235 } 236 237 const struct evcnt * 238 iq80310_pci_intr_evcnt(void *v, pci_intr_handle_t ih) 239 { 240 241 /* XXX For now. */ 242 return (NULL); 243 } 244 245 void * 246 iq80310_pci_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 247 int (*func)(void *), void *arg) 248 { 249 250 return (iq80310_intr_establish(ih, ipl, func, arg)); 251 } 252 253 void 254 iq80310_pci_intr_disestablish(void *v, void *cookie) 255 { 256 257 iq80310_intr_disestablish(cookie); 258 } 259