1 /* $NetBSD: i80321_mainbus.c,v 1.1 2002/03/27 21:51:29 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * IQ80321 front-end for the i80321 I/O Processor. We take care 40 * of setting up the i80321 memory map, PCI interrupt routing, etc., 41 * which are all specific to the board the i80321 is wired up to. 42 */ 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 48 #include <machine/autoconf.h> 49 #include <machine/bus.h> 50 51 #include <evbarm/iq80321/iq80321reg.h> 52 #include <evbarm/iq80321/iq80321var.h> 53 54 #include <arm/xscale/i80321reg.h> 55 #include <arm/xscale/i80321var.h> 56 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcidevs.h> 59 60 int i80321_mainbus_match(struct device *, struct cfdata *, void *); 61 void i80321_mainbus_attach(struct device *, struct device *, void *); 62 63 struct cfattach iopxs_mainbus_ca = { 64 sizeof(struct i80321_softc), i80321_mainbus_match, 65 i80321_mainbus_attach, 66 }; 67 68 /* There can be only one. */ 69 int i80321_mainbus_found; 70 71 int 72 i80321_mainbus_match(struct device *parent, struct cfdata *cf, void *aux) 73 { 74 #if 0 75 struct mainbus_attach_args *ma = aux; 76 #endif 77 78 if (i80321_mainbus_found) 79 return (0); 80 81 #if 1 82 /* XXX Shoot arch/arm/mainbus in the head. */ 83 return (1); 84 #else 85 if (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0) 86 return (1); 87 88 return (0); 89 #endif 90 } 91 92 void 93 i80321_mainbus_attach(struct device *parent, struct device *self, void *aux) 94 { 95 struct i80321_softc *sc = (void *) self; 96 paddr_t memstart; 97 psize_t memsize; 98 99 i80321_mainbus_found = 1; 100 101 /* 102 * Fill in the space tag for the i80321's own devices, 103 * and hand-craft the space handle for it (the device 104 * was mapped during early bootstrap). 105 */ 106 i80321_bs_init(&i80321_bs_tag, sc); 107 sc->sc_st = &i80321_bs_tag; 108 sc->sc_sh = IQ80321_80321_VBASE; 109 110 /* 111 * Slice off a subregion for the Memory Controller -- we need it 112 * here in order read the memory size. 113 */ 114 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_MCU_BASE, 115 VERDE_MCU_SIZE, &sc->sc_mcu_sh)) 116 panic("%s: unable to subregion MCU registers\n", 117 sc->sc_dev.dv_xname); 118 119 /* 120 * We have mapped the the PCI I/O windows in the early 121 * bootstrap phase. 122 */ 123 sc->sc_iow_vaddr = IQ80321_IOW_VBASE; 124 125 /* Some boards are always considered "host". */ 126 sc->sc_is_host = 1; /* XXX */ 127 128 printf(": i80321 I/O Processor, acting as PCI %s\n", 129 sc->sc_is_host ? "host" : "slave"); 130 131 i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize); 132 133 /* 134 * We set up the Inbound Windows as follows: 135 * 136 * 0 Access to i80321 PMMRs 137 * 138 * 1 Reserve space for private devices 139 * 140 * 2 RAM access 141 * 142 * 3 Unused. 143 * 144 * This chunk needs to be customized for each IOP321 application. 145 */ 146 #if 0 147 sc->sc_iwin[0].iwin_base_lo = VERDE_PMMR_BASE; 148 sc->sc_iwin[0].iwin_base_hi = 0; 149 sc->sc_iwin[0].iwin_xlate = VERDE_PMMR_BASE; 150 sc->sc_iwin[0].iwin_size = VERDE_PMMR_SIZE; 151 #endif 152 153 if (sc->sc_is_host) { 154 /* Map PCI:Local 1:1. */ 155 sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE | 156 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 157 PCI_MAPREG_MEM_TYPE_64BIT; 158 sc->sc_iwin[1].iwin_base_hi = 0; 159 sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE; 160 sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE; 161 } else { 162 panic("i80321: iwin[1] slave"); 163 } 164 165 if (sc->sc_is_host) { 166 sc->sc_iwin[2].iwin_base_lo = memstart | 167 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 168 PCI_MAPREG_MEM_TYPE_64BIT; 169 sc->sc_iwin[2].iwin_base_hi = 0; 170 sc->sc_iwin[2].iwin_xlate = memstart; 171 sc->sc_iwin[2].iwin_size = memsize; 172 } else { 173 panic("i80321: iwin[2] slave"); 174 } 175 176 /* 177 * We set up the Outbound Windows as follows: 178 * 179 * 0 Access to private PCI space. 180 * 181 * 1 Unused. 182 */ 183 sc->sc_owin[0].owin_xlate_lo = 184 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo); 185 sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi; 186 187 /* 188 * Set the Secondary Outbound I/O window to map 189 * to PCI address 0 for all 64K of the I/O space. 190 */ 191 sc->sc_ioout_xlate = 0; 192 193 /* 194 * Initialize the interrupt part of our PCI chipset tag. 195 */ 196 iq80321_pci_init(&sc->sc_pci_chipset, sc); 197 198 i80321_attach(sc); 199 } 200