1/* $NetBSD: iq80321_start.S,v 1.3 2002/04/26 18:01:21 thorpej Exp $ */ 2 3/* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#include <machine/asm.h> 39#include <arm/armreg.h> 40#include <arm/arm32/pte.h> 41 42 .section .start,"ax",%progbits 43 44 .global _C_LABEL(iq80321_start) 45_C_LABEL(iq80321_start): 46 /* 47 * We will go ahead and disable the MMU here so that we don't 48 * have to worry about flushing caches, etc. 49 * 50 * Note that we may not currently be running VA==PA, which means 51 * we'll need to leap to the next insn after disabing the MMU. 52 */ 53 add r8, pc, #(Lunmapped - . - 8) 54 bic r8, r8, #0xff000000 /* clear upper 8 bits */ 55 orr r8, r8, #0xa0000000 /* OR in physical base address */ 56 57 mrc p15, 0, r2, c1, c0, 0 58 bic r2, r2, #CPU_CONTROL_MMU_ENABLE 59 mcr p15, 0, r2, c1, c0, 0 60 61 nop 62 nop 63 nop 64 65 mov pc, r8 /* Heave-ho! */ 66 67Lunmapped: 68 /* 69 * We want to construct a memory map that maps us 70 * VA==PA (SDRAM at 0xa0000000) and also double-maps 71 * that space at 0xc0000000 (where the kernel address 72 * space starts). We create these mappings uncached 73 * and unbuffered to be safe. 74 * 75 * We also want to map the various devices we want to 76 * talk to VA==PA during bootstrap. 77 * 78 * We just use section mappings for all of this to make it easy. 79 * 80 * We will put the L1 table to do all this at 0xa0004000, which 81 * is also where RedBoot puts it. 82 */ 83 84 /* 85 * Step 1: Map the entire address space VA==PA. 86 */ 87 add r0, pc, #(Ltable - . - 8) 88 ldr r0, [r0] /* r0 = &l1table */ 89 90 mov r3, #(L1_S_AP(AP_KRW)) 91 orr r3, r3, #(L1_TYPE_S) 92 mov r2, #0x100000 /* advance by 1MB */ 93 mov r1, #0x1000 /* 4096MB */ 941: 95 str r3, [r0], #0x04 96 add r3, r3, r2 97 subs r1, r1, #1 98 bgt 1b 99 100 /* 101 * Step 2: Map VA 0xc0000000->0xc3ffffff to PA 0xa0000000->0xa3ffffff. 102 */ 103 add r0, pc, #(Ltable - . - 8) /* r0 = &l1table */ 104 ldr r0, [r0] 105 106 mov r3, #(L1_S_AP(AP_KRW)) 107 orr r3, r3, #(L1_TYPE_S) 108 orr r3, r3, #0xa0000000 109 add r0, r0, #(0xc00 * 4) /* offset to 0xc00xxxxx */ 110 mov r1, #0x40 /* 64MB */ 1111: 112 str r3, [r0], #0x04 113 add r3, r3, r2 114 subs r1, r1, #1 115 bgt 1b 116 117 /* OK! Page table is set up. Give it to the CPU. */ 118 add r0, pc, #(Ltable - . - 8) 119 ldr r0, [r0] 120 mcr p15, 0, r0, c2, c0, 0 121 122 /* Flush the old TLBs, just in case. */ 123 mcr p15, 0, r0, c8, c7, 0 124 125 /* Set the Domain Access register. Very important! */ 126 mov r0, #1 127 mcr p15, 0, r0, c3, c0, 0 128 129 /* Get ready to jump to the "real" kernel entry point... */ 130 add r0, pc, #(Lstart - . - 8) 131 ldr r0, [r0] 132 133 /* OK, let's enable the MMU. */ 134 mrc p15, 0, r2, c1, c0, 0 135 orr r2, r2, #CPU_CONTROL_MMU_ENABLE 136 mcr p15, 0, r2, c1, c0, 0 137 138 nop 139 nop 140 nop 141 142 /* CPWAIT sequence to make sure the MMU is on... */ 143 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */ 144 mov r2, r2 /* force it to complete */ 145 mov pc, r0 /* leap to kernel entry point! */ 146 147Ltable: 148 .word 0xa0004000 149 150Lstart: 151 .word start 152