1 /* $NetBSD: nappi_nppb.c,v 1.4 2002/10/02 05:10:36 thorpej Exp $ */ 2 /* 3 * Copyright (c) 2002 4 * Ichiro FUKUHARA <ichiro@ichiro.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ichiro FUKUHARA. 18 * 4. The name of the company nor the name of the author may be used to 19 * endorse or promote products derived from this software without specific 20 * prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #include "pci.h" 36 #include "opt_pci.h" 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/extent.h> 43 #include <sys/malloc.h> 44 45 #include <machine/bus.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcidevs.h> 50 #include <dev/pci/pciconf.h> 51 52 static int nppbmatch(struct device *, struct cfdata *, void *); 53 static void nppbattach(struct device *, struct device *, void *); 54 55 int nppb_intr(void *); /* XXX into i21555var.h */ 56 57 CFATTACH_DECL(nppb, sizeof(struct device), 58 nppbmatch, nppbattach, NULL, NULL); 59 60 #define NPPB_MMBA 0x10 61 #define NPPB_IOBA 0x14 62 63 #define CSR_READ_1(sc, reg) \ 64 bus_space_read_1(sc->sc_st, sc->sc_sh, reg) 65 #define CSR_READ_2(sc, reg) \ 66 bus_space_read_2(sc->sc_st, sc->sc_sh, reg) 67 #define CSR_READ_4(sc, reg) \ 68 bus_space_read_4(sc->sc_st, sc->sc_sh, reg) 69 70 #define CSR_WRITE_1(sc, reg, val) \ 71 bus_space_write_1(sc->sc_st, sc->sc_sh, reg, val) 72 #define CSR_WRITE_2(sc, reg, val) \ 73 bus_space_write_2(sc->sc_st, sc->sc_sh, reg, val) 74 #define CSR_WRITE_4(sc, reg, val) \ 75 bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val) 76 77 struct nppb_softc { /* XXX into i21555var.h */ 78 struct device sc_dev; /* generic device information */ 79 bus_space_tag_t sc_st; /* bus space tag */ 80 bus_space_handle_t sc_sh; /* bus space handle */ 81 82 void *sc_ih; /* interrupt handler cookie */ 83 }; 84 85 struct nppb_pci_softc { 86 struct nppb_softc psc_nppb; 87 88 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 89 pcitag_t psc_tag; /* pci register tag */ 90 }; 91 92 static int 93 nppbmatch(struct device *parent, struct cfdata *cf, void *aux) 94 { 95 struct pci_attach_args *pa = aux; 96 u_int32_t class, id; 97 98 class = pa->pa_class; 99 id = pa->pa_id; 100 101 if (PCI_CLASS(class) == PCI_CLASS_BRIDGE && 102 PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_MISC) { 103 #ifdef PCI_DEBUG 104 printf("pci vendor = 0x%08x\n", PCI_VENDOR(id)); 105 printf("pci class = 0x%08x\n", PCI_CLASS(class)); 106 printf("pci subclass = 0x%08x\n", PCI_SUBCLASS(class)); 107 #endif 108 switch (PCI_VENDOR(id)) { 109 case PCI_VENDOR_INTEL: 110 switch (PCI_PRODUCT(id)) { 111 case PCI_PRODUCT_INTEL_21555: 112 return(1); 113 } 114 break; 115 } 116 } 117 return(0); 118 } 119 120 static void 121 nppbattach(struct device *parent, struct device *self, void *aux) 122 { 123 struct nppb_pci_softc *psc = (struct nppb_pci_softc *)self; 124 struct nppb_softc *sc = (struct nppb_softc *)self; 125 struct pci_attach_args *pa = aux; 126 pci_chipset_tag_t pc = pa->pa_pc; 127 pci_intr_handle_t ih; 128 const char *intrstr = NULL; 129 char devinfo[256]; 130 131 bus_space_tag_t iot, memt; 132 bus_space_handle_t ioh, memh; 133 int ioh_valid, memh_valid; 134 135 printf("\n"); 136 psc->psc_pc = pc; 137 psc->psc_tag = pa->pa_tag; 138 139 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 140 printf("%s: %s (rev. 0x%02x)\n", self->dv_xname, devinfo, 141 PCI_REVISION(pa->pa_class)); 142 143 /* Make sure bus-mastering is enabled. */ 144 pci_conf_write(psc->psc_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 145 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 146 PCI_COMMAND_MASTER_ENABLE); 147 148 /* Chip Reset */ 149 pci_conf_write(psc->psc_pc, pa->pa_tag, 0xD8, 0x03); 150 151 /* Map control/status registers */ 152 ioh_valid = (pci_mapreg_map(pa, NPPB_IOBA, 153 PCI_MAPREG_TYPE_IO, 0, 154 &iot, &ioh, NULL, NULL) == 0); 155 memh_valid = (pci_mapreg_map(pa, NPPB_MMBA, 156 PCI_MAPREG_TYPE_MEM | 157 PCI_MAPREG_MEM_TYPE_32BIT, 158 0, &memt, &memh, NULL, NULL) == 0); 159 160 if (memh_valid) { 161 sc->sc_st = memt; 162 sc->sc_sh = memh; 163 } else if (ioh_valid) { 164 sc->sc_st = iot; 165 sc->sc_sh = ioh; 166 } else { 167 printf(": unable to map device registers\n"); 168 return; 169 } 170 171 /* Map and establish our interrupt */ 172 if (pci_intr_map(pa, &ih)) { 173 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 174 return; 175 } 176 intrstr = pci_intr_string(pc, ih); 177 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nppb_intr, sc); 178 if (sc->sc_ih == NULL) { 179 printf("%s: couldn't establish interrupt", 180 sc->sc_dev.dv_xname); 181 if (intrstr != NULL) 182 printf(" at %s", intrstr); 183 printf("\n"); 184 return; 185 } 186 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 187 188 } 189 190 /* XXX */ 191 int 192 nppb_intr(void *arg) 193 { 194 #if 0 195 struct nppb_softc *sc = arg; 196 #endif 197 return(0); 198 } 199