1/*	$NetBSD: s3c2800_vector.S,v 1.2 2005/12/11 12:17:09 christos Exp $	*/
2
3/*
4 * Copyright (c) 2002, 2003 Fujitsu Component Limited
5 * Copyright (c) 2002, 2003 Genetec Corporation
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of The Fujitsu Component Limited nor the name of
17 *    Genetec corporation may not be used to endorse or promote products
18 *    derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED.  IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35/*
36 * Vector and initialize for S3C2800 based systems.
37 */
38
39#include <machine/asm.h>
40#include <arm/armreg.h>
41#include <arm/s3c2xx0/s3c2800reg.h>
42
43#ifndef PLLCON_MDIV_VAL
44/* constans to get 200MHz FCLK */
45#if XTAL_CLK == 10000000 || XTAL_CLK == 10
46#define PLLCON_MDIV_VAL	0x5c
47#define PLLCON_PDIV_VAL	3
48#define PLLCON_SDIV_VAL	0
49#elif XTAL_CLK == 8000000 || XTAL_CLK == 8
50#define PLLCON_MDIV_VAL	0x5c
51#define PLLCON_PDIV_VAL	2
52#define PLLCON_SDIV_VAL	0
53#elif XTAL_CLK == 6000000 || XTAL_CLK == 6
54#define PLLCON_MDIV_VAL	0x5c
55#define PLLCON_PDIV_VAL	1
56#define PLLCON_SDIV_VAL	0
57#else
58#error define XTAL_CLK to 10, 8 or 6MHz
59#endif	/* XTAL_CLK */
60#endif	/* PLLCON_MDIV_VAL */
61
62#ifndef SDRAM_START
63#define SDRAM_START	S3C2800_DBANK0_START
64#endif
65#ifndef SDRAM_SIZE
66#define SDRAM_SIZE	0x01000000			    /* 16MB */
67#endif
68
69#define TEMP_STACK_SIZE	(4*1024)
70
71
72	.code 32
73	.section ".vectors"
74
75reset_vector:
76	b	__reset_entry
77undef:
78	b	.
79swi:
80	b	.
81abrtp:
82	b	.
83abrtd:
84	b	.
85resv:
86	b	.
87irq:
88	b	.
89fiq:
90	b	.
91
92/*
93 * Normally this code lives on ROM and runs immediately after reset, but
94 * it may run on RAM and/or be called after system has been initialized.
95 */
96__reset_entry:
97	mrs	r0, cpsr
98	/* SVC mode, Disable interrupts */
99	bic	r0, r0, #PSR_MODE
100	orr	r0, r0, #(I32_bit|F32_bit|PSR_SVC32_MODE)
101	msr	cpsr, r0
102
103	/* Disable MMU, Disable cache */
104	mrc	p15, 0, r10, c1, c0, 0
105	ldr	r0, =(CPU_CONTROL_MMU_ENABLE|CPU_CONTROL_DC_ENABLE|CPU_CONTROL_IC_ENABLE)
106	bic	r10, r10, r0
107	mcr	p15, 0, r10, c1, c0, 0
108	nop
109	nop
110	nop
111
112	/* invalidate I-cache */
113	mcr	p15, 0, r2, c7, c5, 0
114	nop
115	nop
116	nop
117
118	/* Enable I-cache */
119	orr	r10, r10, #CPU_CONTROL_IC_ENABLE
120	mcr	p15, 0, r10, c1, c0, 0
121	nop
122	nop
123	nop
124
125	/* Stop WDT */
126	ldr	r0, Lwdt_wtcon_addr
127	mov	r1, #WTCON_WDTSTOP
128	str	r1, [r0]
129
130	/* Disable all interrupts */
131	ldr	r0, Lintctl_intmsk_addr
132	mov	r1, #0x0
133	str	r1, [r0]
134
135#if 0
136	ldr	r9, =S3C2800_GPIO_BASE
137	/* LEDs on SMDK2800 */
138	mov	r1, #0x3f
139	strh	r1, [r9, #GPIO_PCONC]
140
141	mov	r0, #0xdfff	    /* set PB7 to AHBCLK out */
142	strh	r0, [r9,GPIO_PCONB]
143#endif
144
145	mov	r0, pc
146	cmp	r0, #SDRAM_START
147	bhs	running_on_ram
148
149#ifdef RAM_INIT_HOOK
150	bl	RAM_INIT_HOOK
151#endif
152	ldr	r8, =S3C2800_CLKMAN_BASE
153	ldr	r1, [r8,#CLKMAN_CLKCON]
154	orr	r1, r1, #CLKCON_HCLK  /* AHB clock = FCLK/2 */
155	str	r1, [r8,#CLKMAN_CLKCON]
156
157	ldr	r1, Lclkman_locktime_data
158	str	r1, [r8,#CLKMAN_LOCKTIME]
159
160	/* Initialize PLL */
161	ldr	r1, Lclkman_pllcon_data
162	str	r1, [r8,#CLKMAN_PLLCON]
163
164running_on_ram:
165	/* Change Bus mode to Sync */
166	mrc	p15, 0, r0, c1, c0, 0
167	bic	r0, r0, #(1<<31)		/* unset iA bit */
168	orr	r0, r0, #(1<<30)		/* set nF bit */
169	mcr	p15, 0, r0, c1, c0, 0
170	nop
171	nop
172	nop
173
174	/* set temporary stack */
175	adr	sp, reset_vector
176	/* do we have a room below? */
177	ldr	r1, =(SDRAM_START+TEMP_STACK_SIZE)
178	cmp	sp, r1
179	/* otherwise use top area of RAM */
180	ldrlo	sp, =(SDRAM_START+SDRAM_SIZE)
181
182#ifdef IO_INIT_HOOK
183	bl	IO_INIT_HOOK
184#endif
185#ifdef SELFCOPY_TO_FLASH
186	/* Are we running on RAM? */
187	mov	r0, pc
188	cmp	r0, #SDRAM_START
189	blo	99f      /* no, skip */
190	adr	r0, reset_vector
191	ldr	r1, =__rom_size__
192	b	selfcopy_to_flash
19399:
194#endif
195	b	start
196
197Lwdt_wtcon_addr:
198	.word	(S3C2800_WDT_BASE + WDT_WTCON)
199
200Lintctl_intmsk_addr:
201	.word	(S3C2800_INTCTL_BASE + INTCTL_INTMSK)
202
203	.ltorg
204
205Lclkman_locktime_data:
206	.word	(0xfff)
207
208Lclkman_pllcon_data:
209	.word	(PLLCON_MDIV_VAL<<PLLCON_MDIV_SHIFT) | \
210		(PLLCON_PDIV_VAL<<PLLCON_PDIV_SHIFT) | \
211		(PLLCON_SDIV_VAL<<PLLCON_SDIV_SHIFT)
212
213