1/* $NetBSD: smdk2410_ram_init.S,v 1.2 2005/12/11 12:17:09 christos Exp $ */ 2 3/* 4 * Copyright (c) 2003 By Noon Software, Inc. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The names of the authors may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <machine/asm.h> 30#include <arm/armreg.h> 31#include <arm/s3c2xx0/s3c2410reg.h> 32 33ENTRY(smdk2410_ram_init) 34 /* Initialize memory controller */ 35 adr r0, Lmemctl_initial_data 36 ldr r1, [r0], #4 37 adr r2, Lmemctl_initial_data_end 381: 39 ldr r3, [r0], #4 40 str r3, [r1], #4 41 cmp r0, r2 42 blo 1b 43 44 mov pc,lr 45 46#define BANKCON_VAL_ROM(tacs,tcoc,toch,tacc,tcah,tacp) \ 47 (BANKCON_MT_ROM | \ 48 ((tacs)<<BANKCON_TACS_SHIFT) | ((tcoc)<<BANKCON_TCOS_SHIFT) | \ 49 ((toch)<<BANKCON_TOCH_SHIFT) | ((tacc)<<BANKCON_TACC_SHIFT) | \ 50 ((tcah)<<BANKCON_TCAH_SHIFT) | ((tacp)<<BANKCON_TACP_SHIFT)) 51 52#define BANKCON_VAL_DRAM(trcd,scan) \ 53 (BANKCON_MT_DRAM | ((trcd)<<BANKCON_TRCD_SHIFT) | scan) 54 55Lmemctl_initial_data: 56 .word S3C2410_MEMCTL_BASE + MEMCTL_BWSCON /* address */ 57 .word (BWSCON_DW_32<<28)|(BWSCON_DW_32<<24)|(BWSCON_DW_16<<20)| \ 58 (BWSCON_DW_16<<16)|((BWSCON_DW_16|BWSCON_WS|BWSCON_ST)<<12)| \ 59 ((BWSCON_DW_16|BWSCON_WS|BWSCON_ST)<< 8)|(BWSCON_DW_32<< 4) 60 .word BANKCON_VAL_ROM(0,0,0,7,0,0) /* BANKCON0 */ 61 .word BANKCON_VAL_ROM(0,0,0,7,0,0) /* BANKCON1 */ 62 .word BANKCON_VAL_ROM(0,0,0,7,0,0) /* BANKCON2 */ 63 .word BANKCON_VAL_ROM(0,0,0,7,0,0) /* BANKCON3 */ 64 .word BANKCON_VAL_ROM(0,0,0,7,0,0) /* BANKCON4 */ 65 .word BANKCON_VAL_ROM(0,0,0,7,0,0) /* BANKCON5 */ 66 .word BANKCON_VAL_DRAM(1,1) /* BANKCON6 */ 67 .word BANKCON_VAL_DRAM(1,1) /* BANKCON7 */ 68 .word (1<<23)|(0<<22)|(0<<20)|(3<<18)|(2<<16)|(1113) 69 .word 0x32 /* SCLK power saving mode, BANKSIZE 128M/128M */ 70 .word 0x30 /* MRSR6 CL=3clk */ 71 .word 0x30 /* MRSR7 CL=3clk */ 72Lmemctl_initial_data_end: 73