1/* $NetBSD: smdk2800_ram_init.S,v 1.2 2005/12/11 12:17:09 christos Exp $ */ 2 3/* 4 * Copyright (c) 2002, 2003 Fujitsu Component Limited 5 * Copyright (c) 2002, 2003 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35#include <machine/asm.h> 36#include <arm/armreg.h> 37#include <arm/s3c2xx0/s3c2800reg.h> 38 39ENTRY(smdk2800_ram_init) 40 /* Initialize memory controller */ 41 adr r0, Lmemctl_initial_data 42 ldr r1, [r0], #4 43 adr r2, Lmemctl_initial_data_end 441: 45 ldr r3, [r0], #4 46 str r3, [r1], #4 47 cmp r0, r2 48 blo 1b 49 50 mov pc,lr 51 52#define REFRESH_INIT (REFRESH_REFEN | \ 53 (0x0<<20) | \ 54 (0x3<<16) | \ 55 (0x0<<12) | \ 56 (0x1e9)) 57#define DMTMCON_INIT ((0x2<<16) | \ 58 (0x3<<10) | \ 59 (0x1<<8) | \ 60 (0x1<<6) | \ 61 (0x1<<4) | \ 62 (0x1<<2) | \ 63 (0x1)) 64 65#define SMBCON_VAL(ws,st,tacs,tcoc,toch,tacc,tcah,sdw) \ 66 ((ws) | (st) | \ 67 ((tacs)<<SMBCON_TACS_SHIFT) | ((tcoc)<<SMBCON_TCOS_SHIFT) | \ 68 ((toch)<<SMBCON_TOCH_SHIFT) | ((tacc)<<SMBCON_TACC_SHIFT) | \ 69 ((tcah)<<SMBCON_TCAH_SHIFT) | (sdw)) 70 71Lmemctl_initial_data: 72 .word S3C2800_MEMCTL_BASE + MEMCTL_SMBCON0 /* address */ 73 .word SMBCON_VAL(0,0,0,0,0,0x0a,0,SMBCON_SDW_32BIT) /* SMBCON0 */ 74 .word SMBCON_VAL(0,0,0,0,0,0x0a,0,SMBCON_SDW_16BIT) /* SMBCON1 */ 75 .word SMBCON_VAL(0,0,0,0,0,0x0a,0,SMBCON_SDW_32BIT) /* SMBCON2 */ 76 .word SMBCON_VAL(0,0,0,0,0,0x0a,0,SMBCON_SDW_32BIT) /* SMBCON3 */ 77 .word REFRESH_INIT 78 .word DMTMCON_INIT 79 .word 0x3<<MRSR_CL_SHIFT /* MRSR */ 80Lmemctl_initial_data_end: 81