1 /* $NetBSD: interrupt.c,v 1.14 2010/12/20 00:25:31 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.14 2010/12/20 00:25:31 matt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/cpu.h> 38 #include <sys/intr.h> 39 40 #include <mips/mips3_clock.h> 41 #include <machine/locore.h> 42 43 void 44 intr_init(void) 45 { 46 47 evbmips_intr_init(); /* board specific stuff */ 48 } 49 50 void 51 cpu_intr(uint32_t status, uint32_t cause, vaddr_t pc, uint32_t ipending) 52 { 53 struct clockframe cf; 54 struct cpu_info *ci; 55 56 ci = curcpu(); 57 ci->ci_idepth++; 58 ci->ci_data.cpu_nintr++; 59 60 if (ipending & MIPS_INT_MASK_5) { 61 /* call the common MIPS3 clock interrupt handler */ 62 cf.pc = pc; 63 cf.sr = status; 64 mips3_clockintr(&cf); 65 66 /* Re-enable clock interrupts. */ 67 cause &= ~MIPS_INT_MASK_5; 68 _splset(MIPS_SR_INT_IE | 69 ((status & ~cause) & MIPS_HARD_INT_MASK)); 70 } 71 72 if (ipending & (MIPS_INT_MASK_0|MIPS_INT_MASK_1|MIPS_INT_MASK_2| 73 MIPS_INT_MASK_3|MIPS_INT_MASK_4)) { 74 /* Process I/O and error interrupts. */ 75 evbmips_iointr(status, cause, pc, ipending); 76 } 77 ci->ci_idepth--; 78 79 #ifdef __HAVE_FAST_SOFTINTS 80 ipending &= (MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0); 81 if (ipending == 0) 82 return; 83 _clrsoftintr(ipending); 84 softintr_dispatch(ipending); 85 #endif 86 } 87