1 /* $NetBSD: ap_ms104_sh4reg.h,v 1.1 2010/04/06 15:54:29 nonaka Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 NONAKA Kimihiro <nonaka@netbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef AP_MS104_SH4REG_H_ 30 #define AP_MS104_SH4REG_H_ 31 32 #define EXTINTR_MASK1 0xa4000000 /* R/W: 8bit */ 33 #define EXTINTR_MASK2 0xa4100000 /* R/W: 8bit */ 34 #define EXTINTR_MASK3 0xa4200000 /* R/W: 8bit */ 35 #define EXTINTR_MASK4 0xa4300000 /* R/W: 8bit */ 36 #define EXTINTR_STAT1 0xa4400000 /* R: 8bit */ 37 #define EXTINTR_STAT2 0xa4500000 /* R: 8bit */ 38 #define EXTINTR_STAT3 0xa4600000 /* R: 8bit */ 39 #define EXTINTR_STAT4 0xa4700000 /* R: 8bit */ 40 #define CFBUS_CTRL 0xa4800000 /* W: 8bit */ 41 42 /* EXTINTR_MASK1 */ 43 #define MASK1_INT14 (1U << 0) 44 #define MASK1_INT13 (1U << 1) 45 #define MASK1_INT12 (1U << 2) 46 #define MASK1_INT11 (1U << 3) 47 48 /* EXTINTR_MASK2 */ 49 #define MASK2_INT10 (1U << 0) 50 #define MASK2_INT9 (1U << 1) 51 #define MASK2_INT8 (1U << 2) 52 #define MASK2_INT7 (1U << 3) 53 54 /* EXTINTR_MASK3 */ 55 #define MASK3_INT6 (1U << 0) 56 #define MASK3_INT5 (1U << 1) 57 #define MASK3_INT4 (1U << 2) 58 #define MASK3_INT3 (1U << 3) 59 60 /* EXTINTR_MASK4 */ 61 #define MASK4_INT2 (1U << 0) 62 #define MASK4_INT1 (1U << 1) 63 64 /* EXTINTR_STAT1 */ 65 #define STAT1_INT14 (1U << 0) 66 #define STAT1_INT13 (1U << 1) 67 #define STAT1_INT12 (1U << 2) 68 #define STAT1_INT11 (1U << 3) 69 70 /* EXTINTR_STAT2 */ 71 #define STAT2_INT10 (1U << 0) 72 #define STAT2_INT9 (1U << 1) 73 #define STAT2_INT8 (1U << 2) 74 #define STAT2_INT7 (1U << 3) 75 76 /* EXTINTR_STAT3 */ 77 #define STAT3_INT6 (1U << 0) 78 #define STAT3_INT5 (1U << 1) 79 #define STAT3_INT4 (1U << 2) 80 #define STAT3_INT3 (1U << 3) 81 82 /* EXTINTR_STAT4 */ 83 #define STAT4_INT2 (1U << 0) 84 #define STAT4_INT1 (1U << 1) 85 86 /* CFBUS_CTRL */ 87 #define CFBUS_CTRL_WAIT (1U << 0) 88 #define CFBUS_CTRL_IOIS16 (1U << 1) 89 90 /* external intr# */ 91 #define EXTINTR_INTR_SMC91C111 8 92 #define EXTINTR_INTR_CFIREQ 12 93 #define EXTINTR_INTR_RTC 14 94 95 /* GPIO pin# */ 96 #define GPIO_PIN_CARD_CD 8 /* In */ 97 #define GPIO_PIN_CARD_PON 9 /* Out */ 98 #define GPIO_PIN_CARD_RESET 10 /* Out */ 99 #define GPIO_PIN_CARD_ENABLE 11 /* Out */ 100 #define GPIO_PIN_RTC_SIO 13 /* In/Out */ 101 #define GPIO_PIN_RTC_SCLK 14 /* Out */ 102 #define GPIO_PIN_RTC_CE 15 /* Out */ 103 104 #endif /* AP_MS104_SH4REG_H_ */ 105