1 /* $NetBSD: platid_mask.c,v 1.24 2010/04/06 16:18:24 nonaka Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2001 5 * Shin Takemura and PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 /* 36 * Do not edit. 37 * This file is automatically generated by platid.awk. 38 */ 39 #include <machine/platid.h> 40 #include <machine/platid_mask.h> 41 #ifdef hpcmips 42 platid_t platid_mask_CPU_MIPS = {{ 43 PLATID_CPU_MIPS, 44 PLATID_WILD 45 }}; 46 platid_t platid_mask_CPU_MIPS_VR = {{ 47 PLATID_CPU_MIPS_VR, 48 PLATID_WILD 49 }}; 50 platid_t platid_mask_CPU_MIPS_VR_41XX = {{ 51 PLATID_CPU_MIPS_VR_41XX, 52 PLATID_WILD 53 }}; 54 platid_t platid_mask_CPU_MIPS_VR_4102 = {{ 55 PLATID_CPU_MIPS_VR_4102, 56 PLATID_WILD 57 }}; 58 platid_t platid_mask_CPU_MIPS_VR_4111 = {{ 59 PLATID_CPU_MIPS_VR_4111, 60 PLATID_WILD 61 }}; 62 platid_t platid_mask_CPU_MIPS_VR_4121 = {{ 63 PLATID_CPU_MIPS_VR_4121, 64 PLATID_WILD 65 }}; 66 platid_t platid_mask_CPU_MIPS_VR_4181 = {{ 67 PLATID_CPU_MIPS_VR_4181, 68 PLATID_WILD 69 }}; 70 platid_t platid_mask_CPU_MIPS_VR_4122 = {{ 71 PLATID_CPU_MIPS_VR_4122, 72 PLATID_WILD 73 }}; 74 platid_t platid_mask_CPU_MIPS_VR_4131 = {{ 75 PLATID_CPU_MIPS_VR_4131, 76 PLATID_WILD 77 }}; 78 platid_t platid_mask_CPU_MIPS_VR_4181A = {{ 79 PLATID_CPU_MIPS_VR_4181A, 80 PLATID_WILD 81 }}; 82 platid_t platid_mask_CPU_MIPS_TX = {{ 83 PLATID_CPU_MIPS_TX, 84 PLATID_WILD 85 }}; 86 platid_t platid_mask_CPU_MIPS_TX_3900 = {{ 87 PLATID_CPU_MIPS_TX_3900, 88 PLATID_WILD 89 }}; 90 platid_t platid_mask_CPU_MIPS_TX_3911 = {{ 91 PLATID_CPU_MIPS_TX_3911, 92 PLATID_WILD 93 }}; 94 platid_t platid_mask_CPU_MIPS_TX_3912 = {{ 95 PLATID_CPU_MIPS_TX_3912, 96 PLATID_WILD 97 }}; 98 platid_t platid_mask_CPU_MIPS_TX_3920 = {{ 99 PLATID_CPU_MIPS_TX_3920, 100 PLATID_WILD 101 }}; 102 platid_t platid_mask_CPU_MIPS_TX_3922 = {{ 103 PLATID_CPU_MIPS_TX_3922, 104 PLATID_WILD 105 }}; 106 platid_t platid_mask_CPU_MIPS_TX_3927 = {{ 107 PLATID_CPU_MIPS_TX_3927, 108 PLATID_WILD 109 }}; 110 #endif /* hpcmips */ 111 #ifdef hpcsh 112 platid_t platid_mask_CPU_SH = {{ 113 PLATID_CPU_SH, 114 PLATID_WILD 115 }}; 116 platid_t platid_mask_CPU_SH_3 = {{ 117 PLATID_CPU_SH_3, 118 PLATID_WILD 119 }}; 120 platid_t platid_mask_CPU_SH_3_7709 = {{ 121 PLATID_CPU_SH_3_7709, 122 PLATID_WILD 123 }}; 124 platid_t platid_mask_CPU_SH_3_7709A = {{ 125 PLATID_CPU_SH_3_7709A, 126 PLATID_WILD 127 }}; 128 platid_t platid_mask_CPU_SH_3_7707 = {{ 129 PLATID_CPU_SH_3_7707, 130 PLATID_WILD 131 }}; 132 platid_t platid_mask_CPU_SH_4 = {{ 133 PLATID_CPU_SH_4, 134 PLATID_WILD 135 }}; 136 platid_t platid_mask_CPU_SH_4_7750 = {{ 137 PLATID_CPU_SH_4_7750, 138 PLATID_WILD 139 }}; 140 #endif /* hpcsh */ 141 #ifdef hpcarm 142 platid_t platid_mask_CPU_ARM = {{ 143 PLATID_CPU_ARM, 144 PLATID_WILD 145 }}; 146 platid_t platid_mask_CPU_ARM_STRONGARM = {{ 147 PLATID_CPU_ARM_STRONGARM, 148 PLATID_WILD 149 }}; 150 platid_t platid_mask_CPU_ARM_STRONGARM_SA1100 = {{ 151 PLATID_CPU_ARM_STRONGARM_SA1100, 152 PLATID_WILD 153 }}; 154 platid_t platid_mask_CPU_ARM_STRONGARM_SA1110 = {{ 155 PLATID_CPU_ARM_STRONGARM_SA1110, 156 PLATID_WILD 157 }}; 158 platid_t platid_mask_CPU_ARM_XSCALE = {{ 159 PLATID_CPU_ARM_XSCALE, 160 PLATID_WILD 161 }}; 162 platid_t platid_mask_CPU_ARM_XSCALE_PXA250 = {{ 163 PLATID_CPU_ARM_XSCALE_PXA250, 164 PLATID_WILD 165 }}; 166 platid_t platid_mask_CPU_ARM_XSCALE_PXA270 = {{ 167 PLATID_CPU_ARM_XSCALE_PXA270, 168 PLATID_WILD 169 }}; 170 #endif /* hpcarm */ 171 #ifdef hpcmips 172 platid_t platid_mask_MACH_NEC = {{ 173 PLATID_WILD, 174 PLATID_MACH_NEC 175 }}; 176 platid_t platid_mask_MACH_NEC_MCCS = {{ 177 PLATID_WILD, 178 PLATID_MACH_NEC_MCCS 179 }}; 180 platid_t platid_mask_MACH_NEC_MCCS_1X = {{ 181 PLATID_WILD, 182 PLATID_MACH_NEC_MCCS_1X 183 }}; 184 platid_t platid_mask_MACH_NEC_MCCS_11 = {{ 185 PLATID_CPU_MIPS_VR_4102, 186 PLATID_MACH_NEC_MCCS_11 187 }}; 188 platid_t platid_mask_MACH_NEC_MCCS_12 = {{ 189 PLATID_CPU_MIPS_VR_4102, 190 PLATID_MACH_NEC_MCCS_12 191 }}; 192 platid_t platid_mask_MACH_NEC_MCCS_13 = {{ 193 PLATID_CPU_MIPS_VR_4102, 194 PLATID_MACH_NEC_MCCS_13 195 }}; 196 platid_t platid_mask_MACH_NEC_MCR = {{ 197 PLATID_WILD, 198 PLATID_MACH_NEC_MCR 199 }}; 200 platid_t platid_mask_MACH_NEC_MCR_3XX = {{ 201 PLATID_CPU_MIPS_VR_41XX, 202 PLATID_MACH_NEC_MCR_3XX 203 }}; 204 platid_t platid_mask_MACH_NEC_MCR_300 = {{ 205 PLATID_CPU_MIPS_VR_4111, 206 PLATID_MACH_NEC_MCR_300 207 }}; 208 platid_t platid_mask_MACH_NEC_MCR_320 = {{ 209 PLATID_CPU_MIPS_VR_4121, 210 PLATID_MACH_NEC_MCR_320 211 }}; 212 platid_t platid_mask_MACH_NEC_MCR_FORDOCOMO = {{ 213 PLATID_CPU_MIPS_VR_4111, 214 PLATID_MACH_NEC_MCR_FORDOCOMO 215 }}; 216 platid_t platid_mask_MACH_NEC_MCR_MPRO700 = {{ 217 PLATID_CPU_MIPS_VR_4102, 218 PLATID_MACH_NEC_MCR_MPRO700 219 }}; 220 platid_t platid_mask_MACH_NEC_MCR_330 = {{ 221 PLATID_CPU_MIPS_VR_4121, 222 PLATID_MACH_NEC_MCR_330 223 }}; 224 platid_t platid_mask_MACH_NEC_MCR_5XX = {{ 225 PLATID_CPU_MIPS_VR_41XX, 226 PLATID_MACH_NEC_MCR_5XX 227 }}; 228 platid_t platid_mask_MACH_NEC_MCR_500 = {{ 229 PLATID_CPU_MIPS_VR_4111, 230 PLATID_MACH_NEC_MCR_500 231 }}; 232 platid_t platid_mask_MACH_NEC_MCR_510 = {{ 233 PLATID_CPU_MIPS_VR_4121, 234 PLATID_MACH_NEC_MCR_510 235 }}; 236 platid_t platid_mask_MACH_NEC_MCR_520 = {{ 237 PLATID_CPU_MIPS_VR_4121, 238 PLATID_MACH_NEC_MCR_520 239 }}; 240 platid_t platid_mask_MACH_NEC_MCR_520A = {{ 241 PLATID_CPU_MIPS_VR_4121, 242 PLATID_MACH_NEC_MCR_520A 243 }}; 244 platid_t platid_mask_MACH_NEC_MCR_500A = {{ 245 PLATID_CPU_MIPS_VR_4111, 246 PLATID_MACH_NEC_MCR_500A 247 }}; 248 platid_t platid_mask_MACH_NEC_MCR_530 = {{ 249 PLATID_CPU_MIPS_VR_4121, 250 PLATID_MACH_NEC_MCR_530 251 }}; 252 platid_t platid_mask_MACH_NEC_MCR_430 = {{ 253 PLATID_CPU_MIPS_VR_4121, 254 PLATID_MACH_NEC_MCR_430 255 }}; 256 platid_t platid_mask_MACH_NEC_MCR_530A = {{ 257 PLATID_CPU_MIPS_VR_4121, 258 PLATID_MACH_NEC_MCR_530A 259 }}; 260 platid_t platid_mask_MACH_NEC_MCR_SIGMARION = {{ 261 PLATID_CPU_MIPS_VR_4121, 262 PLATID_MACH_NEC_MCR_SIGMARION 263 }}; 264 platid_t platid_mask_MACH_NEC_MCR_550 = {{ 265 PLATID_CPU_MIPS_VR_4121, 266 PLATID_MACH_NEC_MCR_550 267 }}; 268 platid_t platid_mask_MACH_NEC_MCR_450 = {{ 269 PLATID_CPU_MIPS_VR_4121, 270 PLATID_MACH_NEC_MCR_450 271 }}; 272 platid_t platid_mask_MACH_NEC_MCR_SIGMARION2 = {{ 273 PLATID_CPU_MIPS_VR_4131, 274 PLATID_MACH_NEC_MCR_SIGMARION2 275 }}; 276 platid_t platid_mask_MACH_NEC_MCR_7XX = {{ 277 PLATID_CPU_MIPS_VR_41XX, 278 PLATID_MACH_NEC_MCR_7XX 279 }}; 280 platid_t platid_mask_MACH_NEC_MCR_700 = {{ 281 PLATID_CPU_MIPS_VR_4121, 282 PLATID_MACH_NEC_MCR_700 283 }}; 284 platid_t platid_mask_MACH_NEC_MCR_700A = {{ 285 PLATID_CPU_MIPS_VR_4121, 286 PLATID_MACH_NEC_MCR_700A 287 }}; 288 platid_t platid_mask_MACH_NEC_MCR_730 = {{ 289 PLATID_CPU_MIPS_VR_4121, 290 PLATID_MACH_NEC_MCR_730 291 }}; 292 platid_t platid_mask_MACH_NEC_MCR_730A = {{ 293 PLATID_CPU_MIPS_VR_4121, 294 PLATID_MACH_NEC_MCR_730A 295 }}; 296 #endif /* hpcmips */ 297 #ifdef hpcmips 298 platid_t platid_mask_MACH_EVEREX = {{ 299 PLATID_WILD, 300 PLATID_MACH_EVEREX 301 }}; 302 platid_t platid_mask_MACH_EVEREX_FREESTYLE = {{ 303 PLATID_WILD, 304 PLATID_MACH_EVEREX_FREESTYLE 305 }}; 306 platid_t platid_mask_MACH_EVEREX_FREESTYLE_AXX = {{ 307 PLATID_CPU_MIPS_VR_41XX, 308 PLATID_MACH_EVEREX_FREESTYLE_AXX 309 }}; 310 platid_t platid_mask_MACH_EVEREX_FREESTYLE_A10 = {{ 311 PLATID_CPU_MIPS_VR_4102, 312 PLATID_MACH_EVEREX_FREESTYLE_A10 313 }}; 314 platid_t platid_mask_MACH_EVEREX_FREESTYLE_A15 = {{ 315 PLATID_CPU_MIPS_VR_4111, 316 PLATID_MACH_EVEREX_FREESTYLE_A15 317 }}; 318 platid_t platid_mask_MACH_EVEREX_FREESTYLE_A20 = {{ 319 PLATID_CPU_MIPS_VR_4111, 320 PLATID_MACH_EVEREX_FREESTYLE_A20 321 }}; 322 #endif /* hpcmips */ 323 platid_t platid_mask_MACH_CASIO = {{ 324 PLATID_WILD, 325 PLATID_MACH_CASIO 326 }}; 327 #ifdef hpcmips 328 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE = {{ 329 PLATID_WILD, 330 PLATID_MACH_CASIO_CASSIOPEIAE 331 }}; 332 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_EXX = {{ 333 PLATID_WILD, 334 PLATID_MACH_CASIO_CASSIOPEIAE_EXX 335 }}; 336 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E10 = {{ 337 PLATID_CPU_MIPS_VR_4111, 338 PLATID_MACH_CASIO_CASSIOPEIAE_E10 339 }}; 340 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E11 = {{ 341 PLATID_CPU_MIPS_VR_4111, 342 PLATID_MACH_CASIO_CASSIOPEIAE_E11 343 }}; 344 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E15 = {{ 345 PLATID_CPU_MIPS_VR_4111, 346 PLATID_MACH_CASIO_CASSIOPEIAE_E15 347 }}; 348 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E55 = {{ 349 PLATID_CPU_MIPS_VR_4111, 350 PLATID_MACH_CASIO_CASSIOPEIAE_E55 351 }}; 352 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_FORDOCOMO = {{ 353 PLATID_CPU_MIPS_VR_4111, 354 PLATID_MACH_CASIO_CASSIOPEIAE_FORDOCOMO 355 }}; 356 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E65 = {{ 357 PLATID_CPU_MIPS_VR_4111, 358 PLATID_MACH_CASIO_CASSIOPEIAE_E65 359 }}; 360 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_EXXX = {{ 361 PLATID_WILD, 362 PLATID_MACH_CASIO_CASSIOPEIAE_EXXX 363 }}; 364 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E100 = {{ 365 PLATID_CPU_MIPS_VR_4121, 366 PLATID_MACH_CASIO_CASSIOPEIAE_E100 367 }}; 368 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E105 = {{ 369 PLATID_CPU_MIPS_VR_4121, 370 PLATID_MACH_CASIO_CASSIOPEIAE_E105 371 }}; 372 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E500 = {{ 373 PLATID_CPU_MIPS_VR_4121, 374 PLATID_MACH_CASIO_CASSIOPEIAE_E500 375 }}; 376 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E507 = {{ 377 PLATID_CPU_MIPS_VR_4121, 378 PLATID_MACH_CASIO_CASSIOPEIAE_E507 379 }}; 380 platid_t platid_mask_MACH_CASIO_POCKETPOSTPET = {{ 381 PLATID_WILD, 382 PLATID_MACH_CASIO_POCKETPOSTPET 383 }}; 384 platid_t platid_mask_MACH_CASIO_POCKETPOSTPET_POCKETPOSTPET = {{ 385 PLATID_CPU_MIPS_VR_4121, 386 PLATID_MACH_CASIO_POCKETPOSTPET_POCKETPOSTPET 387 }}; 388 #endif /* hpcmips */ 389 #ifdef hpcsh 390 platid_t platid_mask_MACH_CASIO_CASSIOPEIAA = {{ 391 PLATID_WILD, 392 PLATID_MACH_CASIO_CASSIOPEIAA 393 }}; 394 platid_t platid_mask_MACH_CASIO_CASSIOPEIAA_AXX = {{ 395 PLATID_WILD, 396 PLATID_MACH_CASIO_CASSIOPEIAA_AXX 397 }}; 398 platid_t platid_mask_MACH_CASIO_CASSIOPEIAA_A55V = {{ 399 PLATID_CPU_SH_3_7709, 400 PLATID_MACH_CASIO_CASSIOPEIAA_A55V 401 }}; 402 #endif /* hpcsh */ 403 #if defined(hpcmips) || defined(hpcarm) 404 platid_t platid_mask_MACH_SHARP = {{ 405 PLATID_WILD, 406 PLATID_MACH_SHARP 407 }}; 408 #if defined(hpcmips) 409 platid_t platid_mask_MACH_SHARP_TRIPAD = {{ 410 PLATID_WILD, 411 PLATID_MACH_SHARP_TRIPAD 412 }}; 413 platid_t platid_mask_MACH_SHARP_TRIPAD_PV = {{ 414 PLATID_WILD, 415 PLATID_MACH_SHARP_TRIPAD_PV 416 }}; 417 platid_t platid_mask_MACH_SHARP_TRIPAD_PV6000 = {{ 418 PLATID_CPU_MIPS_VR_4111, 419 PLATID_MACH_SHARP_TRIPAD_PV6000 420 }}; 421 platid_t platid_mask_MACH_SHARP_TELIOS = {{ 422 PLATID_WILD, 423 PLATID_MACH_SHARP_TELIOS 424 }}; 425 platid_t platid_mask_MACH_SHARP_TELIOS_HCAJ = {{ 426 PLATID_WILD, 427 PLATID_MACH_SHARP_TELIOS_HCAJ 428 }}; 429 platid_t platid_mask_MACH_SHARP_TELIOS_HCAJ1_JP = {{ 430 PLATID_CPU_MIPS_TX_3922, 431 PLATID_MACH_SHARP_TELIOS_HCAJ1_JP 432 }}; 433 platid_t platid_mask_MACH_SHARP_TELIOS_HCAJ2_JP = {{ 434 PLATID_CPU_MIPS_TX_3922, 435 PLATID_MACH_SHARP_TELIOS_HCAJ2_JP 436 }}; 437 platid_t platid_mask_MACH_SHARP_TELIOS_HCAJ3_JP = {{ 438 PLATID_CPU_MIPS_TX_3922, 439 PLATID_MACH_SHARP_TELIOS_HCAJ3_JP 440 }}; 441 platid_t platid_mask_MACH_SHARP_TELIOS_HCVJ = {{ 442 PLATID_WILD, 443 PLATID_MACH_SHARP_TELIOS_HCVJ 444 }}; 445 platid_t platid_mask_MACH_SHARP_TELIOS_HCVJ1C_JP = {{ 446 PLATID_WILD, 447 PLATID_MACH_SHARP_TELIOS_HCVJ1C_JP 448 }}; 449 platid_t platid_mask_MACH_SHARP_MOBILON = {{ 450 PLATID_WILD, 451 PLATID_MACH_SHARP_MOBILON 452 }}; 453 platid_t platid_mask_MACH_SHARP_MOBILON_HC = {{ 454 PLATID_WILD, 455 PLATID_MACH_SHARP_MOBILON_HC 456 }}; 457 platid_t platid_mask_MACH_SHARP_MOBILON_HC4100 = {{ 458 PLATID_CPU_MIPS_TX_3912, 459 PLATID_MACH_SHARP_MOBILON_HC4100 460 }}; 461 platid_t platid_mask_MACH_SHARP_MOBILON_HC4500 = {{ 462 PLATID_CPU_MIPS_TX_3912, 463 PLATID_MACH_SHARP_MOBILON_HC4500 464 }}; 465 platid_t platid_mask_MACH_SHARP_MOBILON_HC1200 = {{ 466 PLATID_CPU_MIPS_TX_3912, 467 PLATID_MACH_SHARP_MOBILON_HC1200 468 }}; 469 #endif /* hpcmips */ 470 #if defined(hpcarm) 471 platid_t platid_mask_MACH_SHARP_WZERO3 = {{ 472 PLATID_WILD, 473 PLATID_MACH_SHARP_WZERO3 474 }}; 475 platid_t platid_mask_MACH_SHARP_WZERO3_WS003SH = {{ 476 PLATID_CPU_ARM_XSCALE_PXA270, 477 PLATID_MACH_SHARP_WZERO3_WS003SH 478 }}; 479 platid_t platid_mask_MACH_SHARP_WZERO3_WS004SH = {{ 480 PLATID_CPU_ARM_XSCALE_PXA270, 481 PLATID_MACH_SHARP_WZERO3_WS004SH 482 }}; 483 platid_t platid_mask_MACH_SHARP_WZERO3_WS007SH = {{ 484 PLATID_CPU_ARM_XSCALE_PXA270, 485 PLATID_MACH_SHARP_WZERO3_WS007SH 486 }}; 487 platid_t platid_mask_MACH_SHARP_WZERO3_WS011SH = {{ 488 PLATID_CPU_ARM_XSCALE_PXA270, 489 PLATID_MACH_SHARP_WZERO3_WS011SH 490 }}; 491 platid_t platid_mask_MACH_SHARP_WZERO3_WS020SH = {{ 492 PLATID_CPU_ARM_XSCALE_PXA270, 493 PLATID_MACH_SHARP_WZERO3_WS020SH 494 }}; 495 #endif /* hpcarm */ 496 #endif /* hpcmips || hpcarm */ 497 #ifdef hpcmips 498 platid_t platid_mask_MACH_FUJITSU = {{ 499 PLATID_WILD, 500 PLATID_MACH_FUJITSU 501 }}; 502 platid_t platid_mask_MACH_FUJITSU_INTERTOP = {{ 503 PLATID_WILD, 504 PLATID_MACH_FUJITSU_INTERTOP 505 }}; 506 platid_t platid_mask_MACH_FUJITSU_INTERTOP_ITXXX = {{ 507 PLATID_WILD, 508 PLATID_MACH_FUJITSU_INTERTOP_ITXXX 509 }}; 510 platid_t platid_mask_MACH_FUJITSU_INTERTOP_IT300 = {{ 511 PLATID_CPU_MIPS_VR_4121, 512 PLATID_MACH_FUJITSU_INTERTOP_IT300 513 }}; 514 platid_t platid_mask_MACH_FUJITSU_INTERTOP_IT310 = {{ 515 PLATID_CPU_MIPS_VR_4121, 516 PLATID_MACH_FUJITSU_INTERTOP_IT310 517 }}; 518 platid_t platid_mask_MACH_FUJITSU_PENCENTRA = {{ 519 PLATID_WILD, 520 PLATID_MACH_FUJITSU_PENCENTRA 521 }}; 522 platid_t platid_mask_MACH_FUJITSU_PENCENTRA_130 = {{ 523 PLATID_CPU_MIPS_VR_4121, 524 PLATID_MACH_FUJITSU_PENCENTRA_130 525 }}; 526 platid_t platid_mask_MACH_FUJITSU_PENCENTRA_130TM = {{ 527 PLATID_CPU_MIPS_VR_4121, 528 PLATID_MACH_FUJITSU_PENCENTRA_130TM 529 }}; 530 platid_t platid_mask_MACH_FUJITSU_PENCENTRA_130RF = {{ 531 PLATID_CPU_MIPS_VR_4121, 532 PLATID_MACH_FUJITSU_PENCENTRA_130RF 533 }}; 534 platid_t platid_mask_MACH_FUJITSU_PENCENTRA_200 = {{ 535 PLATID_CPU_MIPS_TX_3922, 536 PLATID_MACH_FUJITSU_PENCENTRA_200 537 }}; 538 platid_t platid_mask_MACH_FUJITSU_PENCENTRA_200CTM = {{ 539 PLATID_CPU_MIPS_TX_3922, 540 PLATID_MACH_FUJITSU_PENCENTRA_200CTM 541 }}; 542 platid_t platid_mask_MACH_FUJITSU_PENCENTRA_200CRF = {{ 543 PLATID_CPU_MIPS_TX_3922, 544 PLATID_MACH_FUJITSU_PENCENTRA_200CRF 545 }}; 546 #endif /* hpcmips */ 547 #ifdef hpcmips 548 platid_t platid_mask_MACH_PHILIPS = {{ 549 PLATID_WILD, 550 PLATID_MACH_PHILIPS 551 }}; 552 platid_t platid_mask_MACH_PHILIPS_NINO = {{ 553 PLATID_WILD, 554 PLATID_MACH_PHILIPS_NINO 555 }}; 556 platid_t platid_mask_MACH_PHILIPS_NINO_3XX = {{ 557 PLATID_WILD, 558 PLATID_MACH_PHILIPS_NINO_3XX 559 }}; 560 platid_t platid_mask_MACH_PHILIPS_NINO_312 = {{ 561 PLATID_CPU_MIPS_TX_3912, 562 PLATID_MACH_PHILIPS_NINO_312 563 }}; 564 #endif /* hpcmips */ 565 platid_t platid_mask_MACH_COMPAQ = {{ 566 PLATID_WILD, 567 PLATID_MACH_COMPAQ 568 }}; 569 #ifdef hpcmips 570 platid_t platid_mask_MACH_COMPAQ_C = {{ 571 PLATID_WILD, 572 PLATID_MACH_COMPAQ_C 573 }}; 574 platid_t platid_mask_MACH_COMPAQ_C_8XX = {{ 575 PLATID_WILD, 576 PLATID_MACH_COMPAQ_C_8XX 577 }}; 578 platid_t platid_mask_MACH_COMPAQ_C_810 = {{ 579 PLATID_CPU_MIPS_TX_3912, 580 PLATID_MACH_COMPAQ_C_810 581 }}; 582 platid_t platid_mask_MACH_COMPAQ_C_201X = {{ 583 PLATID_WILD, 584 PLATID_MACH_COMPAQ_C_201X 585 }}; 586 platid_t platid_mask_MACH_COMPAQ_C_2010 = {{ 587 PLATID_CPU_MIPS_TX_3912, 588 PLATID_MACH_COMPAQ_C_2010 589 }}; 590 platid_t platid_mask_MACH_COMPAQ_C_2015 = {{ 591 PLATID_CPU_MIPS_TX_3912, 592 PLATID_MACH_COMPAQ_C_2015 593 }}; 594 platid_t platid_mask_MACH_COMPAQ_AERO = {{ 595 PLATID_WILD, 596 PLATID_MACH_COMPAQ_AERO 597 }}; 598 platid_t platid_mask_MACH_COMPAQ_AERO_15XX = {{ 599 PLATID_WILD, 600 PLATID_MACH_COMPAQ_AERO_15XX 601 }}; 602 platid_t platid_mask_MACH_COMPAQ_AERO_1530 = {{ 603 PLATID_CPU_MIPS_VR_4111, 604 PLATID_MACH_COMPAQ_AERO_1530 605 }}; 606 platid_t platid_mask_MACH_COMPAQ_AERO_21XX = {{ 607 PLATID_WILD, 608 PLATID_MACH_COMPAQ_AERO_21XX 609 }}; 610 platid_t platid_mask_MACH_COMPAQ_AERO_2110 = {{ 611 PLATID_CPU_MIPS_VR_4111, 612 PLATID_MACH_COMPAQ_AERO_2110 613 }}; 614 platid_t platid_mask_MACH_COMPAQ_AERO_2130 = {{ 615 PLATID_CPU_MIPS_VR_4111, 616 PLATID_MACH_COMPAQ_AERO_2130 617 }}; 618 platid_t platid_mask_MACH_COMPAQ_AERO_2140 = {{ 619 PLATID_CPU_MIPS_VR_4111, 620 PLATID_MACH_COMPAQ_AERO_2140 621 }}; 622 platid_t platid_mask_MACH_COMPAQ_PRESARIO = {{ 623 PLATID_WILD, 624 PLATID_MACH_COMPAQ_PRESARIO 625 }}; 626 platid_t platid_mask_MACH_COMPAQ_PRESARIO_21X = {{ 627 PLATID_WILD, 628 PLATID_MACH_COMPAQ_PRESARIO_21X 629 }}; 630 platid_t platid_mask_MACH_COMPAQ_PRESARIO_213 = {{ 631 PLATID_CPU_MIPS_VR_4111, 632 PLATID_MACH_COMPAQ_PRESARIO_213 633 }}; 634 #endif /* hpcmips */ 635 #ifdef hpcarm 636 platid_t platid_mask_MACH_COMPAQ_IPAQ = {{ 637 PLATID_WILD, 638 PLATID_MACH_COMPAQ_IPAQ 639 }}; 640 platid_t platid_mask_MACH_COMPAQ_IPAQ_H31XX = {{ 641 PLATID_WILD, 642 PLATID_MACH_COMPAQ_IPAQ_H31XX 643 }}; 644 platid_t platid_mask_MACH_COMPAQ_IPAQ_H3100 = {{ 645 PLATID_CPU_ARM_STRONGARM_SA1110, 646 PLATID_MACH_COMPAQ_IPAQ_H3100 647 }}; 648 platid_t platid_mask_MACH_COMPAQ_IPAQ_H36XX = {{ 649 PLATID_WILD, 650 PLATID_MACH_COMPAQ_IPAQ_H36XX 651 }}; 652 platid_t platid_mask_MACH_COMPAQ_IPAQ_H3600 = {{ 653 PLATID_CPU_ARM_STRONGARM_SA1110, 654 PLATID_MACH_COMPAQ_IPAQ_H3600 655 }}; 656 platid_t platid_mask_MACH_COMPAQ_IPAQ_H3660 = {{ 657 PLATID_CPU_ARM_STRONGARM_SA1110, 658 PLATID_MACH_COMPAQ_IPAQ_H3660 659 }}; 660 platid_t platid_mask_MACH_COMPAQ_IPAQ_H39XX = {{ 661 PLATID_WILD, 662 PLATID_MACH_COMPAQ_IPAQ_H39XX 663 }}; 664 platid_t platid_mask_MACH_COMPAQ_IPAQ_H3900 = {{ 665 PLATID_CPU_ARM_XSCALE_PXA250, 666 PLATID_MACH_COMPAQ_IPAQ_H3900 667 }}; 668 #endif /* hpcarm */ 669 #ifdef hpcsh 670 platid_t platid_mask_MACH_COMPAQ_AERO = {{ 671 PLATID_WILD, 672 PLATID_MACH_COMPAQ_AERO 673 }}; 674 platid_t platid_mask_MACH_COMPAQ_AERO_8000 = {{ 675 PLATID_WILD, 676 PLATID_MACH_COMPAQ_AERO_8000 677 }}; 678 #endif /* hpcsh */ 679 #ifdef hpcmips 680 platid_t platid_mask_MACH_VICTOR = {{ 681 PLATID_WILD, 682 PLATID_MACH_VICTOR 683 }}; 684 platid_t platid_mask_MACH_VICTOR_INTERLINK = {{ 685 PLATID_WILD, 686 PLATID_MACH_VICTOR_INTERLINK 687 }}; 688 platid_t platid_mask_MACH_VICTOR_INTERLINK_MP = {{ 689 PLATID_WILD, 690 PLATID_MACH_VICTOR_INTERLINK_MP 691 }}; 692 platid_t platid_mask_MACH_VICTOR_INTERLINK_MPC101 = {{ 693 PLATID_CPU_MIPS_TX_3922, 694 PLATID_MACH_VICTOR_INTERLINK_MPC101 695 }}; 696 platid_t platid_mask_MACH_VICTOR_INTERLINK_MPC303 = {{ 697 PLATID_CPU_MIPS_VR_4122, 698 PLATID_MACH_VICTOR_INTERLINK_MPC303 699 }}; 700 platid_t platid_mask_MACH_VICTOR_INTERLINK_MPC304 = {{ 701 PLATID_CPU_MIPS_VR_4122, 702 PLATID_MACH_VICTOR_INTERLINK_MPC304 703 }}; 704 #endif /* hpcmips */ 705 #ifdef hpcmips 706 platid_t platid_mask_MACH_IBM = {{ 707 PLATID_WILD, 708 PLATID_MACH_IBM 709 }}; 710 platid_t platid_mask_MACH_IBM_WORKPAD = {{ 711 PLATID_WILD, 712 PLATID_MACH_IBM_WORKPAD 713 }}; 714 platid_t platid_mask_MACH_IBM_WORKPAD_Z50 = {{ 715 PLATID_WILD, 716 PLATID_MACH_IBM_WORKPAD_Z50 717 }}; 718 platid_t platid_mask_MACH_IBM_WORKPAD_26011AU = {{ 719 PLATID_CPU_MIPS_VR_4121, 720 PLATID_MACH_IBM_WORKPAD_26011AU 721 }}; 722 #endif /* hpcmips */ 723 #ifdef hpcmips 724 platid_t platid_mask_MACH_VADEM = {{ 725 PLATID_WILD, 726 PLATID_MACH_VADEM 727 }}; 728 platid_t platid_mask_MACH_VADEM_CLIO = {{ 729 PLATID_WILD, 730 PLATID_MACH_VADEM_CLIO 731 }}; 732 platid_t platid_mask_MACH_VADEM_CLIO_C = {{ 733 PLATID_WILD, 734 PLATID_MACH_VADEM_CLIO_C 735 }}; 736 platid_t platid_mask_MACH_VADEM_CLIO_C1000 = {{ 737 PLATID_CPU_MIPS_VR_4111, 738 PLATID_MACH_VADEM_CLIO_C1000 739 }}; 740 platid_t platid_mask_MACH_VADEM_CLIO_C1050 = {{ 741 PLATID_CPU_MIPS_VR_4121, 742 PLATID_MACH_VADEM_CLIO_C1050 743 }}; 744 #endif /* hpcmips */ 745 platid_t platid_mask_MACH_HP = {{ 746 PLATID_WILD, 747 PLATID_MACH_HP 748 }}; 749 #ifdef hpcsh 750 platid_t platid_mask_MACH_HP_LX = {{ 751 PLATID_WILD, 752 PLATID_MACH_HP_LX 753 }}; 754 platid_t platid_mask_MACH_HP_LX_620 = {{ 755 PLATID_CPU_SH_3_7709, 756 PLATID_MACH_HP_LX_620 757 }}; 758 platid_t platid_mask_MACH_HP_LX_620JP = {{ 759 PLATID_CPU_SH_3_7709, 760 PLATID_MACH_HP_LX_620JP 761 }}; 762 platid_t platid_mask_MACH_HP_LX_360 = {{ 763 PLATID_CPU_SH_3_7707, 764 PLATID_MACH_HP_LX_360 765 }}; 766 #endif /* hpcsh */ 767 platid_t platid_mask_MACH_HP_JORNADA = {{ 768 PLATID_WILD, 769 PLATID_MACH_HP_JORNADA 770 }}; 771 #ifdef hpcsh 772 platid_t platid_mask_MACH_HP_JORNADA_6XX = {{ 773 PLATID_WILD, 774 PLATID_MACH_HP_JORNADA_6XX 775 }}; 776 platid_t platid_mask_MACH_HP_JORNADA_680 = {{ 777 PLATID_CPU_SH_3_7709A, 778 PLATID_MACH_HP_JORNADA_680 779 }}; 780 platid_t platid_mask_MACH_HP_JORNADA_680JP = {{ 781 PLATID_CPU_SH_3_7709A, 782 PLATID_MACH_HP_JORNADA_680JP 783 }}; 784 platid_t platid_mask_MACH_HP_JORNADA_680EU = {{ 785 PLATID_CPU_SH_3_7709A, 786 PLATID_MACH_HP_JORNADA_680EU 787 }}; 788 platid_t platid_mask_MACH_HP_JORNADA_680DE = {{ 789 PLATID_CPU_SH_3_7709A, 790 PLATID_MACH_HP_JORNADA_680DE 791 }}; 792 platid_t platid_mask_MACH_HP_JORNADA_690 = {{ 793 PLATID_CPU_SH_3_7709A, 794 PLATID_MACH_HP_JORNADA_690 795 }}; 796 platid_t platid_mask_MACH_HP_JORNADA_690JP = {{ 797 PLATID_CPU_SH_3_7709A, 798 PLATID_MACH_HP_JORNADA_690JP 799 }}; 800 platid_t platid_mask_MACH_HP_JORNADA_690EU = {{ 801 PLATID_CPU_SH_3_7709A, 802 PLATID_MACH_HP_JORNADA_690EU 803 }}; 804 platid_t platid_mask_MACH_HP_JORNADA_690DE = {{ 805 PLATID_CPU_SH_3_7709A, 806 PLATID_MACH_HP_JORNADA_690DE 807 }}; 808 platid_t platid_mask_MACH_HP_JORNADA_680FR = {{ 809 PLATID_CPU_SH_3_7709A, 810 PLATID_MACH_HP_JORNADA_680FR 811 }}; 812 platid_t platid_mask_MACH_HP_JORNADA_690FR = {{ 813 PLATID_CPU_SH_3_7709A, 814 PLATID_MACH_HP_JORNADA_690FR 815 }}; 816 platid_t platid_mask_MACH_HP_JORNADA_680SV = {{ 817 PLATID_CPU_SH_3_7709A, 818 PLATID_MACH_HP_JORNADA_680SV 819 }}; 820 platid_t platid_mask_MACH_HP_JORNADA_690SV = {{ 821 PLATID_CPU_SH_3_7709A, 822 PLATID_MACH_HP_JORNADA_690SV 823 }}; 824 platid_t platid_mask_MACH_HP_JORNADA_680ES = {{ 825 PLATID_CPU_SH_3_7709A, 826 PLATID_MACH_HP_JORNADA_680ES 827 }}; 828 platid_t platid_mask_MACH_HP_JORNADA_690ES = {{ 829 PLATID_CPU_SH_3_7709A, 830 PLATID_MACH_HP_JORNADA_690ES 831 }}; 832 #endif /* hpcsh */ 833 #ifdef hpcarm 834 platid_t platid_mask_MACH_HP_JORNADA_7XX = {{ 835 PLATID_WILD, 836 PLATID_MACH_HP_JORNADA_7XX 837 }}; 838 platid_t platid_mask_MACH_HP_JORNADA_720 = {{ 839 PLATID_CPU_ARM_STRONGARM_SA1110, 840 PLATID_MACH_HP_JORNADA_720 841 }}; 842 platid_t platid_mask_MACH_HP_JORNADA_720JP = {{ 843 PLATID_CPU_ARM_STRONGARM_SA1110, 844 PLATID_MACH_HP_JORNADA_720JP 845 }}; 846 platid_t platid_mask_MACH_HP_JORNADA_720EU = {{ 847 PLATID_CPU_ARM_STRONGARM_SA1110, 848 PLATID_MACH_HP_JORNADA_720EU 849 }}; 850 platid_t platid_mask_MACH_HP_JORNADA_720DE = {{ 851 PLATID_CPU_ARM_STRONGARM_SA1110, 852 PLATID_MACH_HP_JORNADA_720DE 853 }}; 854 platid_t platid_mask_MACH_HP_JORNADA_720FR = {{ 855 PLATID_CPU_ARM_STRONGARM_SA1110, 856 PLATID_MACH_HP_JORNADA_720FR 857 }}; 858 platid_t platid_mask_MACH_HP_JORNADA_720SV = {{ 859 PLATID_CPU_ARM_STRONGARM_SA1110, 860 PLATID_MACH_HP_JORNADA_720SV 861 }}; 862 platid_t platid_mask_MACH_HP_JORNADA_720ES = {{ 863 PLATID_CPU_ARM_STRONGARM_SA1110, 864 PLATID_MACH_HP_JORNADA_720ES 865 }}; 866 platid_t platid_mask_MACH_HP_JORNADA_8XX = {{ 867 PLATID_WILD, 868 PLATID_MACH_HP_JORNADA_8XX 869 }}; 870 platid_t platid_mask_MACH_HP_JORNADA_820 = {{ 871 PLATID_CPU_ARM_STRONGARM_SA1100, 872 PLATID_MACH_HP_JORNADA_820 873 }}; 874 platid_t platid_mask_MACH_HP_JORNADA_820JP = {{ 875 PLATID_CPU_ARM_STRONGARM_SA1100, 876 PLATID_MACH_HP_JORNADA_820JP 877 }}; 878 #endif /* hpcarm */ 879 #ifdef hpcsh 880 platid_t platid_mask_MACH_HITACHI = {{ 881 PLATID_WILD, 882 PLATID_MACH_HITACHI 883 }}; 884 platid_t platid_mask_MACH_HITACHI_PERSONA = {{ 885 PLATID_WILD, 886 PLATID_MACH_HITACHI_PERSONA 887 }}; 888 platid_t platid_mask_MACH_HITACHI_PERSONA_HPW230JC = {{ 889 PLATID_CPU_SH_3_7709, 890 PLATID_MACH_HITACHI_PERSONA_HPW230JC 891 }}; 892 platid_t platid_mask_MACH_HITACHI_PERSONA_HPW50PAD = {{ 893 PLATID_CPU_SH_3_7709, 894 PLATID_MACH_HITACHI_PERSONA_HPW50PAD 895 }}; 896 platid_t platid_mask_MACH_HITACHI_PERSONA_HPW200EC = {{ 897 PLATID_CPU_SH_3_7709, 898 PLATID_MACH_HITACHI_PERSONA_HPW200EC 899 }}; 900 platid_t platid_mask_MACH_HITACHI_PERSONA_HPW650PA = {{ 901 PLATID_CPU_SH_4_7750, 902 PLATID_MACH_HITACHI_PERSONA_HPW650PA 903 }}; 904 #endif /* hpcsh */ 905 #ifdef hpcsh 906 platid_t platid_mask_MACH_LGE = {{ 907 PLATID_WILD, 908 PLATID_MACH_LGE 909 }}; 910 platid_t platid_mask_MACH_LGE_PHENOM = {{ 911 PLATID_WILD, 912 PLATID_MACH_LGE_PHENOM 913 }}; 914 platid_t platid_mask_MACH_LGE_PHENOM_H220C = {{ 915 PLATID_CPU_SH_3_7709, 916 PLATID_MACH_LGE_PHENOM_H220C 917 }}; 918 #endif /* hpcsh */ 919 #ifdef hpcmips 920 platid_t platid_mask_MACH_LASER5 = {{ 921 PLATID_WILD, 922 PLATID_MACH_LASER5 923 }}; 924 platid_t platid_mask_MACH_LASER5_L = {{ 925 PLATID_WILD, 926 PLATID_MACH_LASER5_L 927 }}; 928 platid_t platid_mask_MACH_LASER5_L_CARD = {{ 929 PLATID_CPU_MIPS_VR_4181, 930 PLATID_MACH_LASER5_L_CARD 931 }}; 932 platid_t platid_mask_MACH_LASER5_L_BOARD = {{ 933 PLATID_CPU_MIPS_VR_4122, 934 PLATID_MACH_LASER5_L_BOARD 935 }}; 936 #endif /* hpcmips */ 937 #ifdef hpcmips 938 platid_t platid_mask_MACH_AGENDA = {{ 939 PLATID_WILD, 940 PLATID_MACH_AGENDA 941 }}; 942 platid_t platid_mask_MACH_AGENDA_VR = {{ 943 PLATID_WILD, 944 PLATID_MACH_AGENDA_VR 945 }}; 946 platid_t platid_mask_MACH_AGENDA_VR_VR3 = {{ 947 PLATID_CPU_MIPS_VR_4181, 948 PLATID_MACH_AGENDA_VR_VR3 949 }}; 950 #endif /* hpcmips */ 951