1 /* $NetBSD: platid_mask.c,v 1.13 2001/09/04 08:46:59 sato Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2001 5 * Shin Takemura and PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 /* 36 * Do not edit. 37 * This file is automatically generated by platid.awk. 38 */ 39 #include <machine/platid.h> 40 #include <machine/platid_mask.h> 41 #ifdef hpcmips 42 platid_t platid_mask_CPU_MIPS = {{ 43 PLATID_CPU_MIPS, 44 PLATID_WILD 45 }}; 46 platid_t platid_mask_CPU_MIPS_VR = {{ 47 PLATID_CPU_MIPS_VR, 48 PLATID_WILD 49 }}; 50 platid_t platid_mask_CPU_MIPS_VR_41XX = {{ 51 PLATID_CPU_MIPS_VR_41XX, 52 PLATID_WILD 53 }}; 54 platid_t platid_mask_CPU_MIPS_VR_4102 = {{ 55 PLATID_CPU_MIPS_VR_4102, 56 PLATID_WILD 57 }}; 58 platid_t platid_mask_CPU_MIPS_VR_4111 = {{ 59 PLATID_CPU_MIPS_VR_4111, 60 PLATID_WILD 61 }}; 62 platid_t platid_mask_CPU_MIPS_VR_4121 = {{ 63 PLATID_CPU_MIPS_VR_4121, 64 PLATID_WILD 65 }}; 66 platid_t platid_mask_CPU_MIPS_VR_4181 = {{ 67 PLATID_CPU_MIPS_VR_4181, 68 PLATID_WILD 69 }}; 70 platid_t platid_mask_CPU_MIPS_VR_4122 = {{ 71 PLATID_CPU_MIPS_VR_4122, 72 PLATID_WILD 73 }}; 74 platid_t platid_mask_CPU_MIPS_VR_4131 = {{ 75 PLATID_CPU_MIPS_VR_4131, 76 PLATID_WILD 77 }}; 78 platid_t platid_mask_CPU_MIPS_VR_4181A = {{ 79 PLATID_CPU_MIPS_VR_4181A, 80 PLATID_WILD 81 }}; 82 platid_t platid_mask_CPU_MIPS_TX = {{ 83 PLATID_CPU_MIPS_TX, 84 PLATID_WILD 85 }}; 86 platid_t platid_mask_CPU_MIPS_TX_3900 = {{ 87 PLATID_CPU_MIPS_TX_3900, 88 PLATID_WILD 89 }}; 90 platid_t platid_mask_CPU_MIPS_TX_3911 = {{ 91 PLATID_CPU_MIPS_TX_3911, 92 PLATID_WILD 93 }}; 94 platid_t platid_mask_CPU_MIPS_TX_3912 = {{ 95 PLATID_CPU_MIPS_TX_3912, 96 PLATID_WILD 97 }}; 98 platid_t platid_mask_CPU_MIPS_TX_3920 = {{ 99 PLATID_CPU_MIPS_TX_3920, 100 PLATID_WILD 101 }}; 102 platid_t platid_mask_CPU_MIPS_TX_3922 = {{ 103 PLATID_CPU_MIPS_TX_3922, 104 PLATID_WILD 105 }}; 106 platid_t platid_mask_CPU_MIPS_TX_3927 = {{ 107 PLATID_CPU_MIPS_TX_3927, 108 PLATID_WILD 109 }}; 110 #endif /* hpcmips */ 111 #ifdef hpcsh 112 platid_t platid_mask_CPU_SH = {{ 113 PLATID_CPU_SH, 114 PLATID_WILD 115 }}; 116 platid_t platid_mask_CPU_SH_3 = {{ 117 PLATID_CPU_SH_3, 118 PLATID_WILD 119 }}; 120 platid_t platid_mask_CPU_SH_3_7709 = {{ 121 PLATID_CPU_SH_3_7709, 122 PLATID_WILD 123 }}; 124 platid_t platid_mask_CPU_SH_3_7709A = {{ 125 PLATID_CPU_SH_3_7709A, 126 PLATID_WILD 127 }}; 128 platid_t platid_mask_CPU_SH_4 = {{ 129 PLATID_CPU_SH_4, 130 PLATID_WILD 131 }}; 132 platid_t platid_mask_CPU_SH_4_7750 = {{ 133 PLATID_CPU_SH_4_7750, 134 PLATID_WILD 135 }}; 136 #endif /* hpcsh */ 137 #ifdef hpcarm 138 platid_t platid_mask_CPU_ARM = {{ 139 PLATID_CPU_ARM, 140 PLATID_WILD 141 }}; 142 platid_t platid_mask_CPU_ARM_STRONGARM = {{ 143 PLATID_CPU_ARM_STRONGARM, 144 PLATID_WILD 145 }}; 146 platid_t platid_mask_CPU_ARM_STRONGARM_SA1100 = {{ 147 PLATID_CPU_ARM_STRONGARM_SA1100, 148 PLATID_WILD 149 }}; 150 platid_t platid_mask_CPU_ARM_STRONGARM_SA1110 = {{ 151 PLATID_CPU_ARM_STRONGARM_SA1110, 152 PLATID_WILD 153 }}; 154 #endif /* hpcarm */ 155 #ifdef hpcmips 156 platid_t platid_mask_MACH_NEC = {{ 157 PLATID_WILD, 158 PLATID_MACH_NEC 159 }}; 160 platid_t platid_mask_MACH_NEC_MCCS = {{ 161 PLATID_WILD, 162 PLATID_MACH_NEC_MCCS 163 }}; 164 platid_t platid_mask_MACH_NEC_MCCS_1X = {{ 165 PLATID_WILD, 166 PLATID_MACH_NEC_MCCS_1X 167 }}; 168 platid_t platid_mask_MACH_NEC_MCCS_11 = {{ 169 PLATID_CPU_MIPS_VR_4102, 170 PLATID_MACH_NEC_MCCS_11 171 }}; 172 platid_t platid_mask_MACH_NEC_MCCS_12 = {{ 173 PLATID_CPU_MIPS_VR_4102, 174 PLATID_MACH_NEC_MCCS_12 175 }}; 176 platid_t platid_mask_MACH_NEC_MCCS_13 = {{ 177 PLATID_CPU_MIPS_VR_4102, 178 PLATID_MACH_NEC_MCCS_13 179 }}; 180 platid_t platid_mask_MACH_NEC_MCR = {{ 181 PLATID_WILD, 182 PLATID_MACH_NEC_MCR 183 }}; 184 platid_t platid_mask_MACH_NEC_MCR_3XX = {{ 185 PLATID_CPU_MIPS_VR_41XX, 186 PLATID_MACH_NEC_MCR_3XX 187 }}; 188 platid_t platid_mask_MACH_NEC_MCR_300 = {{ 189 PLATID_CPU_MIPS_VR_4111, 190 PLATID_MACH_NEC_MCR_300 191 }}; 192 platid_t platid_mask_MACH_NEC_MCR_320 = {{ 193 PLATID_CPU_MIPS_VR_4121, 194 PLATID_MACH_NEC_MCR_320 195 }}; 196 platid_t platid_mask_MACH_NEC_MCR_FORDOCOMO = {{ 197 PLATID_CPU_MIPS_VR_4111, 198 PLATID_MACH_NEC_MCR_FORDOCOMO 199 }}; 200 platid_t platid_mask_MACH_NEC_MCR_MPRO700 = {{ 201 PLATID_CPU_MIPS_VR_4102, 202 PLATID_MACH_NEC_MCR_MPRO700 203 }}; 204 platid_t platid_mask_MACH_NEC_MCR_330 = {{ 205 PLATID_CPU_MIPS_VR_4121, 206 PLATID_MACH_NEC_MCR_330 207 }}; 208 platid_t platid_mask_MACH_NEC_MCR_5XX = {{ 209 PLATID_CPU_MIPS_VR_41XX, 210 PLATID_MACH_NEC_MCR_5XX 211 }}; 212 platid_t platid_mask_MACH_NEC_MCR_500 = {{ 213 PLATID_CPU_MIPS_VR_4111, 214 PLATID_MACH_NEC_MCR_500 215 }}; 216 platid_t platid_mask_MACH_NEC_MCR_510 = {{ 217 PLATID_CPU_MIPS_VR_4121, 218 PLATID_MACH_NEC_MCR_510 219 }}; 220 platid_t platid_mask_MACH_NEC_MCR_520 = {{ 221 PLATID_CPU_MIPS_VR_4121, 222 PLATID_MACH_NEC_MCR_520 223 }}; 224 platid_t platid_mask_MACH_NEC_MCR_520A = {{ 225 PLATID_CPU_MIPS_VR_4121, 226 PLATID_MACH_NEC_MCR_520A 227 }}; 228 platid_t platid_mask_MACH_NEC_MCR_500A = {{ 229 PLATID_CPU_MIPS_VR_4111, 230 PLATID_MACH_NEC_MCR_500A 231 }}; 232 platid_t platid_mask_MACH_NEC_MCR_530 = {{ 233 PLATID_CPU_MIPS_VR_4121, 234 PLATID_MACH_NEC_MCR_530 235 }}; 236 platid_t platid_mask_MACH_NEC_MCR_430 = {{ 237 PLATID_CPU_MIPS_VR_4121, 238 PLATID_MACH_NEC_MCR_430 239 }}; 240 platid_t platid_mask_MACH_NEC_MCR_530A = {{ 241 PLATID_CPU_MIPS_VR_4121, 242 PLATID_MACH_NEC_MCR_530A 243 }}; 244 platid_t platid_mask_MACH_NEC_MCR_SIGMARION = {{ 245 PLATID_CPU_MIPS_VR_4121, 246 PLATID_MACH_NEC_MCR_SIGMARION 247 }}; 248 platid_t platid_mask_MACH_NEC_MCR_550 = {{ 249 PLATID_CPU_MIPS_VR_4121, 250 PLATID_MACH_NEC_MCR_550 251 }}; 252 platid_t platid_mask_MACH_NEC_MCR_450 = {{ 253 PLATID_CPU_MIPS_VR_4121, 254 PLATID_MACH_NEC_MCR_450 255 }}; 256 platid_t platid_mask_MACH_NEC_MCR_SIGMARION2 = {{ 257 PLATID_CPU_MIPS_VR_4131, 258 PLATID_MACH_NEC_MCR_SIGMARION2 259 }}; 260 platid_t platid_mask_MACH_NEC_MCR_7XX = {{ 261 PLATID_CPU_MIPS_VR_41XX, 262 PLATID_MACH_NEC_MCR_7XX 263 }}; 264 platid_t platid_mask_MACH_NEC_MCR_700 = {{ 265 PLATID_CPU_MIPS_VR_4121, 266 PLATID_MACH_NEC_MCR_700 267 }}; 268 platid_t platid_mask_MACH_NEC_MCR_700A = {{ 269 PLATID_CPU_MIPS_VR_4121, 270 PLATID_MACH_NEC_MCR_700A 271 }}; 272 platid_t platid_mask_MACH_NEC_MCR_730 = {{ 273 PLATID_CPU_MIPS_VR_4121, 274 PLATID_MACH_NEC_MCR_730 275 }}; 276 platid_t platid_mask_MACH_NEC_MCR_730A = {{ 277 PLATID_CPU_MIPS_VR_4121, 278 PLATID_MACH_NEC_MCR_730A 279 }}; 280 #endif /* hpcmips */ 281 #ifdef hpcmips 282 platid_t platid_mask_MACH_EVEREX = {{ 283 PLATID_WILD, 284 PLATID_MACH_EVEREX 285 }}; 286 platid_t platid_mask_MACH_EVEREX_FREESTYLE = {{ 287 PLATID_WILD, 288 PLATID_MACH_EVEREX_FREESTYLE 289 }}; 290 platid_t platid_mask_MACH_EVEREX_FREESTYLE_AXX = {{ 291 PLATID_CPU_MIPS_VR_41XX, 292 PLATID_MACH_EVEREX_FREESTYLE_AXX 293 }}; 294 platid_t platid_mask_MACH_EVEREX_FREESTYLE_A10 = {{ 295 PLATID_CPU_MIPS_VR_4102, 296 PLATID_MACH_EVEREX_FREESTYLE_A10 297 }}; 298 platid_t platid_mask_MACH_EVEREX_FREESTYLE_A15 = {{ 299 PLATID_CPU_MIPS_VR_4111, 300 PLATID_MACH_EVEREX_FREESTYLE_A15 301 }}; 302 platid_t platid_mask_MACH_EVEREX_FREESTYLE_A20 = {{ 303 PLATID_CPU_MIPS_VR_4111, 304 PLATID_MACH_EVEREX_FREESTYLE_A20 305 }}; 306 #endif /* hpcmips */ 307 platid_t platid_mask_MACH_CASIO = {{ 308 PLATID_WILD, 309 PLATID_MACH_CASIO 310 }}; 311 #ifdef hpcmips 312 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE = {{ 313 PLATID_WILD, 314 PLATID_MACH_CASIO_CASSIOPEIAE 315 }}; 316 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_EXX = {{ 317 PLATID_WILD, 318 PLATID_MACH_CASIO_CASSIOPEIAE_EXX 319 }}; 320 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E10 = {{ 321 PLATID_CPU_MIPS_VR_4111, 322 PLATID_MACH_CASIO_CASSIOPEIAE_E10 323 }}; 324 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E11 = {{ 325 PLATID_CPU_MIPS_VR_4111, 326 PLATID_MACH_CASIO_CASSIOPEIAE_E11 327 }}; 328 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E15 = {{ 329 PLATID_CPU_MIPS_VR_4111, 330 PLATID_MACH_CASIO_CASSIOPEIAE_E15 331 }}; 332 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E55 = {{ 333 PLATID_CPU_MIPS_VR_4111, 334 PLATID_MACH_CASIO_CASSIOPEIAE_E55 335 }}; 336 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_FORDOCOMO = {{ 337 PLATID_CPU_MIPS_VR_4111, 338 PLATID_MACH_CASIO_CASSIOPEIAE_FORDOCOMO 339 }}; 340 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E65 = {{ 341 PLATID_CPU_MIPS_VR_4111, 342 PLATID_MACH_CASIO_CASSIOPEIAE_E65 343 }}; 344 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_EXXX = {{ 345 PLATID_WILD, 346 PLATID_MACH_CASIO_CASSIOPEIAE_EXXX 347 }}; 348 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E100 = {{ 349 PLATID_CPU_MIPS_VR_4121, 350 PLATID_MACH_CASIO_CASSIOPEIAE_E100 351 }}; 352 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E105 = {{ 353 PLATID_CPU_MIPS_VR_4121, 354 PLATID_MACH_CASIO_CASSIOPEIAE_E105 355 }}; 356 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E500 = {{ 357 PLATID_CPU_MIPS_VR_4121, 358 PLATID_MACH_CASIO_CASSIOPEIAE_E500 359 }}; 360 platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E507 = {{ 361 PLATID_CPU_MIPS_VR_4121, 362 PLATID_MACH_CASIO_CASSIOPEIAE_E507 363 }}; 364 platid_t platid_mask_MACH_CASIO_POCKETPOSTPET = {{ 365 PLATID_WILD, 366 PLATID_MACH_CASIO_POCKETPOSTPET 367 }}; 368 platid_t platid_mask_MACH_CASIO_POCKETPOSTPET_POCKETPOSTPET = {{ 369 PLATID_CPU_MIPS_VR_4121, 370 PLATID_MACH_CASIO_POCKETPOSTPET_POCKETPOSTPET 371 }}; 372 #endif /* hpcmips */ 373 #ifdef hpcsh 374 platid_t platid_mask_MACH_CASIO_CASSIOPEIAA = {{ 375 PLATID_WILD, 376 PLATID_MACH_CASIO_CASSIOPEIAA 377 }}; 378 platid_t platid_mask_MACH_CASIO_CASSIOPEIAA_AXX = {{ 379 PLATID_WILD, 380 PLATID_MACH_CASIO_CASSIOPEIAA_AXX 381 }}; 382 platid_t platid_mask_MACH_CASIO_CASSIOPEIAA_A55V = {{ 383 PLATID_CPU_SH_3_7709, 384 PLATID_MACH_CASIO_CASSIOPEIAA_A55V 385 }}; 386 #endif /* hpcsh */ 387 #ifdef hpcmips 388 platid_t platid_mask_MACH_SHARP = {{ 389 PLATID_WILD, 390 PLATID_MACH_SHARP 391 }}; 392 platid_t platid_mask_MACH_SHARP_TRIPAD = {{ 393 PLATID_WILD, 394 PLATID_MACH_SHARP_TRIPAD 395 }}; 396 platid_t platid_mask_MACH_SHARP_TRIPAD_PV = {{ 397 PLATID_WILD, 398 PLATID_MACH_SHARP_TRIPAD_PV 399 }}; 400 platid_t platid_mask_MACH_SHARP_TRIPAD_PV6000 = {{ 401 PLATID_CPU_MIPS_VR_4111, 402 PLATID_MACH_SHARP_TRIPAD_PV6000 403 }}; 404 platid_t platid_mask_MACH_SHARP_TELIOS = {{ 405 PLATID_WILD, 406 PLATID_MACH_SHARP_TELIOS 407 }}; 408 platid_t platid_mask_MACH_SHARP_TELIOS_HC = {{ 409 PLATID_WILD, 410 PLATID_MACH_SHARP_TELIOS_HC 411 }}; 412 platid_t platid_mask_MACH_SHARP_TELIOS_HCAJ1 = {{ 413 PLATID_CPU_MIPS_TX_3922, 414 PLATID_MACH_SHARP_TELIOS_HCAJ1 415 }}; 416 platid_t platid_mask_MACH_SHARP_TELIOS_HCVJ1C_JP = {{ 417 PLATID_CPU_MIPS_TX_3922, 418 PLATID_MACH_SHARP_TELIOS_HCVJ1C_JP 419 }}; 420 platid_t platid_mask_MACH_SHARP_MOBILON = {{ 421 PLATID_WILD, 422 PLATID_MACH_SHARP_MOBILON 423 }}; 424 platid_t platid_mask_MACH_SHARP_MOBILON_HC = {{ 425 PLATID_WILD, 426 PLATID_MACH_SHARP_MOBILON_HC 427 }}; 428 platid_t platid_mask_MACH_SHARP_MOBILON_HC4100 = {{ 429 PLATID_CPU_MIPS_TX_3912, 430 PLATID_MACH_SHARP_MOBILON_HC4100 431 }}; 432 platid_t platid_mask_MACH_SHARP_MOBILON_HC4500 = {{ 433 PLATID_CPU_MIPS_TX_3912, 434 PLATID_MACH_SHARP_MOBILON_HC4500 435 }}; 436 platid_t platid_mask_MACH_SHARP_MOBILON_HC1200 = {{ 437 PLATID_CPU_MIPS_TX_3912, 438 PLATID_MACH_SHARP_MOBILON_HC1200 439 }}; 440 #endif /* hpcmips */ 441 #ifdef hpcmips 442 platid_t platid_mask_MACH_FUJITSU = {{ 443 PLATID_WILD, 444 PLATID_MACH_FUJITSU 445 }}; 446 platid_t platid_mask_MACH_FUJITSU_INTERTOP = {{ 447 PLATID_WILD, 448 PLATID_MACH_FUJITSU_INTERTOP 449 }}; 450 platid_t platid_mask_MACH_FUJITSU_INTERTOP_ITXXX = {{ 451 PLATID_WILD, 452 PLATID_MACH_FUJITSU_INTERTOP_ITXXX 453 }}; 454 platid_t platid_mask_MACH_FUJITSU_INTERTOP_IT300 = {{ 455 PLATID_CPU_MIPS_VR_4121, 456 PLATID_MACH_FUJITSU_INTERTOP_IT300 457 }}; 458 platid_t platid_mask_MACH_FUJITSU_INTERTOP_IT310 = {{ 459 PLATID_CPU_MIPS_VR_4121, 460 PLATID_MACH_FUJITSU_INTERTOP_IT310 461 }}; 462 platid_t platid_mask_MACH_FUJITSU_PENCENTRA = {{ 463 PLATID_WILD, 464 PLATID_MACH_FUJITSU_PENCENTRA 465 }}; 466 platid_t platid_mask_MACH_FUJITSU_PENCENTRA_130 = {{ 467 PLATID_CPU_MIPS_VR_4121, 468 PLATID_MACH_FUJITSU_PENCENTRA_130 469 }}; 470 platid_t platid_mask_MACH_FUJITSU_PENCENTRA_130TM = {{ 471 PLATID_CPU_MIPS_VR_4121, 472 PLATID_MACH_FUJITSU_PENCENTRA_130TM 473 }}; 474 platid_t platid_mask_MACH_FUJITSU_PENCENTRA_130RF = {{ 475 PLATID_CPU_MIPS_VR_4121, 476 PLATID_MACH_FUJITSU_PENCENTRA_130RF 477 }}; 478 platid_t platid_mask_MACH_FUJITSU_PENCENTRA_200 = {{ 479 PLATID_CPU_MIPS_TX_3922, 480 PLATID_MACH_FUJITSU_PENCENTRA_200 481 }}; 482 platid_t platid_mask_MACH_FUJITSU_PENCENTRA_200CTM = {{ 483 PLATID_CPU_MIPS_TX_3922, 484 PLATID_MACH_FUJITSU_PENCENTRA_200CTM 485 }}; 486 platid_t platid_mask_MACH_FUJITSU_PENCENTRA_200CRF = {{ 487 PLATID_CPU_MIPS_TX_3922, 488 PLATID_MACH_FUJITSU_PENCENTRA_200CRF 489 }}; 490 #endif /* hpcmips */ 491 #ifdef hpcmips 492 platid_t platid_mask_MACH_PHILIPS = {{ 493 PLATID_WILD, 494 PLATID_MACH_PHILIPS 495 }}; 496 platid_t platid_mask_MACH_PHILIPS_NINO = {{ 497 PLATID_WILD, 498 PLATID_MACH_PHILIPS_NINO 499 }}; 500 platid_t platid_mask_MACH_PHILIPS_NINO_3XX = {{ 501 PLATID_WILD, 502 PLATID_MACH_PHILIPS_NINO_3XX 503 }}; 504 platid_t platid_mask_MACH_PHILIPS_NINO_312 = {{ 505 PLATID_CPU_MIPS_TX_3912, 506 PLATID_MACH_PHILIPS_NINO_312 507 }}; 508 #endif /* hpcmips */ 509 platid_t platid_mask_MACH_COMPAQ = {{ 510 PLATID_WILD, 511 PLATID_MACH_COMPAQ 512 }}; 513 #ifdef hpcmips 514 platid_t platid_mask_MACH_COMPAQ_C = {{ 515 PLATID_WILD, 516 PLATID_MACH_COMPAQ_C 517 }}; 518 platid_t platid_mask_MACH_COMPAQ_C_8XX = {{ 519 PLATID_WILD, 520 PLATID_MACH_COMPAQ_C_8XX 521 }}; 522 platid_t platid_mask_MACH_COMPAQ_C_810 = {{ 523 PLATID_CPU_MIPS_TX_3912, 524 PLATID_MACH_COMPAQ_C_810 525 }}; 526 platid_t platid_mask_MACH_COMPAQ_C_201X = {{ 527 PLATID_WILD, 528 PLATID_MACH_COMPAQ_C_201X 529 }}; 530 platid_t platid_mask_MACH_COMPAQ_C_2010 = {{ 531 PLATID_CPU_MIPS_TX_3912, 532 PLATID_MACH_COMPAQ_C_2010 533 }}; 534 platid_t platid_mask_MACH_COMPAQ_C_2015 = {{ 535 PLATID_CPU_MIPS_TX_3912, 536 PLATID_MACH_COMPAQ_C_2015 537 }}; 538 platid_t platid_mask_MACH_COMPAQ_AERO = {{ 539 PLATID_WILD, 540 PLATID_MACH_COMPAQ_AERO 541 }}; 542 platid_t platid_mask_MACH_COMPAQ_AERO_15XX = {{ 543 PLATID_WILD, 544 PLATID_MACH_COMPAQ_AERO_15XX 545 }}; 546 platid_t platid_mask_MACH_COMPAQ_AERO_1530 = {{ 547 PLATID_CPU_MIPS_VR_4111, 548 PLATID_MACH_COMPAQ_AERO_1530 549 }}; 550 platid_t platid_mask_MACH_COMPAQ_AERO_21XX = {{ 551 PLATID_WILD, 552 PLATID_MACH_COMPAQ_AERO_21XX 553 }}; 554 platid_t platid_mask_MACH_COMPAQ_AERO_2110 = {{ 555 PLATID_CPU_MIPS_VR_4111, 556 PLATID_MACH_COMPAQ_AERO_2110 557 }}; 558 platid_t platid_mask_MACH_COMPAQ_AERO_2130 = {{ 559 PLATID_CPU_MIPS_VR_4111, 560 PLATID_MACH_COMPAQ_AERO_2130 561 }}; 562 platid_t platid_mask_MACH_COMPAQ_AERO_2140 = {{ 563 PLATID_CPU_MIPS_VR_4111, 564 PLATID_MACH_COMPAQ_AERO_2140 565 }}; 566 platid_t platid_mask_MACH_COMPAQ_PRESARIO = {{ 567 PLATID_WILD, 568 PLATID_MACH_COMPAQ_PRESARIO 569 }}; 570 platid_t platid_mask_MACH_COMPAQ_PRESARIO_21X = {{ 571 PLATID_WILD, 572 PLATID_MACH_COMPAQ_PRESARIO_21X 573 }}; 574 platid_t platid_mask_MACH_COMPAQ_PRESARIO_213 = {{ 575 PLATID_CPU_MIPS_VR_4111, 576 PLATID_MACH_COMPAQ_PRESARIO_213 577 }}; 578 #endif /* hpcmips */ 579 #ifdef hpcarm 580 platid_t platid_mask_MACH_COMPAQ_IPAQ = {{ 581 PLATID_WILD, 582 PLATID_MACH_COMPAQ_IPAQ 583 }}; 584 platid_t platid_mask_MACH_COMPAQ_IPAQ_H31XX = {{ 585 PLATID_WILD, 586 PLATID_MACH_COMPAQ_IPAQ_H31XX 587 }}; 588 platid_t platid_mask_MACH_COMPAQ_IPAQ_H3100 = {{ 589 PLATID_CPU_ARM_STRONGARM_SA1110, 590 PLATID_MACH_COMPAQ_IPAQ_H3100 591 }}; 592 platid_t platid_mask_MACH_COMPAQ_IPAQ_H36XX = {{ 593 PLATID_WILD, 594 PLATID_MACH_COMPAQ_IPAQ_H36XX 595 }}; 596 platid_t platid_mask_MACH_COMPAQ_IPAQ_H3600 = {{ 597 PLATID_CPU_ARM_STRONGARM_SA1110, 598 PLATID_MACH_COMPAQ_IPAQ_H3600 599 }}; 600 platid_t platid_mask_MACH_COMPAQ_IPAQ_H3660 = {{ 601 PLATID_CPU_ARM_STRONGARM_SA1110, 602 PLATID_MACH_COMPAQ_IPAQ_H3660 603 }}; 604 #endif /* hpcarm */ 605 #ifdef hpcmips 606 platid_t platid_mask_MACH_VICTOR = {{ 607 PLATID_WILD, 608 PLATID_MACH_VICTOR 609 }}; 610 platid_t platid_mask_MACH_VICTOR_INTERLINK = {{ 611 PLATID_WILD, 612 PLATID_MACH_VICTOR_INTERLINK 613 }}; 614 platid_t platid_mask_MACH_VICTOR_INTERLINK_MP = {{ 615 PLATID_WILD, 616 PLATID_MACH_VICTOR_INTERLINK_MP 617 }}; 618 platid_t platid_mask_MACH_VICTOR_INTERLINK_MPC101 = {{ 619 PLATID_CPU_MIPS_TX_3922, 620 PLATID_MACH_VICTOR_INTERLINK_MPC101 621 }}; 622 platid_t platid_mask_MACH_VICTOR_INTERLINK_MPC303 = {{ 623 PLATID_CPU_MIPS_VR_4122, 624 PLATID_MACH_VICTOR_INTERLINK_MPC303 625 }}; 626 platid_t platid_mask_MACH_VICTOR_INTERLINK_MPC304 = {{ 627 PLATID_CPU_MIPS_VR_4122, 628 PLATID_MACH_VICTOR_INTERLINK_MPC304 629 }}; 630 #endif /* hpcmips */ 631 #ifdef hpcmips 632 platid_t platid_mask_MACH_IBM = {{ 633 PLATID_WILD, 634 PLATID_MACH_IBM 635 }}; 636 platid_t platid_mask_MACH_IBM_WORKPAD = {{ 637 PLATID_WILD, 638 PLATID_MACH_IBM_WORKPAD 639 }}; 640 platid_t platid_mask_MACH_IBM_WORKPAD_Z50 = {{ 641 PLATID_WILD, 642 PLATID_MACH_IBM_WORKPAD_Z50 643 }}; 644 platid_t platid_mask_MACH_IBM_WORKPAD_26011AU = {{ 645 PLATID_CPU_MIPS_VR_4121, 646 PLATID_MACH_IBM_WORKPAD_26011AU 647 }}; 648 #endif /* hpcmips */ 649 #ifdef hpcmips 650 platid_t platid_mask_MACH_VADEM = {{ 651 PLATID_WILD, 652 PLATID_MACH_VADEM 653 }}; 654 platid_t platid_mask_MACH_VADEM_CLIO = {{ 655 PLATID_WILD, 656 PLATID_MACH_VADEM_CLIO 657 }}; 658 platid_t platid_mask_MACH_VADEM_CLIO_C = {{ 659 PLATID_WILD, 660 PLATID_MACH_VADEM_CLIO_C 661 }}; 662 platid_t platid_mask_MACH_VADEM_CLIO_C1000 = {{ 663 PLATID_CPU_MIPS_VR_4111, 664 PLATID_MACH_VADEM_CLIO_C1000 665 }}; 666 platid_t platid_mask_MACH_VADEM_CLIO_C1050 = {{ 667 PLATID_CPU_MIPS_VR_4121, 668 PLATID_MACH_VADEM_CLIO_C1050 669 }}; 670 #endif /* hpcmips */ 671 platid_t platid_mask_MACH_HP = {{ 672 PLATID_WILD, 673 PLATID_MACH_HP 674 }}; 675 #ifdef hpcsh 676 platid_t platid_mask_MACH_HP_LX = {{ 677 PLATID_WILD, 678 PLATID_MACH_HP_LX 679 }}; 680 platid_t platid_mask_MACH_HP_LX_620 = {{ 681 PLATID_CPU_SH_3_7709, 682 PLATID_MACH_HP_LX_620 683 }}; 684 platid_t platid_mask_MACH_HP_LX_620JP = {{ 685 PLATID_CPU_SH_3_7709, 686 PLATID_MACH_HP_LX_620JP 687 }}; 688 #endif /* hpcsh */ 689 platid_t platid_mask_MACH_HP_JORNADA = {{ 690 PLATID_WILD, 691 PLATID_MACH_HP_JORNADA 692 }}; 693 #ifdef hpcsh 694 platid_t platid_mask_MACH_HP_JORNADA_6XX = {{ 695 PLATID_WILD, 696 PLATID_MACH_HP_JORNADA_6XX 697 }}; 698 platid_t platid_mask_MACH_HP_JORNADA_680 = {{ 699 PLATID_CPU_SH_3_7709A, 700 PLATID_MACH_HP_JORNADA_680 701 }}; 702 platid_t platid_mask_MACH_HP_JORNADA_680JP = {{ 703 PLATID_CPU_SH_3_7709A, 704 PLATID_MACH_HP_JORNADA_680JP 705 }}; 706 platid_t platid_mask_MACH_HP_JORNADA_680HU = {{ 707 PLATID_CPU_SH_3_7709A, 708 PLATID_MACH_HP_JORNADA_680HU 709 }}; 710 platid_t platid_mask_MACH_HP_JORNADA_680DE = {{ 711 PLATID_CPU_SH_3_7709A, 712 PLATID_MACH_HP_JORNADA_680DE 713 }}; 714 platid_t platid_mask_MACH_HP_JORNADA_690 = {{ 715 PLATID_CPU_SH_3_7709A, 716 PLATID_MACH_HP_JORNADA_690 717 }}; 718 platid_t platid_mask_MACH_HP_JORNADA_690JP = {{ 719 PLATID_CPU_SH_3_7709A, 720 PLATID_MACH_HP_JORNADA_690JP 721 }}; 722 platid_t platid_mask_MACH_HP_JORNADA_690HU = {{ 723 PLATID_CPU_SH_3_7709A, 724 PLATID_MACH_HP_JORNADA_690HU 725 }}; 726 platid_t platid_mask_MACH_HP_JORNADA_690DE = {{ 727 PLATID_CPU_SH_3_7709A, 728 PLATID_MACH_HP_JORNADA_690DE 729 }}; 730 #endif /* hpcsh */ 731 #ifdef hpcarm 732 platid_t platid_mask_MACH_HP_JORNADA_7XX = {{ 733 PLATID_WILD, 734 PLATID_MACH_HP_JORNADA_7XX 735 }}; 736 platid_t platid_mask_MACH_HP_JORNADA_720 = {{ 737 PLATID_CPU_ARM_STRONGARM_SA1110, 738 PLATID_MACH_HP_JORNADA_720 739 }}; 740 platid_t platid_mask_MACH_HP_JORNADA_720JP = {{ 741 PLATID_CPU_ARM_STRONGARM_SA1110, 742 PLATID_MACH_HP_JORNADA_720JP 743 }}; 744 platid_t platid_mask_MACH_HP_JORNADA_8XX = {{ 745 PLATID_WILD, 746 PLATID_MACH_HP_JORNADA_8XX 747 }}; 748 platid_t platid_mask_MACH_HP_JORNADA_820 = {{ 749 PLATID_CPU_ARM_STRONGARM_SA1100, 750 PLATID_MACH_HP_JORNADA_820 751 }}; 752 platid_t platid_mask_MACH_HP_JORNADA_820JP = {{ 753 PLATID_CPU_ARM_STRONGARM_SA1100, 754 PLATID_MACH_HP_JORNADA_820JP 755 }}; 756 #endif /* hpcarm */ 757 #ifdef hpcsh 758 platid_t platid_mask_MACH_HITACHI = {{ 759 PLATID_WILD, 760 PLATID_MACH_HITACHI 761 }}; 762 platid_t platid_mask_MACH_HITACHI_PERSONA = {{ 763 PLATID_WILD, 764 PLATID_MACH_HITACHI_PERSONA 765 }}; 766 platid_t platid_mask_MACH_HITACHI_PERSONA_HPW230JC = {{ 767 PLATID_CPU_SH_3_7709, 768 PLATID_MACH_HITACHI_PERSONA_HPW230JC 769 }}; 770 platid_t platid_mask_MACH_HITACHI_PERSONA_HPW50PAD = {{ 771 PLATID_CPU_SH_3_7709, 772 PLATID_MACH_HITACHI_PERSONA_HPW50PAD 773 }}; 774 platid_t platid_mask_MACH_HITACHI_PERSONA_HPW650PA = {{ 775 PLATID_CPU_SH_4_7750, 776 PLATID_MACH_HITACHI_PERSONA_HPW650PA 777 }}; 778 #endif /* hpcsh */ 779 #ifdef hpcsh 780 platid_t platid_mask_MACH_LGE = {{ 781 PLATID_WILD, 782 PLATID_MACH_LGE 783 }}; 784 platid_t platid_mask_MACH_LGE_PHENOM = {{ 785 PLATID_WILD, 786 PLATID_MACH_LGE_PHENOM 787 }}; 788 platid_t platid_mask_MACH_LGE_PHENOM_H220C = {{ 789 PLATID_CPU_SH_3_7709, 790 PLATID_MACH_LGE_PHENOM_H220C 791 }}; 792 #endif /* hpcsh */ 793 #ifdef hpcmips 794 platid_t platid_mask_MACH_LASER5 = {{ 795 PLATID_WILD, 796 PLATID_MACH_LASER5 797 }}; 798 platid_t platid_mask_MACH_LASER5_L = {{ 799 PLATID_WILD, 800 PLATID_MACH_LASER5_L 801 }}; 802 platid_t platid_mask_MACH_LASER5_L_CARD = {{ 803 PLATID_CPU_MIPS_VR_4181, 804 PLATID_MACH_LASER5_L_CARD 805 }}; 806 platid_t platid_mask_MACH_LASER5_L_BOARD = {{ 807 PLATID_CPU_MIPS_VR_4122, 808 PLATID_MACH_LASER5_L_BOARD 809 }}; 810 #endif /* hpcmips */ 811 #ifdef hpcmips 812 platid_t platid_mask_MACH_AGENDA = {{ 813 PLATID_WILD, 814 PLATID_MACH_AGENDA 815 }}; 816 platid_t platid_mask_MACH_AGENDA_VR = {{ 817 PLATID_WILD, 818 PLATID_MACH_AGENDA_VR 819 }}; 820 platid_t platid_mask_MACH_AGENDA_VR_VR3 = {{ 821 PLATID_CPU_MIPS_VR_4181, 822 PLATID_MACH_AGENDA_VR_VR3 823 }}; 824 #endif /* hpcmips */ 825