1 /* -*-C++-*- $NetBSD: mips_arch.h,v 1.2 2001/04/24 19:28:00 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _HPCBOOT_MIPS_ARCH_H_ 40 #define _HPCBOOT_MIPS_ARCH_H_ 41 42 #include <hpcboot.h> 43 #include <arch.h> 44 45 class Console; 46 47 class MIPSArchitecture : public Architecture { 48 protected: 49 typedef void(*boot_func_t)(struct BootArgs *, struct PageTag *); 50 51 int _kmode; 52 boot_func_t _boot_func; 53 54 public: 55 MIPSArchitecture(Console *&, MemoryManager *&); 56 virtual ~MIPSArchitecture(void); 57 58 virtual BOOL init(void); 59 BOOL setupLoader(void); 60 virtual void systemInfo(void); 61 virtual void cacheFlush(void) = 0; 62 void jump(paddr_t info, paddr_t pvce); 63 }; 64 65 #define DI() \ 66 __asm(".set noreorder;" \ 67 "nop;" \ 68 "mtc0 zero, $12;" \ 69 "nop;nop;nop;" /* CP0 hazard for R4000 */ \ 70 ".set reorder") 71 72 #define GET_SR(x) \ 73 __asm(".set noreorder;" \ 74 "mfc0 t0, $12;" \ 75 "sw t0,(%0);" \ 76 ".set reorder", &(x)); 77 78 #define SET_SR(x) \ 79 __asm(".set noreorder;" \ 80 "lw t0,(%0);" \ 81 "nop;" \ 82 "mtc0 t0, $12;" \ 83 "nop;nop;nop;" /* CP0 hazard for R4000 */ \ 84 ".set reorder", &(x)); 85 86 /* 87 * 2nd-bootloader. make sure that PIC and its size is lower than page size. 88 * and can't call subroutine. 89 * naked funciton can't use stack. if you want to use, remove its declare. 90 * interrupts are disabled. but if access kuseg,(should not occur) 91 * it causes TLB exception and then Windows CE enable interrupts again. 92 */ 93 #define BOOT_FUNC_(x) \ 94 __declspec(naked) void \ 95 x##::boot_func(struct BootArgs *bi, struct PageTag *p) \ 96 { \ 97 /* disable interrupt */ \ 98 DI(); \ 99 /* set kernel image */ \ 100 __asm(".set noreorder;" \ 101 "move t6, a1;" /* p */ \ 102 "li t1, 0xffffffff;" \ 103 "page_start:" \ 104 "beq t6, t1, page_end;" \ 105 "move t7, t6;" \ 106 "lw t6, 0(t7);" /* p = next */ \ 107 "lw t0, 4(t7);" /* src */ \ 108 "lw t4, 8(t7);" /* dst */ \ 109 "lw t2, 12(t7);" /* sz */ \ 110 "beq t0, t1, page_clear;" \ 111 "addu t5, t4, t2;" /* dst + sz */ \ 112 "page_copy:" \ 113 "lw t3, 0(t0);" /* bcopy */ \ 114 "sw t3, 0(t4);" \ 115 "addiu t4, t4, 4;" \ 116 "bltu t4, t5, page_copy;" \ 117 "addiu t0, t0, 4;" \ 118 "b page_start;" \ 119 "nop;" \ 120 "page_clear:" \ 121 "sw zero, 0(t4);" /* bzero */ \ 122 "addiu t4, t4, 4;" \ 123 "bltu t4, t5, page_clear;" \ 124 "nop;" \ 125 "b page_start;" \ 126 "nop;" \ 127 "page_end:" \ 128 "nop;" \ 129 ".set reorder"); \ 130 \ 131 /* Cache flush for kernel */ \ 132 MIPS_##x##_CACHE_FLUSH(); \ 133 \ 134 /* jump to kernel entry */ \ 135 __asm(".set noreorder;" \ 136 "move t0, a0;" \ 137 "lw t1, 0(t0);" \ 138 "lw a0, 4(t0);" \ 139 "lw a1, 8(t0);" \ 140 "lw a2, 12(t0);" \ 141 "jr t1;" \ 142 "nop;" \ 143 ".set reorder"); \ 144 } 145 146 #endif // _HPCBOOT_MIPS_ARCH_H_ 147