1 /* -*-C++-*- $NetBSD: mips_vr41.h,v 1.4 2008/04/28 20:23:20 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <hpcboot.h> 33 #include <mips/mips_arch.h> 34 35 class VR41XX : public MIPSArchitecture { 36 private: 37 38 public: 39 VR41XX(Console *&, MemoryManager *&); 40 ~VR41XX(void); 41 42 virtual BOOL init(void); 43 virtual void systemInfo(void); 44 virtual void cacheFlush(void); 45 static void boot_func(struct BootArgs *, struct PageTag *); 46 }; 47 48 #define MIPS_VR41XX_CACHE_FLUSH() \ 49 __asm( \ 50 ".set noreorder;" \ 51 /* Flush I-cache */ \ 52 "li t0, 0x80000000;" \ 53 "addu t1, t0, 1024*128;" \ 54 "subu t1, t1, 128;" \ 55 "1:" \ 56 "cache 0, 0(t0);" \ 57 "cache 0, 16(t0);" \ 58 "cache 0, 32(t0);" \ 59 "cache 0, 48(t0);" \ 60 "cache 0, 64(t0);" \ 61 "cache 0, 80(t0);" \ 62 "cache 0, 96(t0);" \ 63 "cache 0, 112(t0);" \ 64 "bne t0, t1, 1b;" \ 65 "addu t0, t0, 128;" \ 66 \ 67 /* Flush D-cache */ \ 68 "li t0, 0x80000000;" \ 69 "addu t1, t0, 1024*128;" \ 70 "subu t1, t1, 128;" \ 71 "2:" \ 72 "cache 1, 0(t0);" \ 73 "cache 1, 16(t0);" \ 74 "cache 1, 32(t0);" \ 75 "cache 1, 48(t0);" \ 76 "cache 1, 64(t0);" \ 77 "cache 1, 80(t0);" \ 78 "cache 1, 96(t0);" \ 79 "cache 1, 112(t0);" \ 80 "bne t0, t1, 2b;" \ 81 "addu t0, t0, 128;" \ 82 ".set reorder;" \ 83 ) 84