xref: /netbsd/sys/arch/hpc/stand/hpcboot/sh3/cpu/sh3.h (revision bf9ec67e)
1 /* -*-C++-*-	$NetBSD: sh3.h,v 1.1 2002/02/11 17:08:58 uch Exp $	*/
2 
3 /*-
4  * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by UCHIYAMA Yasushi.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *        This product includes software developed by the NetBSD
21  *        Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 #ifndef _HPCBOOT_SH_CPU_SH3_H_
40 #define _HPCBOOT_SH_CPU_SH3_H_
41 #include <sh3/cpu/sh.h>
42 
43 /*
44  * SH3 designed for Windows CE (SH7709, SH7709A) common defines.
45  */
46 #define SH3_TRA			0xffffffd0
47 #define SH3_EXPEVT		0xffffffd4
48 #define SH3_INTEVT		0xffffffd8
49 #define SH3_INTEVT2		0xa4000000
50 
51 /* Windows CE uses 1Kbyte page for SH3, 4Kbyte for SH4 */
52 #define SH3_PAGE_SIZE		0x400
53 #define SH3_PAGE_MASK		(~(SH3_PAGE_SIZE - 1))
54 
55 /*
56  * Cache (Windows CE uses normal-mode.)
57  */
58 #define SH3_CCR			0xffffffec
59 #define SH3_CCR_CE		  0x00000001
60 #define SH3_CCR_WT		  0x00000002
61 #define SH3_CCR_CB		  0x00000004
62 #define SH3_CCR_CF		  0x00000008
63 #define SH3_CCR_RA		  0x00000020
64 #define SH3_CCA			0xf0000000
65 #define SH3_CCD			0xf1000000
66 
67 /*
68  * 4-way set-associative 32-entry (total 128 entries)
69  */
70 #define SH3_MMU_WAY			4
71 #define SH3_MMU_ENTRY			32
72 
73 #define SH3_PTEH			0xfffffff0
74 #define   SH3_PTEH_ASID_MASK		  0x0000000f
75 #define   SH3_PTEH_VPN_MASK		  0xfffffc00
76 #define SH3_MMUCR			0xffffffe0
77 #define   SH3_MMUCR_AT			  0x00000001
78 #define   SH3_MMUCR_IX			  0x00000002
79 #define   SH3_MMUCR_TF			  0x00000004
80 #define   SH3_MMUCR_RC			  0x00000030
81 #define   SH3_MMUCR_SV			  0x00000100
82 
83 /*
84  * memory-mapped TLB
85  */
86 /* Address array */
87 #define SH3_MMUAA			0xf2000000
88 /* address specification */
89 #define   SH3_MMU_VPN_SHIFT		  12
90 #define   SH3_MMU_VPN_MASK		  0x0001f000	/* [16:12] */
91 #define   SH3_MMU_WAY_SHIFT		  8
92 #define   SH3_MMU_WAY_MASK		  0x00000300
93 /* data specification */
94 #define   SH3_MMU_D_VALID		  0x00000100
95 #define   SH3_MMUAA_D_VPN_MASK		  0xfffe0c00	/* [31:17][11:10] */
96 #define   SH3_MMUAA_D_ASID_MASK		  0x0000000f
97 
98 /* Data array */
99 #define SH3_MMUDA			0xf3000000
100 #define   SH3_MMUDA_D_PPN_MASK		  0xfffffc00
101 #define   SH3_MMUDA_D_V			  0x00000100
102 #define   SH3_MMUDA_D_PR_SHIFT		  5
103 #define   SH3_MMUDA_D_PR_MASK		  0x00000060	/* [6:5] */
104 #define   SH3_MMUDA_D_SZ		  0x00000010
105 #define   SH3_MMUDA_D_C			  0x00000008
106 #define   SH3_MMUDA_D_D			  0x00000004
107 #define   SH3_MMUDA_D_SH		  0x00000002
108 
109 
110 #define SH3_MMU_DISABLE()	_reg_write_4(SH3_MMUCR, SH3_MMUCR_TF)
111 
112 /*
113  * Product dependent headers
114  */
115 #include <sh3/cpu/7707.h>
116 #include <sh3/cpu/7709.h>
117 #include <sh3/cpu/7709a.h>
118 
119 #endif // _HPCBOOT_SH_CPU_SH3_H_
120