1 /* -*-C++-*- $NetBSD: sh4.h,v 1.1 2002/02/11 17:08:58 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _HPCBOOT_SH_CPU_SH4_H_ 40 #define _HPCBOOT_SH_CPU_SH4_H_ 41 #include <sh3/cpu/sh.h> 42 43 /* 44 * SH4 designed for Windows CE (SH7750) common defines. 45 */ 46 47 #define SH4_TRA 0xff000020 48 #define SH4_EXPEVT 0xff000024 49 #define SH4_INTEVT 0xff000028 50 51 #define SH4_ICR 0xffd00000 52 #define SH4_IPRA 0xffd00004 53 #define SH4_IPRB 0xffd00008 54 #define SH4_IPRC 0xffd0000c 55 #define SH4_IPRD 0xffd00010 56 57 /* Windows CE uses 1Kbyte page for SH3, 4Kbyte for SH4 */ 58 #define SH4_PAGE_SIZE 0x1000 59 #define SH4_PAGE_MASK (~(SH4_PAGE_SIZE - 1)) 60 61 /* 62 * Cache 63 */ 64 #define SH4_ICACHE_SIZE 8192 65 #define SH4_DCACHE_SIZE 16384 66 #define SH4_CACHE_LINESZ 32 67 68 #define SH4_CCR 0xff00001c 69 #define SH4_CCR_IIX 0x00008000 70 #define SH4_CCR_ICI 0x00000800 71 #define SH4_CCR_ICE 0x00000100 72 #define SH4_CCR_OIX 0x00000080 73 #define SH4_CCR_ORA 0x00000020 74 #define SH4_CCR_OCI 0x00000008 75 #define SH4_CCR_CB 0x00000004 76 #define SH4_CCR_WT 0x00000002 77 #define SH4_CCR_OCE 0x00000001 78 79 #define SH4_QACR0 0xff000038 80 #define SH4_QACR1 0xff00003c 81 #define SH4_QACR_AREA_SHIFT 2 82 #define SH4_QACR_AREA_MASK 0x0000001c 83 84 /* I-cache address/data array */ 85 #define SH4REG_CCIA 0xf0000000 86 /* address specification */ 87 #define CCIA_A 0x00000008 /* associate bit */ 88 #define CCIA_ENTRY_SHIFT 5 /* line size 32B */ 89 #define CCIA_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */ 90 /* data specification */ 91 #define CCIA_V 0x00000001 92 #define CCIA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 93 94 #define SH4REG_CCID 0xf1000000 95 /* address specification */ 96 #define CCID_L_SHIFT 2 97 #define CCID_L_MASK 0x1c /* line-size is 32B */ 98 #define CCID_ENTRY_MASK 0x00001fe0 /* [12:5] 128-entries */ 99 100 /* D-cache address/data array */ 101 #define SH4REG_CCDA 0xf4000000 102 /* address specification */ 103 #define CCDA_A 0x00000008 /* associate bit */ 104 #define CCDA_ENTRY_SHIFT 5 /* line size 32B */ 105 #define CCDA_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */ 106 /* data specification */ 107 #define CCDA_V 0x00000001 108 #define CCDA_U 0x00000002 109 #define CCDA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 110 111 #define SH4REG_CCDD 0xf5000000 112 113 /* 114 * MMU 115 */ 116 #define SH4_PTEH 0xff000000 117 #define SH4_PTEH_ASID_MASK 0x0000000f 118 #define SH4_PTEL 0xff000004 119 #define SH4_PTEL_WT 0x00000001 120 #define SH4_PTEL_SH 0x00000002 121 #define SH4_PTEL_D 0x00000004 122 #define SH4_PTEL_C 0x00000008 123 #define SH4_PTEL_PR_SHIFT 5 124 #define SH4_PTEL_PR_MASK 0x00000060 /* [5:6] */ 125 #define SH4_PTEL_SZ_MASK 0x00000090 /* [4][7] */ 126 #define SH4_PTEL_SZ_1K 0x00000000 127 #define SH4_PTEL_SZ_4K 0x00000010 128 #define SH4_PTEL_SZ_64K 0x00000080 129 #define SH4_PTEL_SZ_1M 0x00000090 130 #define SH4_PTEL_V 0x00000100 131 #define SH4_PTEA 0xff000034 132 #define SH4_PTEA_SA_MASK 0x00000007 133 #define SH4_PTEA_SA_TC 0x00000008 134 #define SH4_TTB 0xff000008 135 #define SH4_TTA 0xff00000c 136 #define SH4_MMUCR 0xff000010 137 #define SH4_MMUCR_AT 0x00000001 138 #define SH4_MMUCR_TI 0x00000004 139 #define SH4_MMUCR_SV 0x00000100 140 #define SH4_MMUCR_SQMD 0x00000200 141 #define SH4_MMUCR_URC_SHIFT 10 142 #define SH4_MMUCR_URC_MASK 0x0000fc00 /* [10:15] */ 143 #define SH4_MMUCR_URB_SHIFT 18 144 #define SH4_MMUCR_URB_MASK 0x00fc0000 /* [18:23] */ 145 #define SH4_MMUCR_LRUI_SHIFT 26 146 #define SH4_MMUCR_LRUT_MASK 0xfc000000 /* [26:31] */ 147 /* 148 * memory-mapped TLB 149 * must be access from P2-area program. 150 * branch to the other area must be maed at least 8 instruction 151 * after access. 152 */ 153 /* ITLB */ 154 #define SH4_ITLB_AA 0xf2000000 155 /* address specification (common for address and data array(0,1)) */ 156 #define SH4_ITLB_E_SHIFT 8 157 #define SH4_ITLB_E_MASK 0x00000300 /* [9:8] */ 158 /* data specification */ 159 /* address-array */ 160 #define SH4_ITLB_AA_ASID_MASK 0x000000ff /* [7:0] */ 161 #define SH4_ITLB_AA_V 0x00000100 162 #define SH4_ITLB_AA_VPN_SHIFT 10 163 #define SH4_ITLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ 164 /* data-array 1 */ 165 #define SH4_ITLB_DA1 0xf3000000 166 #define SH4_ITLB_DA1_SH 0x00000002 167 #define SH4_ITLB_DA1_C 0x00000008 168 #define SH4_ITLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ 169 #define SH4_ITLB_DA1_SZ_1K 0x00000000 170 #define SH4_ITLB_DA1_SZ_4K 0x00000010 171 #define SH4_ITLB_DA1_SZ_64K 0x00000080 172 #define SH4_ITLB_DA1_SZ_1M 0x00000090 173 #define SH4_ITLB_DA1_PR 0x00000040 174 #define SH4_ITLB_DA1_V 0x00000100 175 #define SH4_ITLB_DA1_PPN_SHIFT 11 176 #define SH4_ITLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ 177 /* data-array 2 */ 178 #define SH4_ITLB_DA2 0xf3800000 179 #define SH4_ITLB_DA2_SA_MASK 0x00000003 180 #define SH4_ITLB_DA2_TC 0x00000004 181 182 /* UTLB */ 183 #define SH4_UTLB_AA 0xf6000000 184 /* address specification (common for address and data array(0,1)) */ 185 #define SH4_UTLB_E_SHIFT 8 186 #define SH4_UTLB_E_MASK 0x00003f00 187 /* data specification */ 188 /* address-array */ 189 #define SH4_UTLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ 190 #define SH4_UTLB_AA_D 0x00000200 191 #define SH4_UTLB_AA_V 0x00000100 192 #define SH4_UTLB_AA_ASID_MASK 0x000000ff /* [7:0] */ 193 /* data-array 1 */ 194 #define SH4_UTLB_DA1 0xf7000000 195 #define SH4_UTLB_DA1_WT 0x00000001 196 #define SH4_UTLB_DA1_SH 0x00000002 197 #define SH4_UTLB_DA1_D 0x00000004 198 #define SH4_UTLB_DA1_C 0x00000008 199 #define SH4_UTLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ 200 #define SH4_UTLB_DA1_SZ_1K 0x00000000 201 #define SH4_UTLB_DA1_SZ_4K 0x00000010 202 #define SH4_UTLB_DA1_SZ_64K 0x00000080 203 #define SH4_UTLB_DA1_SZ_1M 0x00000090 204 #define SH4_UTLB_DA1_PR_SHIFT 5 205 #define SH4_UTLB_DA1_PR_MASK 0x00000060 206 #define SH4_UTLB_DA1_V 0x00000100 207 #define SH4_UTLB_DA1_PPN_SHIFT 11 208 #define SH4_UTLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ 209 /* data-array 2 */ 210 #define SH4_UTLB_DA2 0xf7800000 211 #define SH4_UTLB_DA2_SA_MASK 0x00000003 212 #define SH4_UTLB_DA2_TC 0x00000004 213 214 #define SH4_MMU_DISABLE() _reg_write_4(SH4_MMUCR, SH4_MMUCR_TI) 215 216 /* 217 * Product dependent headers 218 */ 219 #include <sh3/cpu/7750.h> 220 221 #endif /* _HPCBOOT_SH_CPU_SH4_H_ */ 222