1 /* $NetBSD: ipaq_lcdreg.h,v 1.1 2001/07/10 18:09:33 ichiro Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Ichiro FUKUHARA(ichiro@ichiro.org). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* size of I/O space */ 40 #define SALCD_NPORTS 11 41 42 /* LCD framebuffer offset */ 43 #define SALCD_12_16_OFFSET 0x20 /* 12BIT - 16BIT */ 44 #define SALCD_8BIT_OFFSET 0x200 /* 8BIT */ 45 46 /* LCD Control Register 0 */ 47 #define SALCD_CR0 0 48 #define CR0_LEN (1<<0) /* LCD enable */ 49 #define CR0_CMS (1<<1) /* color op enable */ 50 #define CR0_SDS (1<<2) /* Single display or Double display */ 51 #define CR0_LDM (1<<3) /* LDD status bit ignore(dont intrrupt) */ 52 #define CR0_BAM (1<<4) /* Base address update does not 53 generate an intrrupt */ 54 #define CR0_ERM (1<<5) /* Bus error generate an intrrupt */ 55 #define CR0_PAS (1<<7) /* Passive / Active and TFT-LCD enable */ 56 #define CR0_BLE (1<<8) /* endian select 0=little */ 57 #define CR0_DPD (1<<9) 58 59 /* LCD Control Register 1 */ 60 #define SALCD_CR1 0x20 61 #define CR1_PPL(pixel) ((pixel) - 16) /* PPL ; Pixel per line 62 - 16 */ 63 #define CR1_HSW(pixel) (((pixel) - 1) << 10) /* HSW ; */ 64 #define CR1_ELW(pixel) (((pixel) - 1) << 16) /* ELW ; */ 65 #define CR1_BLW(pixel) (((pixel) - 1) << 24) /* BLW ; */ 66 67 /* LCD Control Register 2 */ 68 #define SALCD_CR2 0x24 69 #define CR2_LPP(line) ((line) - 1) /* LPP ; Lines per panel */ 70 #define CR2_VSW(line) (((line) -1) << 10) /* VSW ; */ 71 #define CR2_EFW(line) ((line) << 16) /* EFW ; */ 72 #define CR2_BFW(line) ((line) << 24) /* BFW ; */ 73 74 /* LCD Control Register 3 */ 75 #define SALCD_CR3 0x28 76 #define CR3_PCD(div) (((div) - 4)/2) /* PCD ; Pixel clock divisor */ 77 #define CR3_ACB(div) (((div) - 2)/2) /* ACB ; */ 78 #define CR3_API(div) ((div) << 16) /* API ; AC Bias */ 79 #define CR3_VSPL (0 << 20) /* VSP ; Vsync = Low */ 80 #define CR3_VSPH (1 << 20) /* VSP ; Vsync = High */ 81 #define CR3_HSPL (0 << 21) /* HSP ; Hsync = Low */ 82 #define CR3_HSPH (1 << 21) /* HSP ; Hsync = High */ 83 #define CR3_PCP_RE (0 << 22) /* PCP ; Pixel clock Rising-Edge */ 84 #define CR3_PCP_FE (1 << 22) /* PCP ; Pixel clock Falling-Edge */ 85 #define CR3_OEPH (0 << 23) /* OEP ; Output Enable active High */ 86 #define CR3_OEPL (0 << 23) /* OEP ; Output Enable active Low */ 87 88 89 /* DMA Channel 1 Base Address Register */ 90 #define SALCD_BA1 0x10 91 92 /* DMA Channel 1 Current Address Register */ 93 #define SALCD_CA1 0x14 94 95 /* DMA Channel 1 Base Address Register */ 96 #define SALCD_BA2 0x18 97 98 /* DMA Channel 1 Current Address Register */ 99 #define SALCD_CA2 0x1C 100 101 /* LCD Status Register */ 102 #define SALCD_SR 0x04 103 #define SR_LDD (1<<0) 104 #define SR_BAU (1<<1) 105 #define SR_BER (1<<2) 106 #define SR_ABC (1<<3) 107 #define SR_IOL (1<<4) 108 #define SR_IUL (1<<5) 109 #define SR_IOU (1<<6) 110 #define SR_IUU (1<<7) 111 #define SR_OOL (1<<8) 112 #define SR_OUL (1<<9) 113 #define SR_OOU (1<<10) 114 #define SR_OUU (1<<11) 115 116 /* Products Specification */ 117 #define IPAQ_LCCR0 CR0_LEN | CR0_PAS 118 #define IPAQ_LCCR1 CR1_PPL(320) | CR1_HSW(3) | \ 119 CR1_ELW(17) | CR1_BLW(12) 120 #define IPAQ_LCCR2 CR2_LPP(240) | CR2_VSW(3) | \ 121 CR2_EFW(1) | CR2_BFW(10) 122 #define IPAQ_LCCR3 CR3_PCD(36) | CR3_ACB(2) | \ 123 CR3_VSPL | CR3_HSPL | CR3_API(0) 124 125 /* end of ipaq_lcdreg.h */ 126