1/* $NetBSD: locore.S,v 1.12 2010/04/17 13:36:21 nonaka Exp $ */ 2 3/* 4 * Copyright (C) 1994-1997 Mark Brinicombe 5 * Copyright (C) 1994 Brini 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of Brini may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include "opt_cputypes.h" 35#include "assym.h" 36#include <sys/syscall.h> 37#include <sys/errno.h> 38#include <machine/asm.h> 39#include <machine/cpu.h> 40#include <machine/frame.h> 41#include <machine/param.h> 42#if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 43#include <arm/armreg.h> 44#include <arm/arm32/pte.h> 45#include <arm/arm32/pmap.h> /* for PMAP_DOMAIN_KERNEL */ 46#endif 47 48/* What size should this really be ? It is only used by init_arm() */ 49#define INIT_ARM_STACK_SIZE 2048 50 51/* 52 * This is for kvm_mkdb, and should be the address of the beginning 53 * of the kernel text segment (not necessarily the same as kernbase). 54 */ 55 56ENTRY_NP(kernel_text) 57 58ASENTRY_NP(start) 59 /* Put the processer in SVC mode */ 60 mov r5, sp 61 mrs r4, cpsr_all 62 bic r4, r4, #(PSR_MODE) 63 orr r4, r4, #(PSR_SVC32_MODE) 64 msr cpsr_all, r4 65 mov sp, r5 66 67 /* Disable PID virtual address mapping */ 68 mov r4, #0 69 mcr 15, 0, r4, c13, c0, 0 70 71#if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 72/* 73 * CPWAIT -- Canonical method to wait for CP15 update. 74 * NOTE: Clobbers the specified temp reg. 75 * copied from arm/arm/cpufunc_asm_xscale.S 76 * XXX: better be in a common header file. 77 */ 78#define CPWAIT_BRANCH \ 79 sub pc, pc, #4 80 81#define CPWAIT(tmp) \ 82 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 83 mov tmp, tmp /* wait for it to complete */ ;\ 84 CPWAIT_BRANCH /* branch to next insn */ 85 86 /* 87 * Kernel is loaded in SDRAM (0xa0200000..), and is expected to run 88 * in VA 0xc0200000.. 89 */ 90 91 /* build page table from scratch */ 92 adr r9, .Lstartup_pagetable 93 ldr r9, [r9] 94 adr r4, .Lmmu_init_table 95 b 3f 96 972: 98 str r8, [r9, r7] 99 add r7, r7, #4 100 add r8, r8, #(L1_S_SIZE) 101 subs r6, r6, #1 102 bne 2b 1033: 104 ldmia r4!, {r6,r7,r8} /* # of sections, VA, PA|attr */ 105 cmp r6, #0 106 bne 2b 107 108 /* Set translation table */ 109 mcr p15, 0, r9, c2, c0, 0 110 mcr p15, 0, r9, c8, c7, 0 /* flush I/D-TLBs */ 111 CPWAIT(r9) 112 113 /* Set the Domain Access register. Very important! */ 114 mov r9, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 115 mcr p15, 0, r9, c3, c0, 0 116 117 /* Enable MMU */ 118 mrc p15, 0, r9, c1, c0, 0 119 orr r9, r9, #CPU_CONTROL_SYST_ENABLE 120 orr r9, r9, #CPU_CONTROL_MMU_ENABLE 121 mcr p15, 0, r9, c1, c0, 0 122 CPWAIT(r9) 123 124 /* Jump to kernel code in TRUE VA */ 125 adr r9, .Lstart 126 ldmia r9, {r9, sp} /* and set stack pointer */ 127 mov pc, r9 128 129.Lstart: 130 .word hpc_start 131 .word svcstk + INIT_ARM_STACK_SIZE 132 133#define MMU_INIT(va,pa,n_sec,attr) \ 134 .word (n_sec); \ 135 .word 4 * ((va) >> L1_S_SHIFT); \ 136 .word (pa)|(attr); 137 138.Lstartup_pagetable: 139 .word 0xa0004000 140 141.Lmmu_init_table: 142 /* fill all table VA==PA */ 143 MMU_INIT(0x00000000, 0x00000000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW)) 144 /* map SDRAM VA==PA, WT cacheable */ 145 MMU_INIT(0xa0000000, 0xa0000000, 256, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) 146 /* map VA 0xc0000000..0xcfffffff to PA 0xa0000000..0xafffffff */ 147 MMU_INIT(0xc0000000, 0xa0000000, 256, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) 148 149 .word 0,0,0 /* end of table */ 150 151 .bss 152svcstk: 153 .space INIT_ARM_STACK_SIZE 154 155 .text 156 .align 0 157ASENTRY_NP(hpc_start) 158#endif 159 160 mov fp, #0x00000000 /* trace back starts here */ 161 bl _C_LABEL(initarm) /* Off we go */ 162 163 /* init arm will return the new stack pointer. */ 164 mov sp, r0 165 166 mov fp, #0x00000000 /* trace back starts here */ 167 mov ip, sp 168 stmfd sp!, {fp, ip, lr, pc} 169 sub fp, ip, #4 170 171 /* Setup an initial trap frame for start_init to use */ 172 PUSHFRAME 173 mov r0, sp /* parameter to main is trap frame */ 174 bl _C_LABEL(main) /* Lets light the flame and start her up */ 175 PULLFRAME /* Pull the trap frame, now valid */ 176 movs pc, lr /* Exit to user process */ 177 /* Never gets here */ 178 b . 179 180 .text 181 .align 0 182 183.Lcpufuncs: 184 .word _C_LABEL(cpufuncs) 185 186ENTRY_NP(cpu_reset) 187 mrs r2, cpsr 188 bic r2, r2, #(PSR_MODE) 189 orr r2, r2, #(PSR_SVC32_MODE) 190 orr r2, r2, #(I32_bit | F32_bit) 191 msr cpsr_all, r2 192 193 ldr r4, .Lcpu_reset_address 194 ldr r4, [r4] 195 196 ldr r0, .Lcpufuncs 197 mov lr, pc 198 ldr pc, [r0, #CF_IDCACHE_WBINV_ALL] 199 200 /* 201 * MMU & IDC off, 32 bit program & data space 202 * Hurl ourselves into the ROM 203 */ 204 mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE) 205 mcr 15, 0, r0, c1, c0, 0 206 mcr 15, 0, r0, c8, c7, 0 207 mov pc, r4 208 209 /* 210 * _cpu_reset_address contains the address to branch to, to complete 211 * the CPU reset after turning the MMU off 212 * This variable is provided by the hardware specific code 213 */ 214 215.Lcpu_reset_address: 216 .word _C_LABEL(cpu_reset_address) 217 218/* 219 * setjump + longjmp 220 */ 221ENTRY(setjmp) 222 stmia r0, {r4-r14} 223 mov r0, #0x00000000 224 mov pc, lr 225 226ENTRY(longjmp) 227 ldmia r0, {r4-r14} 228 mov r0, #0x00000001 229 mov pc, lr 230 231 .data 232 .global _C_LABEL(esym) 233_C_LABEL(esym): .word _C_LABEL(end) 234 235ENTRY_NP(abort) 236 b _C_LABEL(abort) 237 238/* 239 * part of doing a system dump, we need to save registers and cpsr onto the 240 * stack, then save the rest of the registers into the dumppcb 241 */ 242ENTRY(dumpsys) 243 /* push registers onto stack */ 244 stmfd sp!, {r0-r7, lr} 245 246 /* push the status bits onto the stack */ 247 mrs r0, cpsr_all 248 stmfd sp!, {r0} 249 250 /* fill in dumppcb */ 251 ldr r0, .Ldumppcb 252 253#ifndef __XSCALE__ 254 add r2, r0, #(PCB_R8) 255 stmia r2, {r8-r13} 256#else 257 strd r8, [r0, #(PCB_R8)] 258 strd r10, [r0, #(PCB_R10)] 259 strd r12, [r0, #(PCB_R12)] 260#endif 261 262 bl _C_LABEL(dodumpsys) 263 264 /* unwind the stack */ 265 ldmfd sp!, {r0} 266 nop 267 ldmfd sp!, {r0-r7, pc} 268 269.Ldumppcb: 270 .word _C_LABEL(dumppcb) 271 272/* End of locore.S */ 273