1 /* $NetBSD: mq200debug.c,v 1.1 2001/03/25 13:06:53 takemura Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 TAKEMURA Shin 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #ifdef _KERNEL 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #else 38 #include <stdio.h> 39 #endif 40 #include <sys/types.h> 41 42 #include <machine/platid.h> 43 #include <machine/platid_mask.h> 44 45 #include "opt_mq200.h" 46 #include "mq200var.h" 47 #include "mq200reg.h" 48 #include "mq200priv.h" 49 50 #define ENABLE(b) ((b)?"enable":"disable") 51 52 #ifdef MQ200_DEBUG 53 54 char *mq200_clknames[] = { "BUS", "PLL1", "PLL2", "PLL3" }; 55 56 void 57 mq200_dump_pll(struct mq200_softc *sc) 58 { 59 int n, m; 60 u_int32_t reg, pm00r; 61 int clocks[4]; 62 int memclock, geclock; 63 static char *clknames[] = { "BUS", "PLL1", "PLL2", "PLL3" }; 64 static char *fd_names[] = { "1", "1.5", "2.5", "3.5", "4.5", "5.5", "6.5" }; 65 static int fd_vals[] = { 10, 15, 25, 35, 45, 55, 65 }; 66 #define FIXEDFLOAT1000(a) (a)/1000, (a)%1000 67 68 /* PM00R */ 69 pm00r = mq200_read(sc, MQ200_PMCR); 70 geclock = (pm00r&MQ200_PMC_GE_CLK_MASK)>>MQ200_PMC_GE_CLK_SHIFT; 71 72 /* MM01R */ 73 reg = mq200_read(sc, MQ200_MMR(1)); 74 memclock = (reg & MQ200_MM01_CLK_PLL2) ? 2 : 1; 75 76 /* bus clock */ 77 clocks[0] = 0; 78 79 /* PLL1 */ 80 reg = mq200_read(sc, MQ200_DCMISCR); 81 m = ((reg & MQ200_PLL_M_MASK) >> MQ200_PLL_M_SHIFT) + 1; 82 n = ((((reg & MQ200_PLL_N_MASK) >> MQ200_PLL_N_SHIFT) + 1) | 83 ((pm00r & MQ200_PMC_PLL1_N) << MQ200_PMC_PLL1_N_SHIFT)); 84 n <<= ((reg & MQ200_PLL_P_MASK) >> MQ200_PLL_P_SHIFT); 85 printf(" PLL1:%3d.%03dMHz(0x%08x, %d.%03dMHzx%3d/%3d)\n", 86 FIXEDFLOAT1000(sc->sc_baseclock*m/n), 87 reg, FIXEDFLOAT1000(sc->sc_baseclock), m, n); 88 clocks[1] = sc->sc_baseclock*m/n; 89 90 /* PLL2 */ 91 if (pm00r & MQ200_PMC_PLL2_ENABLE) { 92 reg = mq200_read(sc, MQ200_PLL2R); 93 m = ((reg & MQ200_PLL_M_MASK) >> MQ200_PLL_M_SHIFT) + 1; 94 n = ((((reg & MQ200_PLL_N_MASK) >> MQ200_PLL_N_SHIFT) +1) << 95 ((reg & MQ200_PLL_P_MASK) >> MQ200_PLL_P_SHIFT)); 96 clocks[2] = sc->sc_baseclock*m/n; 97 printf(" PLL2:%3d.%03dMHz(0x%08x, %d.%03dMHzx%3d/%3d)\n", 98 FIXEDFLOAT1000(sc->sc_baseclock*m/n), 99 reg, FIXEDFLOAT1000(sc->sc_baseclock), m, n); 100 } else { 101 printf(" PLL2: disable\n"); 102 clocks[2] = 0; 103 } 104 105 /* PLL3 */ 106 if (pm00r & MQ200_PMC_PLL3_ENABLE) { 107 reg = mq200_read(sc, MQ200_PLL3R); 108 m = (((reg & MQ200_PLL_M_MASK) >> MQ200_PLL_M_SHIFT) + 1); 109 n = ((((reg & MQ200_PLL_N_MASK) >> MQ200_PLL_N_SHIFT) + 1) << 110 ((reg & MQ200_PLL_P_MASK) >> MQ200_PLL_P_SHIFT)); 111 clocks[3] = sc->sc_baseclock*m/n; 112 printf(" PLL3:%3d.%03dMHz(0x%08x, %d.%03dMHzx%3d/%3d)\n", 113 FIXEDFLOAT1000(sc->sc_baseclock*m/n), 114 reg, FIXEDFLOAT1000(sc->sc_baseclock), m, n); 115 } else { 116 printf(" PLL3: disable\n"); 117 clocks[3] = 0; 118 } 119 120 printf(" MEM:%3d.%03dMHz(%s)\n", 121 FIXEDFLOAT1000(clocks[memclock]), 122 clknames[memclock]); 123 printf(" GE:%3d.%03dMHz(%s)\n", 124 FIXEDFLOAT1000(clocks[geclock]), 125 clknames[geclock]); 126 127 /* GC1 */ 128 reg = mq200_read(sc, MQ200_GCCR(MQ200_GC1)); 129 if (reg & MQ200_GCC_ENABLE) { 130 int fd, sd, rc; 131 rc = (reg&MQ200_GCC_RCLK_MASK)>>MQ200_GCC_RCLK_SHIFT; 132 fd = (reg&MQ200_GCC_MCLK_FD_MASK)>>MQ200_GCC_MCLK_FD_SHIFT; 133 sd = (reg&MQ200_GCC_MCLK_SD_MASK)>>MQ200_GCC_MCLK_SD_SHIFT; 134 printf(" GC1:%3d.%03dMHz(%s/%s/%d)", 135 FIXEDFLOAT1000(clocks[rc]*10/fd_vals[fd]/sd), 136 clknames[rc], fd_names[fd], sd); 137 /* GC01R */ 138 reg = mq200_read(sc, MQ200_GC1CRTCR); 139 if (reg&MQ200_GC1CRTC_DACEN) 140 printf(", CRT"); 141 reg = mq200_read(sc, MQ200_FPCR); 142 if ((reg & MQ200_FPC_ENABLE) && !(reg & MQ200_FPC_GC2)) 143 printf(", LCD"); 144 printf("\n"); 145 } else { 146 printf(" GC1: disable\n"); 147 } 148 149 /* GC2 */ 150 reg = mq200_read(sc, MQ200_GCCR(MQ200_GC2)); 151 if (reg & MQ200_GCC_ENABLE) { 152 int fd, sd, rc; 153 rc = (reg&MQ200_GCC_RCLK_MASK)>>MQ200_GCC_RCLK_SHIFT; 154 fd = (reg&MQ200_GCC_MCLK_FD_MASK)>>MQ200_GCC_MCLK_FD_SHIFT; 155 sd = (reg&MQ200_GCC_MCLK_SD_MASK)>>MQ200_GCC_MCLK_SD_SHIFT; 156 printf(" GC2:%3d.%03dMHz(%s/%s/%d)", 157 FIXEDFLOAT1000(clocks[rc]*10/fd_vals[fd]/sd), 158 clknames[rc], fd_names[fd], sd); 159 reg = mq200_read(sc, MQ200_FPCR); 160 if ((reg & MQ200_FPC_ENABLE) && (reg & MQ200_FPC_GC2)) 161 printf(", FP"); 162 printf("\n"); 163 } else { 164 printf(" GC2: disable\n"); 165 } 166 } 167 168 struct { 169 char *name; 170 u_int32_t base; 171 int start, end; 172 } regs[] = { 173 { "GC", MQ200_GCR(0), 0x00, 0x13 }, 174 { "GC", MQ200_GCR(0), 0x20, 0x33 }, 175 { "FP", MQ200_FP, 0x00, 0x0f }, 176 { "CC", MQ200_CC, 0x00, 0x01 }, 177 { "PC", MQ200_PC, 0x00, 0x05 }, 178 { "MM", MQ200_MM, 0x00, 0x04 }, 179 { "DC", MQ200_DC, 0x00, 0x03 }, 180 { "PM", MQ200_PM, 0x00, 0x03 }, 181 { "PM", MQ200_PM, 0x06, 0x07 }, 182 { "IN", MQ200_IN, 0x00, 0x03 }, 183 }; 184 185 char * 186 mq200_regname(struct mq200_softc *sc, int offset, char *buf, int bufsize) 187 { 188 int i; 189 190 for (i = 0; i < sizeof(regs)/sizeof(*regs); i++) 191 if (regs[i].base + regs[i].start * 4 <= offset && 192 offset <= regs[i].base + regs[i].end * 4) { 193 sprintf(buf, "%s%02XR", regs[i].name, 194 (offset - regs[i].base) / 4); 195 return (buf); 196 } 197 sprintf(buf, "OFFSET %02X", offset); 198 return (buf); 199 } 200 201 void 202 mq200_dump_all(struct mq200_softc *sc) 203 { 204 int i, j; 205 206 for (i = 0; i < sizeof(regs)/sizeof(*regs); i++) 207 for (j = regs[i].start; j <= regs[i].end; j++) 208 printf("%s%02XR: %08x\n", 209 regs[i].name, j, 210 mq200_read(sc, regs[i].base + (j * 4))); 211 } 212 213 void 214 mq200_write(struct mq200_softc *sc, int offset, u_int32_t data) 215 { 216 int i; 217 char buf[32]; 218 219 for (i = 0; i < MQ200_I_MAX; i++) { 220 if (sc->sc_regctxs[i].offset == offset) 221 printf("mq200_write: WARNING: raw access %s\n", 222 mq200_regname(sc, offset, buf, sizeof(buf))); 223 } 224 225 mq200_writex(sc, offset, data); 226 } 227 228 #if 0 229 void 230 mq200_dump_gc(struct mq200_softc *sc, int gc) 231 { 232 u_int32_t reg; 233 char *depth_names[] = { 234 "1bpp with CLUT", 235 "2bpp with CLUT", 236 "4bpp with CLUT", 237 "8bpp with CLUT", 238 "16bpp with CLUT", 239 "24bpp with CLUT", 240 "32bpp(RGB) with CLUT", 241 "32bpp(BGR) with CLUT", 242 "1bpp w/o CLUT", 243 "2bpp w/o CLUT", 244 "4bpp w/o CLUT", 245 "8bpp w/o CLUT", 246 "16bpp w/o CLUT", 247 "24bpp w/o CLUT", 248 "32bpp(RGB) w/o CLUT", 249 "32bpp(BGR) w/o CLUT", 250 }; 251 char *rc_names[] = { "BUS", "PLL1", "PLL2", "PLL3" }; 252 char *fd_names[] = { "1", "1.5", "2.5", "3.5", "4.5", "5.5", "6.5" }; 253 254 /* 255 * GC00R Graphics Controller Control 256 */ 257 reg = mq200_read(sc, MQ200_GCCR(gc)); 258 printf("GC00R=0x%08x: ", reg); 259 printf("%s %s%s%s%s%s\n", 260 ENABLE(reg & MQ200_GCC_ENABLE), 261 (reg & MQ200_GCC_HCRESET)?"HC_reset ":"", 262 (reg & MQ200_GCC_VCRESET)?"VC_reset ":"", 263 (reg & MQ200_GCC_HCEN)?"cursor_enable ":"", 264 (reg & MQ200_GCC_TESTMODE0)?"test_mode0 ":"", 265 (reg & MQ200_GCC_TESTMODE1)?"test_mode1 ":""); 266 printf(" window: %s %s\n", 267 ENABLE(reg & MQ200_GCC_WINEN), 268 depth_names[(reg&MQ200_GCC_DEPTH_MASK)>>MQ200_GCC_DEPTH_SHIFT]); 269 printf(" altwin: %s %s\n", 270 ENABLE(reg & MQ200_GCC_ALTEN), 271 depth_names[(reg&MQ200_GCC_ALTDEPTH_MASK)>>MQ200_GCC_ALTDEPTH_SHIFT]); 272 printf(" clock: root_clock/first_div/second_div = %s/%s/%d\n", 273 rc_names[(reg&MQ200_GCC_RCLK_MASK)>>MQ200_GCC_RCLK_SHIFT], 274 fd_names[(reg&MQ200_GCC_MCLK_FD_MASK)>>MQ200_GCC_MCLK_FD_SHIFT], 275 (reg&MQ200_GCC_MCLK_SD_MASK)>>MQ200_GCC_MCLK_SD_SHIFT); 276 277 if (gc == 0) { 278 /* 279 * GC01R Graphics Controller CRT Control 280 */ 281 reg = mq200_read(sc, MQ200_GC1CRTCR); 282 printf("GC01R=0x%08x:\n", reg); 283 printf(" CRT DAC: %s\n", 284 ENABLE(reg&MQ200_GC1CRTC_DACEN)); 285 286 printf(" power down mode: H-sync="); 287 switch (reg & MQ200_GC1CRTC_HSYNC_PMMASK) { 288 case MQ200_GC1CRTC_HSYNC_PMNORMAL: 289 if (reg & MQ200_GC1CRTC_HSYNC_PMCLK) 290 printf("PMCLK"); 291 else 292 printf("LOW"); 293 break; 294 case MQ200_GC1CRTC_HSYNC_PMLOW: 295 printf("LOW"); 296 break; 297 case MQ200_GC1CRTC_HSYNC_PMHIGH: 298 printf("HIGH"); 299 break; 300 default: 301 printf("???"); 302 break; 303 } 304 305 printf(" V-sync="); 306 switch (reg & MQ200_GC1CRTC_VSYNC_PMMASK) { 307 case MQ200_GC1CRTC_VSYNC_PMNORMAL: 308 if (reg & MQ200_GC1CRTC_VSYNC_PMCLK) 309 printf("PMCLK"); 310 else 311 printf("LOW"); 312 break; 313 case MQ200_GC1CRTC_VSYNC_PMLOW: 314 printf("LOW"); 315 break; 316 case MQ200_GC1CRTC_VSYNC_PMHIGH: 317 printf("HIGH"); 318 break; 319 default: 320 printf("???"); 321 break; 322 } 323 printf("\n"); 324 325 printf(" sync active: H=%s V=%s\n", 326 (reg & MQ200_GC1CRTC_HSYNC_ACTVLOW)?"low":"high", 327 (reg & MQ200_GC1CRTC_VSYNC_ACTVLOW)?"low":"high"); 328 printf(" other: "); 329 if (reg & MQ200_GC1CRTC_SYNC_PEDESTAL_EN) 330 printf("Sync_pedestal "); 331 if (reg & MQ200_GC1CRTC_BLANK_PEDESTAL_EN) 332 printf("Blank_pedestal "); 333 if (reg & MQ200_GC1CRTC_COMPOSITE_SYNC_EN) 334 printf("Conposite_sync "); 335 if (reg & MQ200_GC1CRTC_VREF_EXTR) 336 printf("External_VREF "); 337 if (reg & MQ200_GC1CRTC_MONITOR_SENCE_EN) { 338 if (reg & MQ200_GC1CRTC_CONSTANT_OUTPUT_EN) 339 printf("Monitor_sence=%s%s%s/- ", 340 (reg & MQ200_GC1CRTC_BLUE_NOTLOADED)?"":"B", 341 (reg & MQ200_GC1CRTC_RED_NOTLOADED)?"":"R", 342 (reg & MQ200_GC1CRTC_GREEN_NOTLOADED)?"":"G"); 343 else 344 printf("Monitor_sence=%s%s%s/0x%02x ", 345 (reg & MQ200_GC1CRTC_BLUE_NOTLOADED)?"":"B", 346 (reg & MQ200_GC1CRTC_RED_NOTLOADED)?"":"R", 347 (reg & MQ200_GC1CRTC_GREEN_NOTLOADED)?"":"G", 348 (reg & MQ200_GC1CRTC_OUTPUT_LEVEL_MASK)>>MQ200_GC1CRTC_OUTPUT_LEVEL_SHIFT); 349 } 350 if (reg & MQ200_GC1CRTC_MONO) 351 printf("Mono_monitor "); 352 printf("\n"); 353 } 354 355 /* 356 * GC02R Horizontal Display Control 357 */ 358 reg = mq200_read(sc, MQ200_GCHDCR(gc)); 359 if (gc == 0) { 360 printf("GC02R=0x%08x: Horizontal display total=%03d end=%03d\n", reg, 361 (reg&MQ200_GC1HDC_TOTAL_MASK)>>MQ200_GC1HDC_TOTAL_SHIFT, 362 (reg&MQ200_GCHDC_END_MASK)>>MQ200_GCHDC_END_SHIFT); 363 } else { 364 printf("GC02R=0x%08x: Horizontal display end=%03d\n", reg, 365 (reg&MQ200_GCHDC_END_MASK)>>MQ200_GCHDC_END_SHIFT); 366 } 367 368 /* 369 * GC03R Vertical Display Control 370 */ 371 reg = mq200_read(sc, MQ200_GCVDCR(gc)); 372 if (gc == 0) { 373 printf("GC03R=0x%08x: Vertical display total=%03d end=%03d\n", reg, 374 (reg&MQ200_GC1VDC_TOTAL_MASK)>>MQ200_GC1VDC_TOTAL_SHIFT, 375 (reg&MQ200_GCVDC_END_MASK)>>MQ200_GCVDC_END_SHIFT); 376 } else { 377 printf("GC03R=0x%08x: Vertical display end=%03d\n", reg, 378 (reg&MQ200_GCVDC_END_MASK)>>MQ200_GCVDC_END_SHIFT); 379 } 380 381 /* 382 * GC04R Horizontal Sync Control 383 */ 384 reg = mq200_read(sc, MQ200_GCHSCR(gc)); 385 printf("GC04R=0x%08x: Horizontal sync start=%03d end=%03d\n", reg, 386 (reg&MQ200_GCHSC_START_MASK)>>MQ200_GCHSC_START_SHIFT, 387 (reg&MQ200_GCHSC_END_MASK)>>MQ200_GCHSC_END_SHIFT); 388 389 /* 390 * GC05R Vertical Sync Control 391 */ 392 reg = mq200_read(sc, MQ200_GCVSCR(gc)); 393 printf("GC05R=0x%08x: Vertical sync start=%03d end=%03d\n", reg, 394 (reg&MQ200_GCVSC_START_MASK)>>MQ200_GCVSC_START_SHIFT, 395 (reg&MQ200_GCVSC_END_MASK)>>MQ200_GCVSC_END_SHIFT); 396 397 if (gc == 0) { 398 /* 399 * GC07R Vertical Display Count 400 */ 401 reg = mq200_read(sc, MQ200_GC1VDCNTR); 402 printf("GC07R=0x%08x: Vertical Display Count=%d\n", reg, 403 (reg&MQ200_GC1VDCNT_MASK)); 404 } 405 406 /* 407 * GC08R Window Horizontal Control 408 */ 409 reg = mq200_read(sc, MQ200_GCWHCR(gc)); 410 printf("GC08R=0x%08x: Window Horizontal start=%03d width=%03d", 411 reg, 412 (reg&MQ200_GCWHC_START_MASK)>> MQ200_GCWHC_START_SHIFT, 413 (reg&MQ200_GCWHC_WIDTH_MASK)>> MQ200_GCWHC_WIDTH_SHIFT); 414 if (gc == 0) { 415 printf(" add=%03x", 416 (reg&MQ200_GC1WHC_ALD_MASK)>> MQ200_GC1WHC_ALD_SHIFT); 417 } 418 printf("\n"); 419 420 /* 421 * GC09R Window Vertical Control 422 */ 423 reg = mq200_read(sc, MQ200_GCWVCR(gc)); 424 printf("GC09R=0x%08x: Window Vertical start=%03d hight=%03d\n", 425 reg, 426 (reg&MQ200_GCWVC_START_MASK)>> MQ200_GCWVC_START_SHIFT, 427 (reg&MQ200_GCWVC_HEIGHT_MASK)>> MQ200_GCWVC_HEIGHT_SHIFT); 428 429 /* 430 * GC0AR Alternate Window Horizontal Control 431 */ 432 reg = mq200_read(sc, MQ200_GCAWHCR(gc)); 433 printf("GC0AR=0x%08x: Altwin Horizontal start=%03d width=%03d", 434 reg, 435 (reg&MQ200_GCAWHC_START_MASK)>> MQ200_GCAWHC_START_SHIFT, 436 (reg&MQ200_GCAWHC_WIDTH_MASK)>> MQ200_GCAWHC_WIDTH_SHIFT); 437 if (gc == 0) { 438 printf(" add=%03d", 439 (reg&MQ200_GC1AWHC_ALD_MASK)>> MQ200_GC1AWHC_ALD_SHIFT); 440 } 441 printf("\n"); 442 443 /* 444 * GC0BR Alternate Window Vertical Control 445 */ 446 reg = mq200_read(sc, MQ200_GCAWVCR(gc)); 447 printf("GC0BR=0x%08x: Altwin Vertical start=%03d hight=%03d\n", 448 reg, 449 (reg&MQ200_GCAWVC_START_MASK)>> MQ200_GCAWVC_START_SHIFT, 450 (reg&MQ200_GCAWVC_HEIGHT_MASK)>> MQ200_GCAWVC_HEIGHT_SHIFT); 451 452 /* 453 * GC0CR Window Start Address 454 */ 455 reg = mq200_read(sc, MQ200_GCWSAR(gc)); 456 printf("GC0CR=0x%08x: Window start address=0x%08x\n", 457 reg, (reg&MQ200_GCWSA_MASK)); 458 459 /* 460 * GC0DR Alternate Window Start Address 461 */ 462 reg = mq200_read(sc, MQ200_GCAWSAR(gc)); 463 printf("GC0DR=0x%08x: Altwin start address=0x%08x palette_index=%02d\n", 464 reg, (reg&MQ200_GCAWSA_MASK), 465 (reg&MQ200_GCAWPI_MASK)>>MQ200_GCAWPI_SHIFT); 466 467 /* 468 * GC0ER Windows Stride 469 */ 470 reg = mq200_read(sc, MQ200_GCWSTR(gc)); 471 printf("GC0ER=0x%08x: Stride window=%04d altwin=%04d\n", 472 reg, 473 (reg&MQ200_GCWST_MASK)>>MQ200_GCWST_SHIFT, 474 (reg&MQ200_GCAWST_MASK)>>MQ200_GCAWST_SHIFT); 475 476 /* 477 * GC10R Hardware Cursor Position 478 */ 479 reg = mq200_read(sc, MQ200_GCHCPR(gc)); 480 printf("GC10R=0x%08x: Hardware Cursor Position %d,%d\n", 481 reg, 482 (reg&MQ200_GCHCP_HSTART_MASK)>>MQ200_GCHCP_HSTART_SHIFT, 483 (reg&MQ200_GCHCP_VSTART_MASK)>>MQ200_GCHCP_VSTART_SHIFT); 484 485 /* 486 * GC11R Hardware Cursor Start Address and Offset 487 */ 488 reg = mq200_read(sc, MQ200_GCHCAOR(gc)); 489 printf("GC11R=0x%08x: Hardware Cursor Start Address and Offset\n", 490 reg); 491 492 /* 493 * GC12R Hardware Cursor Foreground Color 494 */ 495 reg = mq200_read(sc, MQ200_GCHCFCR(gc)); 496 printf("GC12R=0x%08x: Hardware Cursor Foreground Color\n", reg); 497 498 /* 499 * GC13R Hardware Cursor Background Color 500 */ 501 reg = mq200_read(sc, MQ200_GCHCBCR(gc)); 502 printf("GC13R=0x%08x: Hardware Cursor Background Color\n", reg); 503 504 } 505 506 void 507 mq200_dump_fp(struct mq200_softc *sc) 508 { 509 u_int32_t reg; 510 #define I(type) ((type)>>MQ200_FPC_TYPE_SHIFT) 511 static char *panel_type_names[64] = { 512 [I(MQ200_FPC_TFT4MONO)] = "TFT 4bit mono", 513 [I(MQ200_FPC_TFT12)] = "TFT 12bit color", 514 [I(MQ200_FPC_SSTN4)] = "S-STN 4bit color", 515 [I(MQ200_FPC_DSTN8)] = "D-STN 8bit color", 516 [I(MQ200_FPC_TFT6MONO)] = "TFT 6bit mono", 517 [I(MQ200_FPC_TFT18)] = "TFT 18bit color", 518 [I(MQ200_FPC_SSTN8)] = "S-STN 8bit color", 519 [I(MQ200_FPC_DSTN16)] = "D-STN 16bit color", 520 [I(MQ200_FPC_TFT8MONO)] = "TFT 8bit mono", 521 [I(MQ200_FPC_TFT24)] = "TFT 24bit color", 522 [I(MQ200_FPC_SSTN12)] = "S-STN 12bit color", 523 [I(MQ200_FPC_DSTN24)] = "D-STN 24bit color", 524 [I(MQ200_FPC_SSTN16)] = "S-STN 16bit color", 525 [I(MQ200_FPC_SSTN24)] = "S-STN 24bit color", 526 }; 527 528 reg = mq200_read(sc, MQ200_FPCR); 529 printf("FP00R=0x%08x: Flat Panel Control\n", reg); 530 printf(" %s, driven by %s, %s\n", 531 ENABLE(reg & MQ200_FPC_ENABLE), 532 (reg & MQ200_FPC_GC2) ? "GC2" : "GC1", 533 panel_type_names[(reg & MQ200_FPC_TYPE_MASK) >> MQ200_FPC_TYPE_SHIFT]); 534 reg = mq200_read(sc, MQ200_FPPCR); 535 printf("FP01R=0x%08x: Flat Panel Output Pin Control\n", reg); 536 } 537 538 void 539 mq200_dump_dc(struct mq200_softc *sc) 540 { 541 u_int32_t reg; 542 543 reg = 0; 544 } 545 #endif /* 0 */ 546 547 #endif /* MQ200_DEBUG */ 548