xref: /netbsd/sys/arch/hpcmips/dev/ucb1200reg.h (revision bf9ec67e)
1 /*	$NetBSD: ucb1200reg.h,v 1.7 2001/09/15 12:47:08 uch Exp $ */
2 
3 /*-
4  * Copyright (c) 2000 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by UCHIYAMA Yasushi.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *        This product includes software developed by the NetBSD
21  *        Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 /*
40  * PHILIPS UCB1200 Advanced modem/audio analog front-end
41  */
42 
43 /* Internal register. access via SIB */
44 #define	UCB1200_IO_DATA_REG		0
45 #define	UCB1200_IO_DIR_REG		1
46 #define	UCB1200_POSINTEN_REG		2
47 #define	UCB1200_NEGINTEN_REG		3
48 #define	UCB1200_INTSTAT_REG		4
49 #define	UCB1200_TELECOMCTRLA_REG	5
50 #define	UCB1200_TELECOMCTRLB_REG	6
51 #define	UCB1200_AUDIOCTRLA_REG		7
52 #define	UCB1200_AUDIOCTRLB_REG		8
53 #define	UCB1200_TSCTRL_REG		9
54 #define	UCB1200_ADCCTRL_REG		10
55 #define	UCB1200_ADCDATA_REG		11
56 #define	UCB1200_ID_REG			12
57 #define	UCB1200_MODE_REG		13
58 #define	UCB1200_RESERVED_REG		14
59 #define	UCB1200_NULL_REG		15 /* always returns 0xffff */
60 
61 /*
62  * I/O port data register
63  */
64 #define UCB1200_IOPORT_MAX		10
65 #define UCB1200_IO_DATA_SPEAKER		0x100 /* XXX general? */
66 
67 /*
68  * Telecom control register A
69  */
70 #define UCB1200_TELECOMCTRLA_DIV_MIN	16
71 #define UCB1200_TELECOMCTRLA_DIV_MAX	127
72 #define UCB1200_TELECOMCTRLA_DIV_SHIFT	0
73 #define UCB1200_TELECOMCTRLA_DIV_MASK	0x7f
74 #define UCB1200_TELECOMCTRLA_DIV(cr)					\
75 	(((cr) >> UCB1200_TELECOMCTRLA_DIV_SHIFT) &			\
76 	UCB1200_TELECOMCTRLA_DIV_MASK)
77 #define UCB1200_TELECOMCTRLA_DIV_SET(cr, val)				\
78 	((cr) | (((val) << UCB1200_TELECOMCTRLA_DIV_SHIFT) &		\
79 	(UCB1200_TELECOMCTRLA_DIV_MASK << UCB1200_TELECOMCTRLA_DIV_SHIFT)))
80 
81 #define UCB1200_TELECOMCTRLA_LOOP	0x0080
82 
83 /*
84  * Telecom control register B
85  */
86 #define UCB1200_TELECOMCTRLB_VBF		0x0008
87 #define UCB1200_TELECOMCTRLB_CLIPSTATCLR	0x0010
88 #define UCB1200_TELECOMCTRLB_ATT		0x0040
89 #define UCB1200_TELECOMCTRLB_STS		0x0800
90 #define UCB1200_TELECOMCTRLB_MUTE		0x2000
91 #define UCB1200_TELECOMCTRLB_INEN		0x4000
92 #define UCB1200_TELECOMCTRLB_OUTEN		0x8000
93 
94 /*
95  * Audio control register A
96  */
97 #define UCB1200_AUDIOCTRLA_DIV_MIN	6
98 #define UCB1200_AUDIOCTRLA_DIV_MAX	127
99 #define UCB1200_AUDIOCTRLA_DIV_SHIFT	0
100 #define UCB1200_AUDIOCTRLA_DIV_MASK	0x7f
101 #define UCB1200_AUDIOCTRLA_DIV(cr)					\
102 	(((cr) >> UCB1200_AUDIOCTRLA_DIV_SHIFT) &			\
103 	UCB1200_AUDIOCTRLA_DIV_MASK)
104 #define UCB1200_AUDIOCTRLA_DIV_SET(cr, val)				\
105 	((cr) | (((val) << UCB1200_AUDIOCTRLA_DIV_SHIFT) &		\
106 	(UCB1200_AUDIOCTRLA_DIV_MASK << UCB1200_AUDIOCTRLA_DIV_SHIFT)))
107 
108 #define UCB1200_AUDIOCTRLA_GAIN_SHIFT	7
109 #define UCB1200_AUDIOCTRLA_GAIN_MASK	0x1f
110 #define UCB1200_AUDIOCTRLA_GAIN(cr)					\
111 	(((cr) >> UCB1200_AUDIOCTRLA_GAIN_SHIFT) &			\
112 	UCB1200_AUDIOCTRLA_GAIN_MASK)
113 #define UCB1200_AUDIOCTRLA_GAIN_SET(cr, val)				\
114 	((cr) | (((val) << UCB1200_AUDIOCTRLA_GAIN_SHIFT) &		\
115 	(UCB1200_AUDIOCTRLA_GAIN_MASK << UCB1200_AUDIOCTRLA_GAIN_SHIFT)))
116 
117 /*
118  * Audio control register B
119  */
120 #define UCB1200_AUDIOCTRLB_ATT_MIN	0
121 #define UCB1200_AUDIOCTRLB_ATT_MAX	0x1f
122 #define UCB1200_AUDIOCTRLB_ATT_SHIFT	0
123 #define UCB1200_AUDIOCTRLB_ATT_MASK	0x1f
124 #define UCB1200_AUDIOCTRLB_ATT(cr)					\
125 	(((cr) >> UCB1200_AUDIOCTRLB_ATT_SHIFT) &			\
126 	UCB1200_AUDIOCTRLB_ATT_MASK)
127 #define UCB1200_AUDIOCTRLB_ATT_CLR(cr)					\
128 	((cr) & ~(UCB1200_AUDIOCTRLB_ATT_MASK <<			\
129 		  UCB1200_AUDIOCTRLB_ATT_SHIFT))
130 #define UCB1200_AUDIOCTRLB_ATT_SET(cr, val)				\
131 	((cr) | (((val) << UCB1200_AUDIOCTRLB_ATT_SHIFT) &		\
132 	(UCB1200_AUDIOCTRLB_ATT_MASK << UCB1200_AUDIOCTRLB_ATT_SHIFT)))
133 
134 #define	UCB1200_AUDIOCTRLB_CLIPSTATCLR	0x0040
135 #define	UCB1200_AUDIOCTRLB_LOOP		0x0100
136 #define	UCB1200_AUDIOCTRLB_MUTE		0x2000
137 #define	UCB1200_AUDIOCTRLB_INEN		0x4000
138 #define	UCB1200_AUDIOCTRLB_OUTEN	0x8000
139 
140 /*
141  * Touch screen control register
142  */
143 #define	UCB1200_TSCTRL_MXLOW	0x00002000
144 #define	UCB1200_TSCTRL_PXLOW	0x00001000
145 #define	UCB1200_TSCTRL_BIAS	0x00000800
146 
147 #define UCB1200_TSCTRL_MODE_SHIFT	8
148 #define UCB1200_TSCTRL_MODE_MASK	0x7f
149 #define UCB1200_TSCTRL_MODE(cr)						\
150 	(((cr) >> UCB1200_TSCTRL_MODE_SHIFT) &				\
151 	UCB1200_TSCTRL_MODE_MASK)
152 #define UCB1200_TSCTRL_MODE_INTERRUPT	0
153 #define UCB1200_TSCTRL_MODE_PRESSURE	(1 << UCB1200_TSCTRL_MODE_SHIFT)
154 #define UCB1200_TSCTRL_MODE_POSITION0	(2 << UCB1200_TSCTRL_MODE_SHIFT)
155 #define UCB1200_TSCTRL_MODE_POSITION1	(3 << UCB1200_TSCTRL_MODE_SHIFT)
156 
157 #define	UCB1200_TSCTRL_PYGND	0x00000080
158 #define	UCB1200_TSCTRL_MYGND	0x00000040
159 #define	UCB1200_TSCTRL_PXGND	0x00000020
160 #define	UCB1200_TSCTRL_MXGND	0x00000010
161 #define	UCB1200_TSCTRL_PYPWR	0x00000008
162 #define	UCB1200_TSCTRL_MYPWR	0x00000004
163 #define	UCB1200_TSCTRL_PXPWR	0x00000002
164 #define	UCB1200_TSCTRL_MXPWR	0x00000001
165 
166 /* touch screen modes */
167 #define UCB1200_TSCTRL_YPOSITION					\
168 	(UCB1200_TSCTRL_PXPWR | UCB1200_TSCTRL_MXGND |			\
169 	UCB1200_TSCTRL_MODE_POSITION0 | UCB1200_TSCTRL_BIAS)
170 #define UCB1200_TSCTRL_XPOSITION					\
171 	(UCB1200_TSCTRL_PYPWR | UCB1200_TSCTRL_MYGND |			\
172 	UCB1200_TSCTRL_MODE_POSITION0 | UCB1200_TSCTRL_BIAS)
173 #define UCB1200_TSCTRL_PRESSURE						\
174 	(UCB1200_TSCTRL_PXPWR | UCB1200_TSCTRL_MXPWR |			\
175 	UCB1200_TSCTRL_PYGND | UCB1200_TSCTRL_MYGND |			\
176 	UCB1200_TSCTRL_MODE_PRESSURE | UCB1200_TSCTRL_BIAS)
177 
178 #define UCB1200_TSCTRL_INTERRUPT					\
179 	(UCB1200_TSCTRL_PXPWR | UCB1200_TSCTRL_MXPWR |			\
180 	UCB1200_TSCTRL_PYGND | UCB1200_TSCTRL_MYGND |			\
181 	UCB1200_TSCTRL_MODE_INTERRUPT)
182 
183 #define UCB1200_TSCTRL_PRESSURE1
184 #define UCB1200_TSCTRL_PRESSURE2
185 #define UCB1200_TSCTRL_PRESSURE3
186 #define UCB1200_TSCTRL_PRESSURE4
187 #define UCB1200_TSCTRL_PRESSURE5
188 #define UCB1200_TSCTRL_XRESISTANCE
189 #define UCB1200_TSCTRL_YRESISTANCE
190 
191 /*
192  * ADC control register
193  */
194 #define UCB1200_ADCCTRL_ENABLE		0x8000
195 #define UCB1200_ADCCTRL_START		0x0080
196 #define UCB1200_ADCCTRL_EXTREF		0x0020
197 
198 #define UCB1200_ADCCTRL_INPUT_SHIFT	2
199 #define UCB1200_ADCCTRL_INPUT_MASK	0x7
200 #define UCB1200_ADCCTRL_INPUT_SET(cr, val)				\
201 	((cr) | (((val) << UCB1200_ADCCTRL_INPUT_SHIFT) &		\
202 	(UCB1200_ADCCTRL_INPUT_MASK << UCB1200_ADCCTRL_INPUT_SHIFT)))
203 #define UCB1200_ADCCTRL_INPUT_TSPX	0x0
204 #define UCB1200_ADCCTRL_INPUT_TSMX	0x1
205 #define UCB1200_ADCCTRL_INPUT_TSPY	0x2
206 #define UCB1200_ADCCTRL_INPUT_TSMY	0x3
207 #define UCB1200_ADCCTRL_INPUT_AD0	0x4
208 #define UCB1200_ADCCTRL_INPUT_AD1	0x5
209 #define UCB1200_ADCCTRL_INPUT_AD2	0x6
210 #define UCB1200_ADCCTRL_INPUT_AD3	0x7
211 
212 #define UCB1200_ADCCTRL_VREFBYP		0x0002
213 #define UCB1200_ADCCTRL_SYNCMODE	0x0001
214 
215 /*
216  * ADC data register
217  */
218 #define UCB1200_ADCDATA_INPROGRESS	0x8000
219 
220 #define UCB1200_ADCDATA_SHIFT	5
221 #define UCB1200_ADCDATA_MASK	0x3ff
222 #define UCB1200_ADCDATA(cr)						\
223 	(((cr) >> UCB1200_ADCDATA_SHIFT) &				\
224 	UCB1200_ADCDATA_MASK)
225 
226 /*
227  * ID register
228  */
229 /* PHILIPS products */
230 /* Version 3, Device 0, Supplier 1 */
231 #define UCB1100_ID	0x1003
232 /* Version 4, Device 0, Supplier 1 */
233 #define UCB1200_ID	0x1004
234 /* Version 10, Device 0, Supplier 1 */
235 #define UCB1300_ID	0x100a
236 /* TOSHIBA TC35413F */
237 #define TC35413F_ID	0x9712
238