1 /* $NetBSD: tx3912video.c,v 1.28 2002/04/13 09:29:54 takemura Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #define TX3912VIDEO_DEBUG 40 41 #include "hpcfb.h" 42 #include "bivideo.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/extent.h> 48 49 #include <sys/ioctl.h> 50 #include <sys/buf.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <dev/cons.h> /* consdev */ 55 56 #include <machine/bus.h> 57 #include <machine/bootinfo.h> 58 #include <machine/config_hook.h> 59 60 #include <hpcmips/tx/tx39var.h> 61 #include <hpcmips/tx/tx3912videovar.h> 62 #include <hpcmips/tx/tx3912videoreg.h> 63 64 /* CLUT */ 65 #include <dev/wscons/wsdisplayvar.h> 66 #include <dev/rasops/rasops.h> 67 #include <dev/hpc/video_subr.h> 68 69 #include <dev/wscons/wsconsio.h> 70 #include <dev/hpc/hpcfbvar.h> 71 #include <dev/hpc/hpcfbio.h> 72 #if NBIVIDEO > 0 73 #include <dev/hpc/bivideovar.h> 74 #endif 75 76 #ifdef TX3912VIDEO_DEBUG 77 int tx3912video_debug = 1; 78 #define DPRINTF(arg) if (tx3912video_debug) printf arg; 79 #define DPRINTFN(n, arg) if (tx3912video_debug > (n)) printf arg; 80 #else 81 #define DPRINTF(arg) 82 #define DPRINTFN(n, arg) 83 #endif 84 85 struct tx3912video_softc { 86 struct device sc_dev; 87 void *sc_powerhook; /* power management hook */ 88 int sc_console; 89 struct hpcfb_fbconf sc_fbconf; 90 struct hpcfb_dspconf sc_dspconf; 91 struct video_chip *sc_chip; 92 }; 93 94 /* TX3912 built-in video chip itself */ 95 static struct video_chip tx3912video_chip; 96 97 int tx3912video_power(void *, int, long, void *); 98 void tx3912video_framebuffer_init(struct video_chip *); 99 int tx3912video_framebuffer_alloc(struct video_chip *, paddr_t, paddr_t *); 100 void tx3912video_reset(struct video_chip *); 101 void tx3912video_resolution_init(struct video_chip *); 102 int tx3912video_match(struct device *, struct cfdata *, void *); 103 void tx3912video_attach(struct device *, struct device *, void *); 104 int tx3912video_print(void *, const char *); 105 106 void tx3912video_hpcfbinit(struct tx3912video_softc *); 107 int tx3912video_ioctl(void *, u_long, caddr_t, int, struct proc *); 108 paddr_t tx3912video_mmap(void *, off_t, int); 109 110 void tx3912video_clut_init(struct tx3912video_softc *); 111 void tx3912video_clut_install(void *, struct rasops_info *); 112 void tx3912video_clut_get(struct tx3912video_softc *, u_int32_t *, int, 113 int); 114 115 static int __get_color8(int); 116 static int __get_color4(int); 117 118 struct cfattach tx3912video_ca = { 119 sizeof(struct tx3912video_softc), tx3912video_match, 120 tx3912video_attach 121 }; 122 123 struct hpcfb_accessops tx3912video_ha = { 124 tx3912video_ioctl, tx3912video_mmap, 0, 0, 0, 0, 125 tx3912video_clut_install 126 }; 127 128 int 129 tx3912video_match(struct device *parent, struct cfdata *cf, void *aux) 130 { 131 return (ATTACH_NORMAL); 132 } 133 134 void 135 tx3912video_attach(struct device *parent, struct device *self, void *aux) 136 { 137 struct tx3912video_softc *sc = (void *)self; 138 struct video_chip *chip; 139 const char *depth_print[] = { 140 [TX3912_VIDEOCTRL1_BITSEL_MONOCHROME] = "monochrome", 141 [TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE] = "2bit greyscale", 142 [TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE] = "4bit greyscale", 143 [TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR] = "8bit color" 144 }; 145 struct hpcfb_attach_args ha; 146 tx_chipset_tag_t tc; 147 txreg_t val; 148 int console; 149 150 sc->sc_console = console = cn_tab ? 0 : 1; 151 sc->sc_chip = chip = &tx3912video_chip; 152 153 /* print video module information */ 154 printf(": %s, frame buffer 0x%08x-0x%08x\n", 155 depth_print[(ffs(chip->vc_fbdepth) - 1) & 0x3], 156 (unsigned)chip->vc_fbpaddr, 157 (unsigned)(chip->vc_fbpaddr + chip->vc_fbsize)); 158 159 /* don't inverse VDAT[3:0] signal */ 160 tc = chip->vc_v; 161 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 162 val &= ~TX3912_VIDEOCTRL1_INVVID; 163 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 164 165 /* install default CLUT */ 166 tx3912video_clut_init(sc); 167 168 /* if serial console, power off video module */ 169 tx3912video_power(sc, 0, 0, (void *) 170 (console ? PWR_RESUME : PWR_SUSPEND)); 171 172 /* Add a hard power hook to power saving */ 173 sc->sc_powerhook = config_hook(CONFIG_HOOK_PMEVENT, 174 CONFIG_HOOK_PMEVENT_HARDPOWER, CONFIG_HOOK_SHARE, 175 tx3912video_power, sc); 176 if (sc->sc_powerhook == 0) 177 printf("WARNING unable to establish hard power hook"); 178 179 #ifdef TX3912VIDEO_DEBUG 180 /* attach debug draw routine (debugging use) */ 181 video_attach_drawfunc(sc->sc_chip); 182 tx_conf_register_video(tc, sc->sc_chip); 183 #endif 184 185 /* Attach frame buffer device */ 186 tx3912video_hpcfbinit(sc); 187 188 if (console && hpcfb_cnattach(&sc->sc_fbconf) != 0) { 189 panic("tx3912video_attach: can't init fb console"); 190 } 191 192 ha.ha_console = console; 193 ha.ha_accessops = &tx3912video_ha; 194 ha.ha_accessctx = sc; 195 ha.ha_curfbconf = 0; 196 ha.ha_nfbconf = 1; 197 ha.ha_fbconflist = &sc->sc_fbconf; 198 ha.ha_curdspconf = 0; 199 ha.ha_ndspconf = 1; 200 ha.ha_dspconflist = &sc->sc_dspconf; 201 202 config_found(self, &ha, hpcfbprint); 203 #if NBIVIDEO > 0 204 /* bivideo is no longer need */ 205 bivideo_dont_attach = 1; 206 #endif /* NBIVIDEO > 0 */ 207 } 208 209 int 210 tx3912video_power(void *ctx, int type, long id, void *msg) 211 { 212 struct tx3912video_softc *sc = ctx; 213 struct video_chip *chip = sc->sc_chip; 214 tx_chipset_tag_t tc = chip->vc_v; 215 int why = (int)msg; 216 txreg_t val; 217 218 switch (why) { 219 case PWR_RESUME: 220 if (!sc->sc_console) 221 return (0); /* serial console */ 222 223 DPRINTF(("%s: ON\n", sc->sc_dev.dv_xname)); 224 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 225 val |= (TX3912_VIDEOCTRL1_DISPON | TX3912_VIDEOCTRL1_ENVID); 226 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 227 break; 228 case PWR_SUSPEND: 229 /* FALLTHROUGH */ 230 case PWR_STANDBY: 231 DPRINTF(("%s: OFF\n", sc->sc_dev.dv_xname)); 232 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 233 val &= ~(TX3912_VIDEOCTRL1_DISPON | TX3912_VIDEOCTRL1_ENVID); 234 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 235 break; 236 } 237 238 return (0); 239 } 240 241 void 242 tx3912video_hpcfbinit(sc) 243 struct tx3912video_softc *sc; 244 { 245 struct video_chip *chip = sc->sc_chip; 246 struct hpcfb_fbconf *fb = &sc->sc_fbconf; 247 vaddr_t fbvaddr = (vaddr_t)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 248 249 memset(fb, 0, sizeof(struct hpcfb_fbconf)); 250 251 fb->hf_conf_index = 0; /* configuration index */ 252 fb->hf_nconfs = 1; /* how many configurations */ 253 strncpy(fb->hf_name, "TX3912 built-in video", HPCFB_MAXNAMELEN); 254 /* frame buffer name */ 255 strncpy(fb->hf_conf_name, "LCD", HPCFB_MAXNAMELEN); 256 /* configuration name */ 257 fb->hf_height = chip->vc_fbheight; 258 fb->hf_width = chip->vc_fbwidth; 259 fb->hf_baseaddr = (u_long)fbvaddr; 260 fb->hf_offset = (u_long)fbvaddr - 261 mips_ptob(mips_btop(fbvaddr)); 262 /* frame buffer start offset */ 263 fb->hf_bytes_per_line = (chip->vc_fbwidth * chip->vc_fbdepth) 264 / NBBY; 265 fb->hf_nplanes = 1; 266 fb->hf_bytes_per_plane = chip->vc_fbheight * fb->hf_bytes_per_line; 267 268 fb->hf_access_flags |= HPCFB_ACCESS_BYTE; 269 fb->hf_access_flags |= HPCFB_ACCESS_WORD; 270 fb->hf_access_flags |= HPCFB_ACCESS_DWORD; 271 if (video_reverse_color()) 272 fb->hf_access_flags |= HPCFB_ACCESS_REVERSE; 273 274 275 switch (chip->vc_fbdepth) { 276 default: 277 panic("tx3912video_hpcfbinit: not supported color depth\n"); 278 /* NOTREACHED */ 279 case 2: 280 fb->hf_class = HPCFB_CLASS_GRAYSCALE; 281 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 282 fb->hf_pack_width = 8; 283 fb->hf_pixels_per_pack = 4; 284 fb->hf_pixel_width = 2; 285 fb->hf_class_data_length = sizeof(struct hf_gray_tag); 286 /* reserved for future use */ 287 fb->hf_u.hf_gray.hf_flags = 0; 288 break; 289 case 8: 290 fb->hf_class = HPCFB_CLASS_INDEXCOLOR; 291 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 292 fb->hf_pack_width = 8; 293 fb->hf_pixels_per_pack = 1; 294 fb->hf_pixel_width = 8; 295 fb->hf_class_data_length = sizeof(struct hf_indexed_tag); 296 /* reserved for future use */ 297 fb->hf_u.hf_indexed.hf_flags = 0; 298 break; 299 } 300 } 301 302 int 303 tx3912video_init(paddr_t fb_start, paddr_t *fb_end) 304 { 305 struct video_chip *chip = &tx3912video_chip; 306 tx_chipset_tag_t tc; 307 txreg_t reg; 308 int fbdepth, reverse, error; 309 310 reverse = video_reverse_color(); 311 chip->vc_v = tc = tx_conf_get_tag(); 312 313 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 314 fbdepth = 1 << (TX3912_VIDEOCTRL1_BITSEL(reg)); 315 316 switch (fbdepth) { 317 case 2: 318 bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; 319 break; 320 case 4: 321 /* XXX should implement rasops4.c */ 322 fbdepth = 2; 323 bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; 324 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 325 TX3912_VIDEOCTRL1_BITSEL_CLR(reg); 326 reg = TX3912_VIDEOCTRL1_BITSEL_SET(reg, 327 TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE); 328 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 329 break; 330 case 8: 331 bootinfo->fb_type = reverse ? BIFB_D8_FF : BIFB_D8_00; 332 break; 333 } 334 335 chip->vc_fbdepth = fbdepth; 336 chip->vc_fbwidth = bootinfo->fb_width; 337 chip->vc_fbheight= bootinfo->fb_height; 338 339 /* Allocate framebuffer area */ 340 error = tx3912video_framebuffer_alloc(chip, fb_start, fb_end); 341 if (error != 0) 342 return (1); 343 344 #if notyet 345 tx3912video_resolution_init(chip); 346 #else 347 /* Use Windows CE setting. */ 348 #endif 349 /* Set DMA transfer address to VID module */ 350 tx3912video_framebuffer_init(chip); 351 352 /* Syncronize framebuffer addr to frame signal */ 353 tx3912video_reset(chip); 354 355 bootinfo->fb_line_bytes = (chip->vc_fbwidth * fbdepth) / NBBY; 356 bootinfo->fb_addr = (void *)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 357 358 return (0); 359 } 360 361 int 362 tx3912video_framebuffer_alloc(struct video_chip *chip, paddr_t fb_start, 363 paddr_t *fb_end /* buffer allocation hint */) 364 { 365 struct extent_fixed ex_fixed[10]; 366 struct extent *ex; 367 u_long addr, size; 368 int error; 369 370 /* calcurate frame buffer size */ 371 size = (chip->vc_fbwidth * chip->vc_fbheight * chip->vc_fbdepth) / 372 NBBY; 373 374 /* extent V-RAM region */ 375 ex = extent_create("Frame buffer address", fb_start, *fb_end, 376 0, (caddr_t)ex_fixed, sizeof ex_fixed, 377 EX_NOWAIT); 378 if (ex == 0) 379 return (1); 380 381 /* Allocate V-RAM area */ 382 error = extent_alloc_subregion(ex, fb_start, fb_start + size - 1, 383 size, TX3912_FRAMEBUFFER_ALIGNMENT, 384 TX3912_FRAMEBUFFER_BOUNDARY, EX_FAST|EX_NOWAIT, &addr); 385 extent_destroy(ex); 386 387 if (error != 0) 388 return (1); 389 390 chip->vc_fbpaddr = addr; 391 chip->vc_fbvaddr = MIPS_PHYS_TO_KSEG1(addr); 392 chip->vc_fbsize = size; 393 394 *fb_end = addr + size; 395 396 return (0); 397 } 398 399 void 400 tx3912video_framebuffer_init(struct video_chip *chip) 401 { 402 u_int32_t fb_addr, fb_size, vaddr, bank, base; 403 txreg_t reg; 404 tx_chipset_tag_t tc = chip->vc_v; 405 406 fb_addr = chip->vc_fbpaddr; 407 fb_size = chip->vc_fbsize; 408 409 /* XXX currently I don't set DFVAL, so force DF signal toggled on 410 * XXX each frame. */ 411 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 412 reg &= ~TX3912_VIDEOCTRL1_DFMODE; 413 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 414 415 /* Set DMA transfer start and end address */ 416 417 bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr); 418 base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr); 419 reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank); 420 /* Upper address counter */ 421 reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base); 422 tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg); 423 424 /* Lower address counter */ 425 base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size); 426 reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base); 427 428 /* Set DF-signal rate */ 429 reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/ 430 431 /* Set VIDDONE signal delay after FRAME signal */ 432 /* XXX not yet*/ 433 tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg); 434 435 /* Clear frame buffer */ 436 vaddr = MIPS_PHYS_TO_KSEG1(fb_addr); 437 memset((void*)vaddr, 0, fb_size); 438 } 439 440 void 441 tx3912video_resolution_init(struct video_chip *chip) 442 { 443 int h, v, split, bit8, horzval, lineval; 444 tx_chipset_tag_t tc = chip->vc_v; 445 txreg_t reg; 446 u_int32_t val; 447 448 h = chip->vc_fbwidth; 449 v = chip->vc_fbheight; 450 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 451 split = reg & TX3912_VIDEOCTRL1_DISPSPLIT; 452 bit8 = (TX3912_VIDEOCTRL1_BITSEL(reg) == 453 TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR); 454 val = TX3912_VIDEOCTRL1_BITSEL(reg); 455 456 if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) && !split) { 457 /* (LCD horizontal pixels / 8bit) * RGB - 1 */ 458 horzval = (h / 8) * 3 - 1; 459 } else { 460 horzval = h / 4 - 1; 461 } 462 lineval = (split ? v / 2 : v) - 1; 463 464 /* Video rate */ 465 /* XXX 466 * probably This value should be determined from DFINT and LCDINT 467 */ 468 reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1); 469 /* Horizontal size of LCD */ 470 reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval); 471 /* # of lines for the LCD */ 472 reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval); 473 474 tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg); 475 } 476 477 void 478 tx3912video_reset(struct video_chip *chip) 479 { 480 tx_chipset_tag_t tc = chip->vc_v; 481 txreg_t reg; 482 483 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 484 485 /* Disable video logic at end of this frame */ 486 reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME; 487 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 488 489 /* Wait for end of frame */ 490 delay(30 * 1000); 491 492 /* Make sure to disable video logic */ 493 reg &= ~TX3912_VIDEOCTRL1_ENVID; 494 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 495 496 delay(1000); 497 498 /* Enable video logic again */ 499 reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME; 500 reg |= TX3912_VIDEOCTRL1_ENVID; 501 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 502 503 delay(1000); 504 } 505 506 int 507 tx3912video_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 508 { 509 struct tx3912video_softc *sc = (struct tx3912video_softc *)v; 510 struct hpcfb_fbconf *fbconf; 511 struct hpcfb_dspconf *dspconf; 512 struct wsdisplay_cmap *cmap; 513 u_int8_t *r, *g, *b; 514 u_int32_t *rgb; 515 int idx, cnt, error; 516 517 switch (cmd) { 518 case WSDISPLAYIO_GETCMAP: 519 cmap = (struct wsdisplay_cmap*)data; 520 cnt = cmap->count; 521 idx = cmap->index; 522 523 if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR || 524 sc->sc_fbconf.hf_pack_width != 8 || 525 !LEGAL_CLUT_INDEX(idx) || 526 !LEGAL_CLUT_INDEX(idx + cnt -1)) { 527 return (EINVAL); 528 } 529 530 if (!uvm_useracc(cmap->red, cnt, B_WRITE) || 531 !uvm_useracc(cmap->green, cnt, B_WRITE) || 532 !uvm_useracc(cmap->blue, cnt, B_WRITE)) { 533 return (EFAULT); 534 } 535 536 error = cmap_work_alloc(&r, &g, &b, &rgb, cnt); 537 if (error != 0) { 538 cmap_work_free(r, g, b, rgb); 539 return (ENOMEM); 540 } 541 tx3912video_clut_get(sc, rgb, idx, cnt); 542 rgb24_decompose(rgb, r, g, b, cnt); 543 544 copyout(r, cmap->red, cnt); 545 copyout(g, cmap->green,cnt); 546 copyout(b, cmap->blue, cnt); 547 548 cmap_work_free(r, g, b, rgb); 549 550 return (0); 551 552 case WSDISPLAYIO_PUTCMAP: 553 /* 554 * TX3912 can't change CLUT index. R:G:B = 3:3:2 555 */ 556 return (0); 557 558 case HPCFBIO_GCONF: 559 fbconf = (struct hpcfb_fbconf *)data; 560 if (fbconf->hf_conf_index != 0 && 561 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 562 return (EINVAL); 563 } 564 *fbconf = sc->sc_fbconf; /* structure assignment */ 565 return (0); 566 567 case HPCFBIO_SCONF: 568 fbconf = (struct hpcfb_fbconf *)data; 569 if (fbconf->hf_conf_index != 0 && 570 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 571 return (EINVAL); 572 } 573 /* 574 * nothing to do because we have only one configration 575 */ 576 return (0); 577 578 case HPCFBIO_GDSPCONF: 579 dspconf = (struct hpcfb_dspconf *)data; 580 if ((dspconf->hd_unit_index != 0 && 581 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 582 (dspconf->hd_conf_index != 0 && 583 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 584 return (EINVAL); 585 } 586 *dspconf = sc->sc_dspconf; /* structure assignment */ 587 return (0); 588 589 case HPCFBIO_SDSPCONF: 590 dspconf = (struct hpcfb_dspconf *)data; 591 if ((dspconf->hd_unit_index != 0 && 592 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 593 (dspconf->hd_conf_index != 0 && 594 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 595 return (EINVAL); 596 } 597 /* 598 * nothing to do 599 * because we have only one unit and one configration 600 */ 601 return (0); 602 603 case HPCFBIO_GOP: 604 case HPCFBIO_SOP: 605 /* XXX not implemented yet */ 606 return (EINVAL); 607 } 608 609 return (EPASSTHROUGH); 610 } 611 612 paddr_t 613 tx3912video_mmap(void *ctx, off_t offset, int prot) 614 { 615 struct tx3912video_softc *sc = (struct tx3912video_softc *)ctx; 616 617 if (offset < 0 || (sc->sc_fbconf.hf_bytes_per_plane + 618 sc->sc_fbconf.hf_offset) < offset) { 619 return (-1); 620 } 621 622 return (mips_btop(sc->sc_chip->vc_fbpaddr + offset)); 623 } 624 625 /* 626 * CLUT staff 627 */ 628 static const struct { 629 int mul, div; 630 } dither_list [] = { 631 [TX3912_VIDEO_DITHER_DUTYCYCLE_1] = { 1, 1 }, 632 [TX3912_VIDEO_DITHER_DUTYCYCLE_6_7] = { 6, 7 }, 633 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_5] = { 4, 5 }, 634 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_4] = { 3, 4 }, 635 [TX3912_VIDEO_DITHER_DUTYCYCLE_5_7] = { 5, 7 }, 636 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_3] = { 2, 3 }, 637 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_5] = { 3, 5 }, 638 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_7] = { 4, 7 }, 639 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_4] = { 2, 4 }, 640 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_7] = { 3, 7 }, 641 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_5] = { 2, 5 }, 642 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_3] = { 1, 3 }, 643 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_7] = { 2, 7 }, 644 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_5] = { 1, 5 }, 645 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_7] = { 1, 7 }, 646 [TX3912_VIDEO_DITHER_DUTYCYCLE_0] = { 0, 1 } 647 }, *dlp; 648 649 static const int dither_level8[8] = { 650 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 651 TX3912_VIDEO_DITHER_DUTYCYCLE_2_7, 652 TX3912_VIDEO_DITHER_DUTYCYCLE_2_5, 653 TX3912_VIDEO_DITHER_DUTYCYCLE_2_4, 654 TX3912_VIDEO_DITHER_DUTYCYCLE_3_5, 655 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 656 TX3912_VIDEO_DITHER_DUTYCYCLE_4_5, 657 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 658 }; 659 660 static const int dither_level4[4] = { 661 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 662 TX3912_VIDEO_DITHER_DUTYCYCLE_1_3, 663 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 664 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 665 }; 666 667 static int 668 __get_color8(int luti) 669 { 670 KASSERT(luti >=0 && luti < 8); 671 dlp = &dither_list[dither_level8[luti]]; 672 673 return ((0xff * dlp->mul) / dlp->div); 674 } 675 676 static int 677 __get_color4(int luti) 678 { 679 KASSERT(luti >=0 && luti < 4); 680 dlp = &dither_list[dither_level4[luti]]; 681 682 return ((0xff * dlp->mul) / dlp->div); 683 } 684 685 void 686 tx3912video_clut_get(struct tx3912video_softc *sc, u_int32_t *rgb, int beg, 687 int cnt) 688 { 689 int i; 690 691 KASSERT(rgb); 692 KASSERT(LEGAL_CLUT_INDEX(beg)); 693 KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1)); 694 695 for (i = beg; i < beg + cnt; i++) { 696 *rgb++ = RGB24(__get_color8((i >> 5) & 0x7), 697 __get_color8((i >> 2) & 0x7), 698 __get_color4(i & 0x3)); 699 } 700 } 701 702 void 703 tx3912video_clut_install(void *ctx, struct rasops_info *ri) 704 { 705 struct tx3912video_softc *sc = ctx; 706 const int system_cmap[0x10] = { 707 TX3912VIDEO_BLACK, 708 TX3912VIDEO_RED, 709 TX3912VIDEO_GREEN, 710 TX3912VIDEO_YELLOW, 711 TX3912VIDEO_BLUE, 712 TX3912VIDEO_MAGENTA, 713 TX3912VIDEO_CYAN, 714 TX3912VIDEO_WHITE, 715 TX3912VIDEO_DARK_BLACK, 716 TX3912VIDEO_DARK_RED, 717 TX3912VIDEO_DARK_GREEN, 718 TX3912VIDEO_DARK_YELLOW, 719 TX3912VIDEO_DARK_BLUE, 720 TX3912VIDEO_DARK_MAGENTA, 721 TX3912VIDEO_DARK_CYAN, 722 TX3912VIDEO_DARK_WHITE, 723 }; 724 725 KASSERT(ri); 726 727 if (sc->sc_chip->vc_fbdepth == 8) { 728 /* XXX 2bit gray scale LUT not supported */ 729 memcpy(ri->ri_devcmap, system_cmap, sizeof system_cmap); 730 } 731 } 732 733 void 734 tx3912video_clut_init(struct tx3912video_softc *sc) 735 { 736 tx_chipset_tag_t tc = sc->sc_chip->vc_v; 737 738 if (sc->sc_chip->vc_fbdepth != 8) { 739 return; /* XXX 2bit gray scale LUT not supported */ 740 } 741 742 /* 743 * time-based dithering pattern (TOSHIBA recommended pattern) 744 */ 745 /* 2/3, 1/3 */ 746 tx_conf_write(tc, TX3912_VIDEOCTRL8_REG, 747 TX3912_VIDEOCTRL8_PAT2_3_DEFAULT); 748 /* 3/4, 2/4 */ 749 tx_conf_write(tc, TX3912_VIDEOCTRL9_REG, 750 (TX3912_VIDEOCTRL9_PAT3_4_DEFAULT << 16) | 751 TX3912_VIDEOCTRL9_PAT2_4_DEFAULT); 752 /* 4/5, 1/5 */ 753 tx_conf_write(tc, TX3912_VIDEOCTRL10_REG, 754 TX3912_VIDEOCTRL10_PAT4_5_DEFAULT); 755 /* 3/5, 2/5 */ 756 tx_conf_write(tc, TX3912_VIDEOCTRL11_REG, 757 TX3912_VIDEOCTRL11_PAT3_5_DEFAULT); 758 /* 6/7, 1/7 */ 759 tx_conf_write(tc, TX3912_VIDEOCTRL12_REG, 760 TX3912_VIDEOCTRL12_PAT6_7_DEFAULT); 761 /* 5/7, 2/7 */ 762 tx_conf_write(tc, TX3912_VIDEOCTRL13_REG, 763 TX3912_VIDEOCTRL13_PAT5_7_DEFAULT); 764 /* 4/7, 3/7 */ 765 tx_conf_write(tc, TX3912_VIDEOCTRL14_REG, 766 TX3912_VIDEOCTRL14_PAT4_7_DEFAULT); 767 768 /* 769 * dither-pattern look-up table. (selected by uch) 770 */ 771 /* red */ 772 tx_conf_write(tc, TX3912_VIDEOCTRL5_REG, 773 (dither_level8[7] << 28) | 774 (dither_level8[6] << 24) | 775 (dither_level8[5] << 20) | 776 (dither_level8[4] << 16) | 777 (dither_level8[3] << 12) | 778 (dither_level8[2] << 8) | 779 (dither_level8[1] << 4) | 780 (dither_level8[0] << 0)); 781 /* green */ 782 tx_conf_write(tc, TX3912_VIDEOCTRL6_REG, 783 (dither_level8[7] << 28) | 784 (dither_level8[6] << 24) | 785 (dither_level8[5] << 20) | 786 (dither_level8[4] << 16) | 787 (dither_level8[3] << 12) | 788 (dither_level8[2] << 8) | 789 (dither_level8[1] << 4) | 790 (dither_level8[0] << 0)); 791 /* blue (2bit gray scale also use this look-up table) */ 792 tx_conf_write(tc, TX3912_VIDEOCTRL7_REG, 793 (dither_level4[3] << 12) | 794 (dither_level4[2] << 8) | 795 (dither_level4[1] << 4) | 796 (dither_level4[0] << 0)); 797 798 tx3912video_reset(sc->sc_chip); 799 } 800