1 /* $NetBSD: tx39biu.c,v 1.6 2002/01/29 18:53:15 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_tx39_watchdogtimer.h" 40 #include "opt_tx39biu_debug.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <machine/bus.h> 47 #include <machine/debug.h> 48 49 #include <hpcmips/tx/tx39var.h> 50 #include <hpcmips/tx/tx39biureg.h> 51 #include <hpcmips/tx/txcsbusvar.h> 52 53 #ifdef TX39BIU_DEBUG 54 #define DPRINTF_ENABLE 55 #define DPRINTF_DEBUG tx39biu_debug 56 #endif 57 #include <machine/debug.h> 58 59 #define ISSET(x, s) ((x) & (1 << (s))) 60 #define ISSETPRINT(r, s, m) dbg_bitmask_print((u_int32_t)(r), \ 61 TX39_MEMCONFIG ## s ## _ ##m, #m) 62 63 int tx39biu_match(struct device *, struct cfdata *, void *); 64 void tx39biu_attach(struct device *, struct device *, void *); 65 void tx39biu_callback(struct device *); 66 int tx39biu_print(void *, const char *); 67 int tx39biu_intr(void *); 68 69 static void *__sc; /* XXX */ 70 #ifdef TX39BIU_DEBUG 71 void tx39biu_dump(tx_chipset_tag_t); 72 #endif 73 74 struct tx39biu_softc { 75 struct device sc_dev; 76 tx_chipset_tag_t sc_tc; 77 }; 78 79 struct cfattach tx39biu_ca = { 80 sizeof(struct tx39biu_softc), tx39biu_match, tx39biu_attach 81 }; 82 83 int 84 tx39biu_match(parent, cf, aux) 85 struct device *parent; 86 struct cfdata *cf; 87 void *aux; 88 { 89 return (ATTACH_NORMAL); 90 } 91 92 void 93 tx39biu_attach(parent, self, aux) 94 struct device *parent; 95 struct device *self; 96 void *aux; 97 { 98 struct txsim_attach_args *ta = aux; 99 struct tx39biu_softc *sc = (void*)self; 100 tx_chipset_tag_t tc; 101 #ifdef TX39_WATCHDOGTIMER 102 txreg_t reg; 103 #endif 104 105 sc->sc_tc = tc = ta->ta_tc; 106 printf("\n"); 107 #ifdef TX39BIU_DEBUG 108 tx39biu_dump(tc); 109 #endif 110 111 #ifdef TX39_WATCHDOGTIMER 112 /* 113 * CLRWRBUSERRINT Bus error connected CPU HwInt0 114 */ 115 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 116 reg |= TX39_MEMCONFIG4_ENWATCH; 117 reg = TX39_MEMCONFIG4_WATCHTIMEVAL_SET(reg, 0xf); 118 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg); 119 120 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 121 if (reg & TX39_MEMCONFIG4_ENWATCH) { 122 int i; 123 i = TX39_MEMCONFIG4_WATCHTIMEVAL(reg); 124 i = (1000 * (i + 1) * 64) / 36864; 125 printf("WatchDogTimerRate: %dus\n", i); 126 } 127 #endif 128 __sc = sc; 129 130 /* Clear watch dog timer interrupt */ 131 tx39biu_intr(sc); 132 133 /* 134 * Chip select virtual bridge 135 */ 136 config_defer(self, tx39biu_callback); 137 } 138 139 void 140 tx39biu_callback(self) 141 struct device *self; 142 { 143 struct tx39biu_softc *sc = (void*)self; 144 struct csbus_attach_args cba; 145 146 cba.cba_busname = "txcsbus"; 147 cba.cba_tc = sc->sc_tc; 148 config_found(self, &cba, tx39biu_print); 149 } 150 151 int 152 tx39biu_print(aux, pnp) 153 void *aux; 154 const char *pnp; 155 { 156 return (pnp ? QUIET : UNCONF); 157 } 158 159 int 160 tx39biu_intr(arg) 161 void *arg; 162 { 163 struct tx39biu_softc *sc = __sc; 164 tx_chipset_tag_t tc; 165 txreg_t reg; 166 167 if (!sc) { 168 return (0); 169 } 170 tc = sc->sc_tc; 171 /* Clear interrupt */ 172 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 173 reg |= TX39_MEMCONFIG4_CLRWRBUSERRINT; 174 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg); 175 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 176 reg &= ~TX39_MEMCONFIG4_CLRWRBUSERRINT; 177 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg); 178 179 return (0); 180 } 181 182 #ifdef TX39BIU_DEBUG 183 void 184 tx39biu_dump(tc) 185 tx_chipset_tag_t tc; 186 { 187 char *rowsel[] = {"18,17:9", "22,18,20,19,17:9", "20,22,21,19,17:9", 188 "22,23,21,19,17:9"}; 189 char *colsel[] = {"22,20,18,8:1", "19,18,8:2", "21,20,18,8:2", 190 "23,22,20,18,8:2", "24,22,20,18,8:2", 191 "18,p,X,8:0","22,p,X,21,8:0", "18,p,X,21,8:1", 192 "22,p,X,23,21,8:1", "24,23,21,8:2"}; 193 txreg_t reg; 194 int i; 195 /* 196 * Memory config 0 register 197 */ 198 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 199 printf(" config0:"); 200 ISSETPRINT(reg, 0, ENDCLKOUTTRI); 201 ISSETPRINT(reg, 0, DISDQMINIT); 202 ISSETPRINT(reg, 0, ENSDRAMPD); 203 ISSETPRINT(reg, 0, SHOWDINO); 204 ISSETPRINT(reg, 0, ENRMAP2); 205 ISSETPRINT(reg, 0, ENRMAP1); 206 ISSETPRINT(reg, 0, ENWRINPAGE); 207 ISSETPRINT(reg, 0, ENCS3USER); 208 ISSETPRINT(reg, 0, ENCS2USER); 209 ISSETPRINT(reg, 0, ENCS1USER); 210 ISSETPRINT(reg, 0, ENCS1DRAM); 211 ISSETPRINT(reg, 0, CS3SIZE); 212 ISSETPRINT(reg, 0, CS2SIZE); 213 ISSETPRINT(reg, 0, CS1SIZE); 214 ISSETPRINT(reg, 0, CS0SIZE); 215 printf("\n"); 216 for (i = 0; i < 2; i++) { 217 int r, c; 218 printf(" BANK%d: ", i); 219 switch (i ? TX39_MEMCONFIG0_BANK1CONF(reg) 220 : TX39_MEMCONFIG0_BANK0CONF(reg)) { 221 case TX39_MEMCONFIG0_BANKCONF_16BITSDRAM: 222 printf("16bit SDRAM"); 223 break; 224 case TX39_MEMCONFIG0_BANKCONF_8BITSDRAM: 225 printf("8bit SDRAM"); 226 break; 227 case TX39_MEMCONFIG0_BANKCONF_32BITSDHDRAM: 228 printf("32bit DRAM/HDRAM"); 229 break; 230 case TX39_MEMCONFIG0_BANKCONF_16BITSDHDRAM: 231 printf("16bit DRAM/HDRAM"); 232 break; 233 } 234 if (i == 1) { 235 r = TX39_MEMCONFIG0_ROWSEL1(reg); 236 c = TX39_MEMCONFIG0_COLSEL1(reg); 237 } else { 238 r = TX39_MEMCONFIG0_ROWSEL0(reg); 239 c = TX39_MEMCONFIG0_COLSEL0(reg); 240 } 241 printf(" ROW %s COL %s\n", rowsel[r], colsel[c]); 242 } 243 244 /* 245 * Memory config 3 register 246 */ 247 printf(" config3:"); 248 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 249 #ifdef TX391X 250 ISSETPRINT(reg, 3, ENMCS3PAGE); 251 ISSETPRINT(reg, 3, ENMCS2PAGE); 252 ISSETPRINT(reg, 3, ENMCS1PAGE); 253 ISSETPRINT(reg, 3, ENMCS0PAGE); 254 #endif /* TX391X */ 255 ISSETPRINT(reg, 3, ENCS3PAGE); 256 ISSETPRINT(reg, 3, ENCS2PAGE); 257 ISSETPRINT(reg, 3, ENCS1PAGE); 258 ISSETPRINT(reg, 3, ENCS0PAGE); 259 ISSETPRINT(reg, 3, CARD2WAITEN); 260 ISSETPRINT(reg, 3, CARD1WAITEN); 261 ISSETPRINT(reg, 3, CARD2IOEN); 262 ISSETPRINT(reg, 3, CARD1IOEN); 263 #ifdef TX391X 264 ISSETPRINT(reg, 3, PORT8SEL); 265 #endif /* TX391X */ 266 #ifdef TX392X 267 ISSETPRINT(reg, 3, CARD2_8SEL); 268 ISSETPRINT(reg, 3, CARD1_8SEL); 269 #endif /* TX392X */ 270 271 printf("\n"); 272 273 /* 274 * Memory config 4 register 275 */ 276 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 277 printf(" config4:"); 278 ISSETPRINT(reg, 4, ENBANK1HDRAM); 279 ISSETPRINT(reg, 4, ENBANK0HDRAM); 280 ISSETPRINT(reg, 4, ENARB); 281 ISSETPRINT(reg, 4, DISSNOOP); 282 ISSETPRINT(reg, 4, CLRWRBUSERRINT); 283 ISSETPRINT(reg, 4, ENBANK1OPT); 284 ISSETPRINT(reg, 4, ENBANK0OPT); 285 ISSETPRINT(reg, 4, ENWATCH); 286 ISSETPRINT(reg, 4, MEMPOWERDOWN); 287 ISSETPRINT(reg, 4, ENRFSH1); 288 ISSETPRINT(reg, 4, ENRFSH0); 289 if (reg & TX39_MEMCONFIG4_ENWATCH) { 290 i = TX39_MEMCONFIG4_WATCHTIMEVAL(reg); 291 i = (1000 * (i + 1) * 64) / 36864; 292 printf("WatchDogTimerRate: %dus", i); 293 } 294 printf("\n"); 295 } 296 #endif /* TX39BIU_DEBUG */ 297