1 /* $NetBSD: tx39biu.c,v 1.8 2002/10/02 05:26:49 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_tx39_watchdogtimer.h" 40 #include "opt_tx39biu_debug.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <machine/bus.h> 47 #include <machine/debug.h> 48 49 #include <hpcmips/tx/tx39var.h> 50 #include <hpcmips/tx/tx39biureg.h> 51 #include <hpcmips/tx/txcsbusvar.h> 52 53 #ifdef TX39BIU_DEBUG 54 #define DPRINTF_ENABLE 55 #define DPRINTF_DEBUG tx39biu_debug 56 #endif 57 #include <machine/debug.h> 58 59 #define ISSET(x, s) ((x) & (1 << (s))) 60 #define ISSETPRINT(r, s, m) dbg_bitmask_print((u_int32_t)(r), \ 61 TX39_MEMCONFIG ## s ## _ ##m, #m) 62 63 int tx39biu_match(struct device *, struct cfdata *, void *); 64 void tx39biu_attach(struct device *, struct device *, void *); 65 void tx39biu_callback(struct device *); 66 int tx39biu_print(void *, const char *); 67 int tx39biu_intr(void *); 68 69 static void *__sc; /* XXX */ 70 #ifdef TX39BIU_DEBUG 71 void tx39biu_dump(tx_chipset_tag_t); 72 #endif 73 74 struct tx39biu_softc { 75 struct device sc_dev; 76 tx_chipset_tag_t sc_tc; 77 }; 78 79 CFATTACH_DECL(tx39biu, sizeof(struct tx39biu_softc), 80 tx39biu_match, tx39biu_attach, NULL, NULL); 81 82 int 83 tx39biu_match(parent, cf, aux) 84 struct device *parent; 85 struct cfdata *cf; 86 void *aux; 87 { 88 return (ATTACH_NORMAL); 89 } 90 91 void 92 tx39biu_attach(parent, self, aux) 93 struct device *parent; 94 struct device *self; 95 void *aux; 96 { 97 struct txsim_attach_args *ta = aux; 98 struct tx39biu_softc *sc = (void*)self; 99 tx_chipset_tag_t tc; 100 #ifdef TX39_WATCHDOGTIMER 101 txreg_t reg; 102 #endif 103 104 sc->sc_tc = tc = ta->ta_tc; 105 printf("\n"); 106 #ifdef TX39BIU_DEBUG 107 tx39biu_dump(tc); 108 #endif 109 110 #ifdef TX39_WATCHDOGTIMER 111 /* 112 * CLRWRBUSERRINT Bus error connected CPU HwInt0 113 */ 114 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 115 reg |= TX39_MEMCONFIG4_ENWATCH; 116 reg = TX39_MEMCONFIG4_WATCHTIMEVAL_SET(reg, 0xf); 117 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg); 118 119 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 120 if (reg & TX39_MEMCONFIG4_ENWATCH) { 121 int i; 122 i = TX39_MEMCONFIG4_WATCHTIMEVAL(reg); 123 i = (1000 * (i + 1) * 64) / 36864; 124 printf("WatchDogTimerRate: %dus\n", i); 125 } 126 #endif 127 __sc = sc; 128 129 /* Clear watch dog timer interrupt */ 130 tx39biu_intr(sc); 131 132 /* 133 * Chip select virtual bridge 134 */ 135 config_defer(self, tx39biu_callback); 136 } 137 138 void 139 tx39biu_callback(self) 140 struct device *self; 141 { 142 struct tx39biu_softc *sc = (void*)self; 143 struct csbus_attach_args cba; 144 145 cba.cba_busname = "txcsbus"; 146 cba.cba_tc = sc->sc_tc; 147 config_found(self, &cba, tx39biu_print); 148 } 149 150 int 151 tx39biu_print(aux, pnp) 152 void *aux; 153 const char *pnp; 154 { 155 return (pnp ? QUIET : UNCONF); 156 } 157 158 int 159 tx39biu_intr(arg) 160 void *arg; 161 { 162 struct tx39biu_softc *sc = __sc; 163 tx_chipset_tag_t tc; 164 txreg_t reg; 165 166 if (!sc) { 167 return (0); 168 } 169 tc = sc->sc_tc; 170 /* Clear interrupt */ 171 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 172 reg |= TX39_MEMCONFIG4_CLRWRBUSERRINT; 173 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg); 174 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 175 reg &= ~TX39_MEMCONFIG4_CLRWRBUSERRINT; 176 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg); 177 178 return (0); 179 } 180 181 #ifdef TX39BIU_DEBUG 182 void 183 tx39biu_dump(tc) 184 tx_chipset_tag_t tc; 185 { 186 char *rowsel[] = {"18,17:9", "22,18,20,19,17:9", "20,22,21,19,17:9", 187 "22,23,21,19,17:9"}; 188 char *colsel[] = {"22,20,18,8:1", "19,18,8:2", "21,20,18,8:2", 189 "23,22,20,18,8:2", "24,22,20,18,8:2", 190 "18,p,X,8:0","22,p,X,21,8:0", "18,p,X,21,8:1", 191 "22,p,X,23,21,8:1", "24,23,21,8:2"}; 192 txreg_t reg; 193 int i; 194 /* 195 * Memory config 0 register 196 */ 197 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 198 printf(" config0:"); 199 ISSETPRINT(reg, 0, ENDCLKOUTTRI); 200 ISSETPRINT(reg, 0, DISDQMINIT); 201 ISSETPRINT(reg, 0, ENSDRAMPD); 202 ISSETPRINT(reg, 0, SHOWDINO); 203 ISSETPRINT(reg, 0, ENRMAP2); 204 ISSETPRINT(reg, 0, ENRMAP1); 205 ISSETPRINT(reg, 0, ENWRINPAGE); 206 ISSETPRINT(reg, 0, ENCS3USER); 207 ISSETPRINT(reg, 0, ENCS2USER); 208 ISSETPRINT(reg, 0, ENCS1USER); 209 ISSETPRINT(reg, 0, ENCS1DRAM); 210 ISSETPRINT(reg, 0, CS3SIZE); 211 ISSETPRINT(reg, 0, CS2SIZE); 212 ISSETPRINT(reg, 0, CS1SIZE); 213 ISSETPRINT(reg, 0, CS0SIZE); 214 printf("\n"); 215 for (i = 0; i < 2; i++) { 216 int r, c; 217 printf(" BANK%d: ", i); 218 switch (i ? TX39_MEMCONFIG0_BANK1CONF(reg) 219 : TX39_MEMCONFIG0_BANK0CONF(reg)) { 220 case TX39_MEMCONFIG0_BANKCONF_16BITSDRAM: 221 printf("16bit SDRAM"); 222 break; 223 case TX39_MEMCONFIG0_BANKCONF_8BITSDRAM: 224 printf("8bit SDRAM"); 225 break; 226 case TX39_MEMCONFIG0_BANKCONF_32BITSDHDRAM: 227 printf("32bit DRAM/HDRAM"); 228 break; 229 case TX39_MEMCONFIG0_BANKCONF_16BITSDHDRAM: 230 printf("16bit DRAM/HDRAM"); 231 break; 232 } 233 if (i == 1) { 234 r = TX39_MEMCONFIG0_ROWSEL1(reg); 235 c = TX39_MEMCONFIG0_COLSEL1(reg); 236 } else { 237 r = TX39_MEMCONFIG0_ROWSEL0(reg); 238 c = TX39_MEMCONFIG0_COLSEL0(reg); 239 } 240 printf(" ROW %s COL %s\n", rowsel[r], colsel[c]); 241 } 242 243 /* 244 * Memory config 3 register 245 */ 246 printf(" config3:"); 247 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 248 #ifdef TX391X 249 ISSETPRINT(reg, 3, ENMCS3PAGE); 250 ISSETPRINT(reg, 3, ENMCS2PAGE); 251 ISSETPRINT(reg, 3, ENMCS1PAGE); 252 ISSETPRINT(reg, 3, ENMCS0PAGE); 253 #endif /* TX391X */ 254 ISSETPRINT(reg, 3, ENCS3PAGE); 255 ISSETPRINT(reg, 3, ENCS2PAGE); 256 ISSETPRINT(reg, 3, ENCS1PAGE); 257 ISSETPRINT(reg, 3, ENCS0PAGE); 258 ISSETPRINT(reg, 3, CARD2WAITEN); 259 ISSETPRINT(reg, 3, CARD1WAITEN); 260 ISSETPRINT(reg, 3, CARD2IOEN); 261 ISSETPRINT(reg, 3, CARD1IOEN); 262 #ifdef TX391X 263 ISSETPRINT(reg, 3, PORT8SEL); 264 #endif /* TX391X */ 265 #ifdef TX392X 266 ISSETPRINT(reg, 3, CARD2_8SEL); 267 ISSETPRINT(reg, 3, CARD1_8SEL); 268 #endif /* TX392X */ 269 270 printf("\n"); 271 272 /* 273 * Memory config 4 register 274 */ 275 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 276 printf(" config4:"); 277 ISSETPRINT(reg, 4, ENBANK1HDRAM); 278 ISSETPRINT(reg, 4, ENBANK0HDRAM); 279 ISSETPRINT(reg, 4, ENARB); 280 ISSETPRINT(reg, 4, DISSNOOP); 281 ISSETPRINT(reg, 4, CLRWRBUSERRINT); 282 ISSETPRINT(reg, 4, ENBANK1OPT); 283 ISSETPRINT(reg, 4, ENBANK0OPT); 284 ISSETPRINT(reg, 4, ENWATCH); 285 ISSETPRINT(reg, 4, MEMPOWERDOWN); 286 ISSETPRINT(reg, 4, ENRFSH1); 287 ISSETPRINT(reg, 4, ENRFSH0); 288 if (reg & TX39_MEMCONFIG4_ENWATCH) { 289 i = TX39_MEMCONFIG4_WATCHTIMEVAL(reg); 290 i = (1000 * (i + 1) * 64) / 36864; 291 printf("WatchDogTimerRate: %dus", i); 292 } 293 printf("\n"); 294 } 295 #endif /* TX39BIU_DEBUG */ 296