1 /* $NetBSD: rtcreg.h,v 1.8 2002/02/10 14:36:52 sato Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 Shin Takemura. All rights reserved. 5 * Copyright (c) 1999-2001 SATO Kazumi. All rights reserved. 6 * Copyright (c) 1999 PocketBSD Project. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the PocketBSD project 19 * and its contributors. 20 * 4. Neither the name of the project nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #define SECMIN ((unsigned)60) /* seconds per minute */ 39 #define SECHOUR ((unsigned)(60*SECMIN)) /* seconds per hour */ 40 41 #define SEC2MIN ((unsigned)60/2) /* 2seconds per minute */ 42 #define SEC2HOUR ((unsigned)(60*SECMIN)/2) /* 2seconds per hour */ 43 #define SEC2DAY ((unsigned)(24*SECHOUR)/2) /* 2seconds per day */ 44 #define SEC2YR ((unsigned)(365*SECDAY)/2) /* 2seconds per common year */ 45 46 #define YRREF 1999 47 #define MREF 1 48 #define DREF 1 49 50 #ifndef YBASE 51 #define YBASE 1900 52 #endif 53 54 #define EPOCHOFF 0 /* epoch offset */ 55 #ifndef EPOCHYEAR 56 #define EPOCHYEAR 1850 /* XXX */ /* WINCE epoch year */ 57 #endif 58 #define EPOCHMONTH 1 /* WINCE epoch month of year */ 59 #define EPOCHDATE 1 /* WINCE epoch date of month */ 60 61 #define LEAPYEAR4(year) ((((year) % 4) == 0 && ((year) % 100) != 0) || ((year%400)) == 0) 62 #define LEAPYEAR2(year) (((year) % 4) == 0) 63 64 /* 65 * RTC (Real Time Clock Unit) Registers definitions. 66 * start 0x0B0000C0 (Vr4102-4121) 67 * start 0x0F000100 (Vr4122-4131) 68 * start 0x0B0000C0 (Vr4181) 69 */ 70 #define RTC_NO_REG_W 0xffffffff 71 72 #define ETIME_L_REG_W 0x000 /* Elapsed Time L */ 73 #define ETIME_M_REG_W 0x002 /* Elapsed Time M */ 74 #define ETIME_H_REG_W 0x004 /* Elapsed Time H */ 75 76 #define ETIME_L_HZ 0x8000 /* 1 HZ */ 77 78 79 #define ECMP_L_REG_W 0x008 /* Elapsed Compare L */ 80 #define ECMP_M_REG_W 0x00a /* Elapsed Compare M */ 81 #define ECMP_H_REG_W 0x00c /* Elapsed Compare H */ 82 83 84 #define RTCL1_L_REG_W 0x010 /* RTC Long 1 L */ 85 #define RTCL1_H_REG_W 0x012 /* RTC Long 1 H */ 86 87 #define RTCL1_L_HZ 0x8000 /* 1 HZ */ 88 89 90 #define RTCL1_CNT_L_REG_W 0x014 /* RTC Long 1 Count L */ 91 #define RTCL1_CNT_H_REG_W 0x016 /* RTC Long 1 Count H */ 92 93 94 #define RTCL2_L_REG_W 0x018 /* RTC Long 2 L */ 95 #define RTCL2_H_REG_W 0x01a /* RTC Long 2 H */ 96 97 #define RTCL2_L_HZ 0x8000 /* 1 HZ */ 98 99 100 #define RTCL2_CNT_L_REG_W 0x01c /* RTC Long 2 Count L */ 101 #define RTCL2_CNT_H_REG_W 0x01e /* RTC Long 2 Count H */ 102 103 104 #define VR4102_TCLK_L_REG_W 0x100 /* TCLK L */ 105 #define VR4102_TCLK_H_REG_W 0x102 /* TCLK H */ 106 #define VR4122_TCLK_L_REG_W 0x020 /* TCLK L */ 107 #define VR4122_TCLK_H_REG_W 0x022 /* TCLK H */ 108 #if defined SINGLE_VRIP_BASE 109 #if defined VRGROUP_4102_4121 110 #define TCLK_L_REG_W VR4102_TCLK_L_REG_W /* TCLK L */ 111 #define TCLK_H_REG_W VR4102_TCLK_H_REG_W /* TCLK H */ 112 #endif /* VRGROUP_4102_4121 */ 113 #if defined VRGROUP_4122_4131 114 #define TCLK_L_REG_W VR4122_TCLK_L_REG_W /* TCLK L */ 115 #define TCLK_H_REG_W VR4122_TCLK_H_REG_W /* TCLK H */ 116 #endif /* VRGROUP_4122_4131 */ 117 #if defined VRGROUP_4181 118 #define TCLK_L_REG_W RTC_NO_REG_W 119 #define TCLK_H_REG_W RTC_NO_REG_W 120 #endif /* VRGROUP_4181 */ 121 #endif /* defined SINGLE_VRIP_BASE */ 122 123 124 #define VR4102_TCLK_CNT_L_REG_W 0x104 /* TCLK Count L */ 125 #define VR4102_TCLK_CNT_H_REG_W 0x106 /* TCLK Count H */ 126 #define VR4122_TCLK_CNT_L_REG_W 0x024 /* TCLK Count L */ 127 #define VR4122_TCLK_CNT_H_REG_W 0x026 /* TCLK Count H */ 128 #if defined SINGLE_VRIP_BASE 129 #if defined VRGROUP_4102_4121 130 #define TCLK_CNT_L_REG_W VR4102_TCLK_CNT_L_REG_W /* TCLK Count L */ 131 #define TCLK_CNT_H_REG_W VR4102_TCLK_CNT_L_REG_W /* TCLK Count H */ 132 #endif /* VRGROUP_4102_4121 */ 133 #if defined VRGROUP_4122_4131 134 #define TCLK_CNT_L_REG_W VR4122_TCLK_CNT_L_REG_W /* TCLK Count L */ 135 #define TCLK_CNT_H_REG_W VR4122_TCLK_CNT_H_REG_W /* TCLK Count H */ 136 #endif /* VRGROUP_4122_4131 */ 137 #if defined VRGROUP_4181 138 #define TCLK_CNT_L_REG_W RTC_NO_REG_W 139 #define TCLK_CNT_H_REG_W RTC_NO_REG_W 140 #endif /* VRGROUP_4181 */ 141 #endif /* defined SINGLE_VRIP_BASE */ 142 143 144 #define VR4102_RTCINT_REG_W 0x11e /* RTC intr reg. */ 145 #define VR4122_RTCINT_REG_W 0x03e /* RTC intr reg. */ 146 #define VR4181_RTCINT_REG_W 0x11e /* RTC intr reg. */ 147 #if defined SINGLE_VRIP_BASE 148 #if defined VRGROUP_4102_4121 149 #define RTCINT_REG_W VR4102_RTCINT_REG_W /* RTC intr reg. */ 150 #endif /* VRGROUP_4102_4121 */ 151 #if defined VRGROUP_4122_4131 152 #define RTCINT_REG_W VR4122_RTCINT_REG_W /* RTC intr reg. */ 153 #endif /* VRGROUP_4122 */ 154 #if defined VRGROUP_4181 155 #define RTCINT_REG_W VR4181_RTCINT_REG_W /* RTC intr reg. */ 156 #endif /* VRGROUP_4181 */ 157 #endif /* defined SINGLE_VRIP_BASE */ 158 159 #define RTCINT_TCLOCK (1<<3) /* TClock */ 160 #define RTCINT_RTCLONG2 (1<<2) /* RTC Long 2 */ 161 #define RTCINT_RTCLONG1 (1<<1) /* RTC Long 1 */ 162 #define RTCINT_ELAPSED (1) /* Elapsed time */ 163 #define RTCINT_ALL (RTCINT_TCLOCK|RTCINT_RTCLONG2|RTCINT_RTCLONG1|RTCINT_ELAPSED) 164 165 /* END rtcreg.h */ 166