1 /* 2 * Copyright (c) 2001 HAMAJIMA Katsuomi. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include <sys/param.h> 27 #include <sys/systm.h> 28 #include <sys/device.h> 29 30 #include <uvm/uvm_extern.h> 31 32 #include <machine/cpu.h> 33 #include <machine/bus.h> 34 #include <machine/bus_dma_hpcmips.h> 35 36 #include <hpcmips/vr/vripif.h> 37 #include <hpcmips/vr/dcureg.h> 38 39 #ifdef VRDCU_DEBUG 40 int vrdcu_debug = VRDCU_DEBUG; 41 #define DPRINTFN(n,x) if (vrdcu_debug>(n)) printf x; 42 #else 43 #define DPRINTFN(n,x) 44 #endif 45 46 struct vrdcu_softc { 47 struct device sc_dev; 48 bus_space_tag_t sc_iot; 49 bus_space_handle_t sc_ioh; 50 struct vrdcu_chipset_tag sc_chipset; 51 int sc_status; /* DMA status */ 52 }; 53 54 int vrdcu_match(struct device *, struct cfdata *, void *); 55 void vrdcu_attach(struct device *, struct device *, void *); 56 57 CFATTACH_DECL(vrdcu, sizeof(struct vrdcu_softc), 58 vrdcu_match, vrdcu_attach, NULL, NULL); 59 60 int vrdcu_enable_aiuin(vrdcu_chipset_tag_t); 61 int vrdcu_enable_aiuout(vrdcu_chipset_tag_t); 62 int vrdcu_enable_fir(vrdcu_chipset_tag_t); 63 void vrdcu_disable(vrdcu_chipset_tag_t); 64 void vrdcu_fir_direction(vrdcu_chipset_tag_t, int); 65 int _vrdcu_dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t, 66 bus_size_t, bus_dma_segment_t *, int, int *, int); 67 68 struct bus_dma_tag vrdcu_bus_dma_tag = { 69 NULL, 70 { 71 _hpcmips_bd_map_create, 72 _hpcmips_bd_map_destroy, 73 _hpcmips_bd_map_load, 74 _hpcmips_bd_map_load_mbuf, 75 _hpcmips_bd_map_load_uio, 76 _hpcmips_bd_map_load_raw, 77 _hpcmips_bd_map_unload, 78 _hpcmips_bd_map_sync, 79 _vrdcu_dmamem_alloc, 80 _hpcmips_bd_mem_free, 81 _hpcmips_bd_mem_map, 82 _hpcmips_bd_mem_unmap, 83 _hpcmips_bd_mem_mmap, 84 }, 85 }; 86 87 int 88 vrdcu_match(struct device *parent, struct cfdata *cf, void *aux) 89 { 90 return 2; /* 1st attach group of vrip */ 91 } 92 93 void 94 vrdcu_attach(struct device *parent, struct device *self, void *aux) 95 { 96 struct vrip_attach_args *va = aux; 97 struct vrdcu_softc *sc = (void*)self; 98 99 sc->sc_iot = va->va_iot; 100 sc->sc_chipset.dc_sc = sc; 101 sc->sc_chipset.dc_enable_aiuin = vrdcu_enable_aiuin; 102 sc->sc_chipset.dc_enable_aiuout = vrdcu_enable_aiuout; 103 sc->sc_chipset.dc_enable_fir = vrdcu_enable_fir; 104 sc->sc_chipset.dc_disable = vrdcu_disable; 105 sc->sc_chipset.dc_fir_direction = vrdcu_fir_direction; 106 107 if (bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 108 0 /* no flags */, &sc->sc_ioh)) { 109 printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname); 110 return; 111 } 112 printf("\n"); 113 vrip_register_dcu(va->va_vc, &sc->sc_chipset); 114 115 sc->sc_status = DMASDS; 116 /* reset DCU */ 117 bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMARST_REG_W, DMARST); 118 } 119 120 int 121 vrdcu_enable_aiuin(vrdcu_chipset_tag_t dc) 122 { 123 struct vrdcu_softc *sc = dc->dc_sc; 124 int mask; 125 126 DPRINTFN(1, ("vrdcu_enable_aiuin\n")); 127 128 if (sc->sc_status){ 129 mask = bus_space_read_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W); 130 if (mask & DMAMSKAIN) { 131 DPRINTFN(0, ("vrdcu_enable_aiuin: already enabled\n")); 132 return 0; 133 } else { 134 DPRINTFN(0, ("vrdcu_enable_aiuin: device busy\n")); 135 return EBUSY; 136 } 137 } 138 sc->sc_status = DMASEN; 139 bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W, DMAMSKAIN); 140 bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMASEN_REG_W, sc->sc_status); 141 return 0; 142 } 143 144 int 145 vrdcu_enable_aiuout(vrdcu_chipset_tag_t dc) 146 { 147 struct vrdcu_softc *sc = dc->dc_sc; 148 int mask; 149 150 DPRINTFN(1, ("vrdcu_enable_aiuout\n")); 151 152 if (sc->sc_status){ 153 mask = bus_space_read_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W); 154 if (mask & DMAMSKAOUT) { 155 DPRINTFN(0, ("vrdcu_enable_aiuout: already enabled\n")); 156 return 0; 157 } else { 158 DPRINTFN(0, ("vrdcu_enable_aiuout: device busy\n")); 159 return EBUSY; 160 } 161 } 162 sc->sc_status = DMASEN; 163 bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W, DMAMSKAOUT); 164 bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMASEN_REG_W, sc->sc_status); 165 return 0; 166 } 167 168 int 169 vrdcu_enable_fir(vrdcu_chipset_tag_t dc) 170 { 171 struct vrdcu_softc *sc = dc->dc_sc; 172 int mask; 173 174 DPRINTFN(1, ("vrdcu_enable_fir\n")); 175 176 if (sc->sc_status){ 177 mask = bus_space_read_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W); 178 if (mask & DMAMSKFOUT) { 179 DPRINTFN(0, ("vrdcu_enable_fir: already enabled\n")); 180 return 0; 181 } else { 182 DPRINTFN(0, ("vrdcu_enable_fir: device busy\n")); 183 return EBUSY; 184 } 185 } 186 sc->sc_status = DMASEN; 187 bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W, DMAMSKFOUT); 188 bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMASEN_REG_W, sc->sc_status); 189 return 0; 190 } 191 192 void 193 vrdcu_disable(vrdcu_chipset_tag_t dc) 194 { 195 struct vrdcu_softc *sc = dc->dc_sc; 196 197 DPRINTFN(1, ("vrdcu_disable\n")); 198 199 sc->sc_status = DMASDS; 200 bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMASEN_REG_W, sc->sc_status); 201 } 202 203 void 204 vrdcu_fir_direction(vrdcu_chipset_tag_t dc, int dir) 205 { 206 struct vrdcu_softc *sc = dc->dc_sc; 207 208 DPRINTFN(1, ("vrdcu_fir_direction: dir %d\n", dir)); 209 210 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 211 DMATD_REG_W, dir & DMATDMASK); 212 } 213 214 int 215 _vrdcu_dmamem_alloc(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment, 216 bus_size_t boundary, bus_dma_segment_t *segs, 217 int nsegs, int *rsegs, int flags) 218 { 219 extern paddr_t avail_start, avail_end; /* XXX */ 220 paddr_t high; 221 222 DPRINTFN(1, ("_vrdcu_dmamem_alloc\n")); 223 224 high = (avail_end < VRDMAAU_BOUNCE_THRESHOLD ? 225 avail_end : VRDMAAU_BOUNCE_THRESHOLD) - PAGE_SIZE; 226 alignment = alignment > VRDMAAU_ALIGNMENT ? 227 alignment : VRDMAAU_ALIGNMENT; 228 229 return _hpcmips_bd_mem_alloc_range(t, size, alignment, boundary, 230 segs, nsegs, rsegs, flags, 231 avail_start, high); 232 } 233